commit a502322188111ed1219db940b8bcdf11dfe4c366 Author: jeon Date: Tue Jun 16 09:29:03 2026 +0900 chore: HERV 통합 저장소 재초기화 커밋 손상된 .git 히스토리(missing tree)로 재초기화 후 작업트리 전체 커밋. .claude/ 만 제외(로컬 에이전트 설정). 구 저장소 백업(.git_corrupt_backup/) 포함. Co-Authored-By: Claude Opus 4.8 (1M context) diff --git a/.git_corrupt_backup/COMMIT_EDITMSG b/.git_corrupt_backup/COMMIT_EDITMSG new file mode 100644 index 0000000..c82d4a0 --- /dev/null +++ b/.git_corrupt_backup/COMMIT_EDITMSG @@ -0,0 +1,9 @@ +chore: HERV 통합 저장소 초기 커밋 + +- 펌웨어(program), C# 대시보드(TestProgram), 시뮬레이터(Simulator), + 프로토콜/문서(Protocol, doc) 전체를 단일 저장소로 통합 +- program 폴더의 별도 git 저장소를 제거하고 통합 저장소에 흡수 +- 빌드 산출물(program/build, bin/obj, *.o/.elf/.bin/.hex 등) .gitignore 처리 +- 사내 Synology NAS Git 원격 연결 예정 + +Co-Authored-By: Claude Opus 4.8 (1M context) diff --git a/.git_corrupt_backup/HEAD b/.git_corrupt_backup/HEAD new file mode 100644 index 0000000..b870d82 --- /dev/null +++ b/.git_corrupt_backup/HEAD @@ -0,0 +1 @@ +ref: refs/heads/main diff --git a/.git_corrupt_backup/config b/.git_corrupt_backup/config new file mode 100644 index 0000000..fe75c3b --- /dev/null +++ b/.git_corrupt_backup/config @@ -0,0 +1,10 @@ +[core] + repositoryformatversion = 0 + filemode = false + bare = false + logallrefupdates = true + symlinks = false + ignorecase = true +[user] + email = jeon@himpelai.com + name = jeon diff --git a/.git_corrupt_backup/description b/.git_corrupt_backup/description new file mode 100644 index 0000000..498b267 --- /dev/null +++ b/.git_corrupt_backup/description @@ -0,0 +1 @@ +Unnamed repository; edit this file 'description' to name the repository. diff --git a/.git_corrupt_backup/hooks/applypatch-msg.sample b/.git_corrupt_backup/hooks/applypatch-msg.sample new file mode 100644 index 0000000..a5d7b84 --- /dev/null +++ b/.git_corrupt_backup/hooks/applypatch-msg.sample @@ -0,0 +1,15 @@ +#!/bin/sh +# +# An example hook script to check the commit log message taken by +# applypatch from an e-mail message. +# +# The hook should exit with non-zero status after issuing an +# appropriate message if it wants to stop the commit. The hook is +# allowed to edit the commit message file. +# +# To enable this hook, rename this file to "applypatch-msg". + +. git-sh-setup +commitmsg="$(git rev-parse --git-path hooks/commit-msg)" +test -x "$commitmsg" && exec "$commitmsg" ${1+"$@"} +: diff --git a/.git_corrupt_backup/hooks/commit-msg.sample b/.git_corrupt_backup/hooks/commit-msg.sample new file mode 100644 index 0000000..f7458ef --- /dev/null +++ b/.git_corrupt_backup/hooks/commit-msg.sample @@ -0,0 +1,74 @@ +#!/bin/sh +# +# An example hook script to check the commit log message. +# Called by "git commit" with one argument, the name of the file +# that has the commit message. The hook should exit with non-zero +# status after issuing an appropriate message if it wants to stop the +# commit. The hook is allowed to edit the commit message file. +# +# To enable this hook, rename this file to "commit-msg". + +# Uncomment the below to add a Signed-off-by line to the message. +# Doing this in a hook is a bad idea in general, but the prepare-commit-msg +# hook is more suited to it. +# +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p') +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1" + +# This example catches duplicate Signed-off-by lines and messages that +# would confuse 'git am'. + +ret=0 + +test "" = "$(grep '^Signed-off-by: ' "$1" | + sort | uniq -c | sed -e '/^[ ]*1[ ]/d')" || { + echo >&2 Duplicate Signed-off-by lines. + ret=1 +} + +comment_re="$( + { + git config --get-regexp "^core\.comment(char|string)\$" || + echo '#' + } | sed -n -e ' + ${ + s/^[^ ]* // + s|[][*./\]|\\&|g + s/^auto$/[#;@!$%^&|:]/ + p + }' +)" +scissors_line="^${comment_re} -\{8,\} >8 -\{8,\}\$" +comment_line="^${comment_re}.*" +blank_line='^[ ]*$' +# Disallow lines starting with "diff -" or "Index: " in the body of the +# message. Stop looking if we see a scissors line. +line="$(sed -n -e " + # Skip comments and blank lines at the start of the file. + /${scissors_line}/q + /${comment_line}/d + /${blank_line}/d + # The first paragraph will become the subject header so + # does not need to be checked. + : subject + n + /${scissors_line}/q + /${blank_line}/!b subject + # Check the body of the message for problematic + # prefixes. + : body + n + /${scissors_line}/q + /${comment_line}/b body + /^diff -/{p;q;} + /^Index: /{p;q;} + b body + " "$1")" +if test -n "$line" +then + echo >&2 "Message contains a diff that will confuse 'git am'." + echo >&2 "To fix this indent the diff." + ret=1 +fi + +exit $ret diff --git a/.git_corrupt_backup/hooks/fsmonitor-watchman.sample b/.git_corrupt_backup/hooks/fsmonitor-watchman.sample new file mode 100644 index 0000000..429e0a5 --- /dev/null +++ b/.git_corrupt_backup/hooks/fsmonitor-watchman.sample @@ -0,0 +1,168 @@ +#!/usr/bin/perl + +use strict; +use warnings; +use IPC::Open2; + +# An example hook script to integrate Watchman +# (https://facebook.github.io/watchman/) with git to speed up detecting +# new and modified files. +# +# The hook is passed a version (currently 2) and last update token +# formatted as a string and outputs to stdout a new update token and +# all files that have been modified since the update token. Paths must +# be relative to the root of the working tree and separated by a single NUL. +# +# To enable this hook, rename this file to "query-watchman" and set +# 'git config core.fsmonitor .git/hooks/query-watchman' +# +my ($version, $last_update_token) = @ARGV; + +# Uncomment for debugging +# print STDERR "$0 $version $last_update_token\n"; + +# Check the hook interface version +if ($version ne 2) { + die "Unsupported query-fsmonitor hook version '$version'.\n" . + "Falling back to scanning...\n"; +} + +my $git_work_tree = get_working_dir(); + +my $json_pkg; +eval { + require JSON::XS; + $json_pkg = "JSON::XS"; + 1; +} or do { + require JSON::PP; + $json_pkg = "JSON::PP"; +}; + +launch_watchman(); + +sub launch_watchman { + my $o = watchman_query(); + if (is_work_tree_watched($o)) { + output_result($o->{clock}, @{$o->{files}}); + } +} + +sub output_result { + my ($clockid, @files) = @_; + + # Uncomment for debugging watchman output + # open (my $fh, ">", ".git/watchman-output.out"); + # binmode $fh, ":utf8"; + # print $fh "$clockid\n@files\n"; + # close $fh; + + binmode STDOUT, ":utf8"; + print $clockid; + print "\0"; + local $, = "\0"; + print @files; +} + +sub watchman_clock { + my $response = qx/watchman clock "$git_work_tree"/; + die "Failed to get clock id on '$git_work_tree'.\n" . + "Falling back to scanning...\n" if $? != 0; + + return $json_pkg->new->utf8->decode($response); +} + +sub watchman_query { + my $pid = open2(\*CHLD_OUT, \*CHLD_IN, 'watchman -j --no-pretty') + or die "open2() failed: $!\n" . + "Falling back to scanning...\n"; + + # In the query expression below we're asking for names of files that + # changed since $last_update_token but not from the .git folder. + # + # To accomplish this, we're using the "since" generator to use the + # recency index to select candidate nodes and "fields" to limit the + # output to file names only. Then we're using the "expression" term to + # further constrain the results. + my $last_update_line = ""; + if (substr($last_update_token, 0, 1) eq "c") { + $last_update_token = "\"$last_update_token\""; + $last_update_line = qq[\n"since": $last_update_token,]; + } + my $query = <<" END"; + ["query", "$git_work_tree", {$last_update_line + "fields": ["name"], + "expression": ["not", ["dirname", ".git"]] + }] + END + + # Uncomment for debugging the watchman query + # open (my $fh, ">", ".git/watchman-query.json"); + # print $fh $query; + # close $fh; + + print CHLD_IN $query; + close CHLD_IN; + my $response = do {local $/; }; + + # Uncomment for debugging the watch response + # open ($fh, ">", ".git/watchman-response.json"); + # print $fh $response; + # close $fh; + + die "Watchman: command returned no output.\n" . + "Falling back to scanning...\n" if $response eq ""; + die "Watchman: command returned invalid output: $response\n" . + "Falling back to scanning...\n" unless $response =~ /^\{/; + + return $json_pkg->new->utf8->decode($response); +} + +sub is_work_tree_watched { + my ($output) = @_; + my $error = $output->{error}; + if ($error and $error =~ m/unable to resolve root .* directory (.*) is not watched/) { + my $response = qx/watchman watch "$git_work_tree"/; + die "Failed to make watchman watch '$git_work_tree'.\n" . + "Falling back to scanning...\n" if $? != 0; + $output = $json_pkg->new->utf8->decode($response); + $error = $output->{error}; + die "Watchman: $error.\n" . + "Falling back to scanning...\n" if $error; + + # Uncomment for debugging watchman output + # open (my $fh, ">", ".git/watchman-output.out"); + # close $fh; + + # Watchman will always return all files on the first query so + # return the fast "everything is dirty" flag to git and do the + # Watchman query just to get it over with now so we won't pay + # the cost in git to look up each individual file. + my $o = watchman_clock(); + $error = $o->{error}; + + die "Watchman: $error.\n" . + "Falling back to scanning...\n" if $error; + + output_result($o->{clock}, ("/")); + return 0; + } + + die "Watchman: $error.\n" . + "Falling back to scanning...\n" if $error; + + return 1; +} + +sub get_working_dir { + my $working_dir; + if ($^O =~ 'msys' || $^O =~ 'cygwin') { + $working_dir = Win32::GetCwd(); + $working_dir =~ tr/\\/\//; + } else { + require Cwd; + $working_dir = Cwd::cwd(); + } + + return $working_dir; +} diff --git a/.git_corrupt_backup/hooks/post-update.sample b/.git_corrupt_backup/hooks/post-update.sample new file mode 100644 index 0000000..ec17ec1 --- /dev/null +++ b/.git_corrupt_backup/hooks/post-update.sample @@ -0,0 +1,8 @@ +#!/bin/sh +# +# An example hook script to prepare a packed repository for use over +# dumb transports. +# +# To enable this hook, rename this file to "post-update". + +exec git update-server-info diff --git a/.git_corrupt_backup/hooks/pre-applypatch.sample b/.git_corrupt_backup/hooks/pre-applypatch.sample new file mode 100644 index 0000000..4142082 --- /dev/null +++ b/.git_corrupt_backup/hooks/pre-applypatch.sample @@ -0,0 +1,14 @@ +#!/bin/sh +# +# An example hook script to verify what is about to be committed +# by applypatch from an e-mail message. +# +# The hook should exit with non-zero status after issuing an +# appropriate message if it wants to stop the commit. +# +# To enable this hook, rename this file to "pre-applypatch". + +. git-sh-setup +precommit="$(git rev-parse --git-path hooks/pre-commit)" +test -x "$precommit" && exec "$precommit" ${1+"$@"} +: diff --git a/.git_corrupt_backup/hooks/pre-commit.sample b/.git_corrupt_backup/hooks/pre-commit.sample new file mode 100644 index 0000000..29ed5ee --- /dev/null +++ b/.git_corrupt_backup/hooks/pre-commit.sample @@ -0,0 +1,49 @@ +#!/bin/sh +# +# An example hook script to verify what is about to be committed. +# Called by "git commit" with no arguments. The hook should +# exit with non-zero status after issuing an appropriate message if +# it wants to stop the commit. +# +# To enable this hook, rename this file to "pre-commit". + +if git rev-parse --verify HEAD >/dev/null 2>&1 +then + against=HEAD +else + # Initial commit: diff against an empty tree object + against=$(git hash-object -t tree /dev/null) +fi + +# If you want to allow non-ASCII filenames set this variable to true. +allownonascii=$(git config --type=bool hooks.allownonascii) + +# Redirect output to stderr. +exec 1>&2 + +# Cross platform projects tend to avoid non-ASCII filenames; prevent +# them from being added to the repository. We exploit the fact that the +# printable range starts at the space character and ends with tilde. +if [ "$allownonascii" != "true" ] && + # Note that the use of brackets around a tr range is ok here, (it's + # even required, for portability to Solaris 10's /usr/bin/tr), since + # the square bracket bytes happen to fall in the designated range. + test $(git diff-index --cached --name-only --diff-filter=A -z $against | + LC_ALL=C tr -d '[ -~]\0' | wc -c) != 0 +then + cat <<\EOF +Error: Attempt to add a non-ASCII file name. + +This can cause problems if you want to work with people on other platforms. + +To be portable it is advisable to rename the file. + +If you know what you are doing you can disable this check using: + + git config hooks.allownonascii true +EOF + exit 1 +fi + +# If there are whitespace errors, print the offending file names and fail. +exec git diff-index --check --cached $against -- diff --git a/.git_corrupt_backup/hooks/pre-merge-commit.sample b/.git_corrupt_backup/hooks/pre-merge-commit.sample new file mode 100644 index 0000000..399eab1 --- /dev/null +++ b/.git_corrupt_backup/hooks/pre-merge-commit.sample @@ -0,0 +1,13 @@ +#!/bin/sh +# +# An example hook script to verify what is about to be committed. +# Called by "git merge" with no arguments. The hook should +# exit with non-zero status after issuing an appropriate message to +# stderr if it wants to stop the merge commit. +# +# To enable this hook, rename this file to "pre-merge-commit". + +. git-sh-setup +test -x "$GIT_DIR/hooks/pre-commit" && + exec "$GIT_DIR/hooks/pre-commit" +: diff --git a/.git_corrupt_backup/hooks/pre-push.sample b/.git_corrupt_backup/hooks/pre-push.sample new file mode 100644 index 0000000..4ce688d --- /dev/null +++ b/.git_corrupt_backup/hooks/pre-push.sample @@ -0,0 +1,53 @@ +#!/bin/sh + +# An example hook script to verify what is about to be pushed. Called by "git +# push" after it has checked the remote status, but before anything has been +# pushed. If this script exits with a non-zero status nothing will be pushed. +# +# This hook is called with the following parameters: +# +# $1 -- Name of the remote to which the push is being done +# $2 -- URL to which the push is being done +# +# If pushing without using a named remote those arguments will be equal. +# +# Information about the commits which are being pushed is supplied as lines to +# the standard input in the form: +# +# +# +# This sample shows how to prevent push of commits where the log message starts +# with "WIP" (work in progress). + +remote="$1" +url="$2" + +zero=$(git hash-object --stdin &2 "Found WIP commit in $local_ref, not pushing" + exit 1 + fi + fi +done + +exit 0 diff --git a/.git_corrupt_backup/hooks/pre-rebase.sample b/.git_corrupt_backup/hooks/pre-rebase.sample new file mode 100644 index 0000000..6cbef5c --- /dev/null +++ b/.git_corrupt_backup/hooks/pre-rebase.sample @@ -0,0 +1,169 @@ +#!/bin/sh +# +# Copyright (c) 2006, 2008 Junio C Hamano +# +# The "pre-rebase" hook is run just before "git rebase" starts doing +# its job, and can prevent the command from running by exiting with +# non-zero status. +# +# The hook is called with the following parameters: +# +# $1 -- the upstream the series was forked from. +# $2 -- the branch being rebased (or empty when rebasing the current branch). +# +# This sample shows how to prevent topic branches that are already +# merged to 'next' branch from getting rebased, because allowing it +# would result in rebasing already published history. + +publish=next +basebranch="$1" +if test "$#" = 2 +then + topic="refs/heads/$2" +else + topic=`git symbolic-ref HEAD` || + exit 0 ;# we do not interrupt rebasing detached HEAD +fi + +case "$topic" in +refs/heads/??/*) + ;; +*) + exit 0 ;# we do not interrupt others. + ;; +esac + +# Now we are dealing with a topic branch being rebased +# on top of master. Is it OK to rebase it? + +# Does the topic really exist? +git show-ref -q "$topic" || { + echo >&2 "No such branch $topic" + exit 1 +} + +# Is topic fully merged to master? +not_in_master=`git rev-list --pretty=oneline ^master "$topic"` +if test -z "$not_in_master" +then + echo >&2 "$topic is fully merged to master; better remove it." + exit 1 ;# we could allow it, but there is no point. +fi + +# Is topic ever merged to next? If so you should not be rebasing it. +only_next_1=`git rev-list ^master "^$topic" ${publish} | sort` +only_next_2=`git rev-list ^master ${publish} | sort` +if test "$only_next_1" = "$only_next_2" +then + not_in_topic=`git rev-list "^$topic" master` + if test -z "$not_in_topic" + then + echo >&2 "$topic is already up to date with master" + exit 1 ;# we could allow it, but there is no point. + else + exit 0 + fi +else + not_in_next=`git rev-list --pretty=oneline ^${publish} "$topic"` + /usr/bin/perl -e ' + my $topic = $ARGV[0]; + my $msg = "* $topic has commits already merged to public branch:\n"; + my (%not_in_next) = map { + /^([0-9a-f]+) /; + ($1 => 1); + } split(/\n/, $ARGV[1]); + for my $elem (map { + /^([0-9a-f]+) (.*)$/; + [$1 => $2]; + } split(/\n/, $ARGV[2])) { + if (!exists $not_in_next{$elem->[0]}) { + if ($msg) { + print STDERR $msg; + undef $msg; + } + print STDERR " $elem->[1]\n"; + } + } + ' "$topic" "$not_in_next" "$not_in_master" + exit 1 +fi + +<<\DOC_END + +This sample hook safeguards topic branches that have been +published from being rewound. + +The workflow assumed here is: + + * Once a topic branch forks from "master", "master" is never + merged into it again (either directly or indirectly). + + * Once a topic branch is fully cooked and merged into "master", + it is deleted. If you need to build on top of it to correct + earlier mistakes, a new topic branch is created by forking at + the tip of the "master". This is not strictly necessary, but + it makes it easier to keep your history simple. + + * Whenever you need to test or publish your changes to topic + branches, merge them into "next" branch. + +The script, being an example, hardcodes the publish branch name +to be "next", but it is trivial to make it configurable via +$GIT_DIR/config mechanism. + +With this workflow, you would want to know: + +(1) ... if a topic branch has ever been merged to "next". Young + topic branches can have stupid mistakes you would rather + clean up before publishing, and things that have not been + merged into other branches can be easily rebased without + affecting other people. But once it is published, you would + not want to rewind it. + +(2) ... if a topic branch has been fully merged to "master". + Then you can delete it. More importantly, you should not + build on top of it -- other people may already want to + change things related to the topic as patches against your + "master", so if you need further changes, it is better to + fork the topic (perhaps with the same name) afresh from the + tip of "master". + +Let's look at this example: + + o---o---o---o---o---o---o---o---o---o "next" + / / / / + / a---a---b A / / + / / / / + / / c---c---c---c B / + / / / \ / + / / / b---b C \ / + / / / / \ / + ---o---o---o---o---o---o---o---o---o---o---o "master" + + +A, B and C are topic branches. + + * A has one fix since it was merged up to "next". + + * B has finished. It has been fully merged up to "master" and "next", + and is ready to be deleted. + + * C has not merged to "next" at all. + +We would want to allow C to be rebased, refuse A, and encourage +B to be deleted. + +To compute (1): + + git rev-list ^master ^topic next + git rev-list ^master next + + if these match, topic has not merged in next at all. + +To compute (2): + + git rev-list master..topic + + if this is empty, it is fully merged to "master". + +DOC_END diff --git a/.git_corrupt_backup/hooks/pre-receive.sample b/.git_corrupt_backup/hooks/pre-receive.sample new file mode 100644 index 0000000..a1fd29e --- /dev/null +++ b/.git_corrupt_backup/hooks/pre-receive.sample @@ -0,0 +1,24 @@ +#!/bin/sh +# +# An example hook script to make use of push options. +# The example simply echoes all push options that start with 'echoback=' +# and rejects all pushes when the "reject" push option is used. +# +# To enable this hook, rename this file to "pre-receive". + +if test -n "$GIT_PUSH_OPTION_COUNT" +then + i=0 + while test "$i" -lt "$GIT_PUSH_OPTION_COUNT" + do + eval "value=\$GIT_PUSH_OPTION_$i" + case "$value" in + echoback=*) + echo "echo from the pre-receive-hook: ${value#*=}" >&2 + ;; + reject) + exit 1 + esac + i=$((i + 1)) + done +fi diff --git a/.git_corrupt_backup/hooks/prepare-commit-msg.sample b/.git_corrupt_backup/hooks/prepare-commit-msg.sample new file mode 100644 index 0000000..10fa14c --- /dev/null +++ b/.git_corrupt_backup/hooks/prepare-commit-msg.sample @@ -0,0 +1,42 @@ +#!/bin/sh +# +# An example hook script to prepare the commit log message. +# Called by "git commit" with the name of the file that has the +# commit message, followed by the description of the commit +# message's source. The hook's purpose is to edit the commit +# message file. If the hook fails with a non-zero status, +# the commit is aborted. +# +# To enable this hook, rename this file to "prepare-commit-msg". + +# This hook includes three examples. The first one removes the +# "# Please enter the commit message..." help message. +# +# The second includes the output of "git diff --name-status -r" +# into the message, just before the "git status" output. It is +# commented because it doesn't cope with --amend or with squashed +# commits. +# +# The third example adds a Signed-off-by line to the message, that can +# still be edited. This is rarely a good idea. + +COMMIT_MSG_FILE=$1 +COMMIT_SOURCE=$2 +SHA1=$3 + +/usr/bin/perl -i.bak -ne 'print unless(m/^. Please enter the commit message/..m/^#$/)' "$COMMIT_MSG_FILE" + +# case "$COMMIT_SOURCE,$SHA1" in +# ,|template,) +# /usr/bin/perl -i.bak -pe ' +# print "\n" . `git diff --cached --name-status -r` +# if /^#/ && $first++ == 0' "$COMMIT_MSG_FILE" ;; +# *) ;; +# esac + +# SOB=$(git var GIT_COMMITTER_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p') +# git interpret-trailers --in-place --trailer "$SOB" "$COMMIT_MSG_FILE" +# if test -z "$COMMIT_SOURCE" +# then +# /usr/bin/perl -i.bak -pe 'print "\n" if !$first_line++' "$COMMIT_MSG_FILE" +# fi diff --git a/.git_corrupt_backup/hooks/push-to-checkout.sample b/.git_corrupt_backup/hooks/push-to-checkout.sample new file mode 100644 index 0000000..af5a0c0 --- /dev/null +++ b/.git_corrupt_backup/hooks/push-to-checkout.sample @@ -0,0 +1,78 @@ +#!/bin/sh + +# An example hook script to update a checked-out tree on a git push. +# +# This hook is invoked by git-receive-pack(1) when it reacts to git +# push and updates reference(s) in its repository, and when the push +# tries to update the branch that is currently checked out and the +# receive.denyCurrentBranch configuration variable is set to +# updateInstead. +# +# By default, such a push is refused if the working tree and the index +# of the remote repository has any difference from the currently +# checked out commit; when both the working tree and the index match +# the current commit, they are updated to match the newly pushed tip +# of the branch. This hook is to be used to override the default +# behaviour; however the code below reimplements the default behaviour +# as a starting point for convenient modification. +# +# The hook receives the commit with which the tip of the current +# branch is going to be updated: +commit=$1 + +# It can exit with a non-zero status to refuse the push (when it does +# so, it must not modify the index or the working tree). +die () { + echo >&2 "$*" + exit 1 +} + +# Or it can make any necessary changes to the working tree and to the +# index to bring them to the desired state when the tip of the current +# branch is updated to the new commit, and exit with a zero status. +# +# For example, the hook can simply run git read-tree -u -m HEAD "$1" +# in order to emulate git fetch that is run in the reverse direction +# with git push, as the two-tree form of git read-tree -u -m is +# essentially the same as git switch or git checkout that switches +# branches while keeping the local changes in the working tree that do +# not interfere with the difference between the branches. + +# The below is a more-or-less exact translation to shell of the C code +# for the default behaviour for git's push-to-checkout hook defined in +# the push_to_deploy() function in builtin/receive-pack.c. +# +# Note that the hook will be executed from the repository directory, +# not from the working tree, so if you want to perform operations on +# the working tree, you will have to adapt your code accordingly, e.g. +# by adding "cd .." or using relative paths. + +if ! git update-index -q --ignore-submodules --refresh +then + die "Up-to-date check failed" +fi + +if ! git diff-files --quiet --ignore-submodules -- +then + die "Working directory has unstaged changes" +fi + +# This is a rough translation of: +# +# head_has_history() ? "HEAD" : EMPTY_TREE_SHA1_HEX +if git cat-file -e HEAD 2>/dev/null +then + head=HEAD +else + head=$(git hash-object -t tree --stdin &2 + exit 1 +} + +unset GIT_DIR GIT_WORK_TREE +cd "$worktree" && + +if grep -q "^diff --git " "$1" +then + validate_patch "$1" +else + validate_cover_letter "$1" +fi && + +if test "$GIT_SENDEMAIL_FILE_COUNTER" = "$GIT_SENDEMAIL_FILE_TOTAL" +then + git config --unset-all sendemail.validateWorktree && + trap 'git worktree remove -ff "$worktree"' EXIT && + validate_series +fi diff --git a/.git_corrupt_backup/hooks/update.sample b/.git_corrupt_backup/hooks/update.sample new file mode 100644 index 0000000..c4d426b --- /dev/null +++ b/.git_corrupt_backup/hooks/update.sample @@ -0,0 +1,128 @@ +#!/bin/sh +# +# An example hook script to block unannotated tags from entering. +# Called by "git receive-pack" with arguments: refname sha1-old sha1-new +# +# To enable this hook, rename this file to "update". +# +# Config +# ------ +# hooks.allowunannotated +# This boolean sets whether unannotated tags will be allowed into the +# repository. By default they won't be. +# hooks.allowdeletetag +# This boolean sets whether deleting tags will be allowed in the +# repository. By default they won't be. +# hooks.allowmodifytag +# This boolean sets whether a tag may be modified after creation. By default +# it won't be. +# hooks.allowdeletebranch +# This boolean sets whether deleting branches will be allowed in the +# repository. By default they won't be. +# hooks.denycreatebranch +# This boolean sets whether remotely creating branches will be denied +# in the repository. By default this is allowed. +# + +# --- Command line +refname="$1" +oldrev="$2" +newrev="$3" + +# --- Safety check +if [ -z "$GIT_DIR" ]; then + echo "Don't run this script from the command line." >&2 + echo " (if you want, you could supply GIT_DIR then run" >&2 + echo " $0 )" >&2 + exit 1 +fi + +if [ -z "$refname" -o -z "$oldrev" -o -z "$newrev" ]; then + echo "usage: $0 " >&2 + exit 1 +fi + +# --- Config +allowunannotated=$(git config --type=bool hooks.allowunannotated) +allowdeletebranch=$(git config --type=bool hooks.allowdeletebranch) +denycreatebranch=$(git config --type=bool hooks.denycreatebranch) +allowdeletetag=$(git config --type=bool hooks.allowdeletetag) +allowmodifytag=$(git config --type=bool hooks.allowmodifytag) + +# check for no description +projectdesc=$(sed -e '1q' "$GIT_DIR/description") +case "$projectdesc" in +"Unnamed repository"* | "") + echo "*** Project description file hasn't been set" >&2 + exit 1 + ;; +esac + +# --- Check types +# if $newrev is 0000...0000, it's a commit to delete a ref. +zero=$(git hash-object --stdin &2 + echo "*** Use 'git tag [ -a | -s ]' for tags you want to propagate." >&2 + exit 1 + fi + ;; + refs/tags/*,delete) + # delete tag + if [ "$allowdeletetag" != "true" ]; then + echo "*** Deleting a tag is not allowed in this repository" >&2 + exit 1 + fi + ;; + refs/tags/*,tag) + # annotated tag + if [ "$allowmodifytag" != "true" ] && git rev-parse $refname > /dev/null 2>&1 + then + echo "*** Tag '$refname' already exists." >&2 + echo "*** Modifying a tag is not allowed in this repository." >&2 + exit 1 + fi + ;; + refs/heads/*,commit) + # branch + if [ "$oldrev" = "$zero" -a "$denycreatebranch" = "true" ]; then + echo "*** Creating a branch is not allowed in this repository" >&2 + exit 1 + fi + ;; + refs/heads/*,delete) + # delete branch + if [ "$allowdeletebranch" != "true" ]; then + echo "*** Deleting a branch is not allowed in this repository" >&2 + exit 1 + fi + ;; + refs/remotes/*,commit) + # tracking branch + ;; + refs/remotes/*,delete) + # delete tracking branch + if [ "$allowdeletebranch" != "true" ]; then + echo "*** Deleting a tracking branch is not allowed in this repository" >&2 + exit 1 + fi + ;; + *) + # Anything else (is there anything else?) + echo "*** Update hook: unknown type of update to ref $refname of type $newrev_type" >&2 + exit 1 + ;; +esac + +# --- Finished +exit 0 diff --git a/.git_corrupt_backup/index b/.git_corrupt_backup/index new file mode 100644 index 0000000..f3e6c5a Binary files /dev/null and b/.git_corrupt_backup/index differ diff --git a/.git_corrupt_backup/info/exclude b/.git_corrupt_backup/info/exclude new file mode 100644 index 0000000..a5196d1 --- /dev/null +++ b/.git_corrupt_backup/info/exclude @@ -0,0 +1,6 @@ +# git ls-files --others --exclude-from=.git/info/exclude +# Lines that start with '#' are comments. +# For a project mostly in C, the following would be a good set of +# exclude patterns (uncomment them if you want to use them): +# *.[oa] +# *~ diff --git a/.git_corrupt_backup/logs/HEAD b/.git_corrupt_backup/logs/HEAD new file mode 100644 index 0000000..7d70bfb --- /dev/null +++ b/.git_corrupt_backup/logs/HEAD @@ -0,0 +1,2 @@ +0000000000000000000000000000000000000000 1568237dc62f9ae863d0ab8bd5ae6d90934be870 goosam1 1781527333 +0900 commit (initial): chore: HERV 통합 저장소 초기 커밋 +1568237dc62f9ae863d0ab8bd5ae6d90934be870 5a96a696b16afe8b9e21e158185bc3e98f645e52 jeon 1781527463 +0900 commit (amend): chore: HERV 통합 저장소 초기 커밋 diff --git a/.git_corrupt_backup/logs/refs/heads/main b/.git_corrupt_backup/logs/refs/heads/main new file mode 100644 index 0000000..7d70bfb --- /dev/null +++ b/.git_corrupt_backup/logs/refs/heads/main @@ -0,0 +1,2 @@ +0000000000000000000000000000000000000000 1568237dc62f9ae863d0ab8bd5ae6d90934be870 goosam1 1781527333 +0900 commit (initial): chore: HERV 통합 저장소 초기 커밋 +1568237dc62f9ae863d0ab8bd5ae6d90934be870 5a96a696b16afe8b9e21e158185bc3e98f645e52 jeon 1781527463 +0900 commit (amend): chore: HERV 통합 저장소 초기 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a/0.install/dotnet-sdk-10.0.301-win-x64.exe b/0.install/dotnet-sdk-10.0.301-win-x64.exe new file mode 100644 index 0000000..8ee660e Binary files /dev/null and b/0.install/dotnet-sdk-10.0.301-win-x64.exe differ diff --git a/0.install/msys2-x86_64-20260322.exe b/0.install/msys2-x86_64-20260322.exe new file mode 100644 index 0000000..5702a7e Binary files /dev/null and b/0.install/msys2-x86_64-20260322.exe differ diff --git a/CLAUDE.md b/CLAUDE.md new file mode 100644 index 0000000..e70b04e --- /dev/null +++ b/CLAUDE.md @@ -0,0 +1,141 @@ +DL 각실제어 시스템 구성 +HERV (전열교환기) -(485통신) BUNBAGI -(485통신) 배기(RA) DIFFUSER -(485통신) 급기(SA) DIFFUSER + +각실 DIFFUSER 구성 +거실 : 배기(RA) DIFFUSER / 급기(SA1) DIFFUSER / 급기(SA2) DIFFUSER +방1 ~ 방3 : 배기(RA) DIFFUSER / 급기(SA) DIFFUSER + +프로토콜 +HERV / BUNBAGI / DIFFUSER : 수정_Each_Room_Jushin_protocol_RS485_Rev1.2_20260115_CWS + +대시보드 프로그램 (모두 TestProgram 폴더 하위) +C# WPF .NET 10 + +빌드 및 배포방법 +PC 대시보드 +dotnet cleand 프로젝트명 +dotnet build 프로젝트명 +dotnet publish "d:\project\nuvoton\HERV\TestProgram\PCDashBoard\ErvDashboard.csproj" -c Release +csproj에 SelfContained / PublishSingleFile / win-x64 가 이미 설정돼 있어서 추가 옵션이 필요 없습니다. +결과물: TestProgram\PCDashBoard\bin\Release\net10.0-windows\win-x64\publish\ErvDashboard.exe + +WEB 대시보드 +# 런타임 미설치 PC용 (단일 exe, 권장) +dotnet publish "d:\project\nuvoton\HERV\TestProgram\WebDashBoard\ErvCollector\ErvCollector.csproj" ` + -c Release -r win-x64 --self-contained true -p:PublishSingleFile=true + +# .NET 10 런타임 이미 깔린 PC용 (가벼움) +dotnet publish "d:\project\nuvoton\HERV\TestProgram\WebDashBoard\ErvCollector\ErvCollector.csproj" -c Release +결과물: ...\ErvCollector\bin\Release\net10.0\win-x64\publish\ +appsettings.json 과 wwwroot\ (웹 모니터 정적파일)가 publish 폴더에 같이 복사됩니다 — publish 폴더 전체를 통째로 복사하세요. exe만 떼면 웹 화면이 안 뜹니다. + +해상도 : 1920 X 1200 (노트북 기준) 안 넘게 제작. +프로토콜 : PC_ERV_Protocol.MD +공용 라이브러리 : TestProgram/ErvProtocol 폴더 (단일 진실원본) +PC용 (485통신) - TestProgram/PCDashBoard (ErvDashboard.csproj) +WEB용 (WIFI) - TestProgram/WebDashBoard (ErvCollector 수집·제어 서버 + ErvWebDashboard 모니터) + +시뮬레이터 프로그램 +C# WPF +UI 내용은 정적생성 할 것. 반복생성은 제외. +ERV SIMULATOR : +DIFFUSER SIMULATOR : + +HERV 사양 +동작사양 +전원 : ON, OFF +운전모드 : 환기(수동), 자동, 바이패스, 공기청정 +(운전모드 전환 시 풍량 1단, 자동 제외) +특이사항 : 기저운전/장비보호 + +(꺼짐예약) : 0 ~ 8 시간, 1시간 단위, 0은 꺼짐 +VSP 설정값 (1바이트 0~255, 사양서 DL 대덕연구소 H-ERV 실측표) + +| 구분 | 단수 | 풍량(CMH) | VSP SA | VSP EA | 전압 SA(V) | 전압 EA(V) | +|----------|--------|-----------|--------|--------|-----------|-----------| +| 환기 | 약-1 | 100 | 57 | 56 | 3.347 | 3.296 | +| 환기 | 중-2 | 150 | 63 | 61 | 3.634 | 3.571 | +| 환기 | 강-3 | 200 | 69 | 67 | 3.968 | 3.893 | +| 환기 | 터보-4 | 250 | 86 | 85 | 4.391 | 4.125 | +| 바이패스 | 기본 | 150 | 66 | 80 | 3.776 | 4.539 | +| 공청 | 약-1 | 80 | 66 | - | 3.778 | - | +| 공청 | 중-2 | 100 | 70 | - | 4.018 | - | +| 공청 | 강-3 | 120 | 77 | - | 4.354 | - | +| 공청 | 터보-4 | 150 | 80 | - | 4.50 | - | + +VSP 테이블 (VSP ↔ 실측전압, V = VSP × 0.05 + 0.5) + +| VSP | V | VSP | V | VSP | V | VSP | V | VSP | V | +|----|------|----|------|----|------|----|------|----|------| +| 5 | 0.75 | 25 | 1.75 | 45 | 2.75 | 65 | 3.75 | 85 | 4.75 | +| 6 | 0.80 | 26 | 1.80 | 46 | 2.80 | 66 | 3.80 | 86 | 4.80 | +| 7 | 0.85 | 27 | 1.85 | 47 | 2.85 | 67 | 3.85 | 87 | 4.85 | +| 8 | 0.90 | 28 | 1.90 | 48 | 2.90 | 68 | 3.90 | 88 | 4.90 | +| 9 | 0.95 | 29 | 1.95 | 49 | 2.95 | 69 | 3.95 | 89 | 4.95 | +| 10 | 1.00 | 30 | 2.00 | 50 | 3.00 | 70 | 4.00 | 90 | 5.00 | +| 11 | 1.05 | 31 | 2.05 | 51 | 3.05 | 71 | 4.05 | 91 | 5.05 | +| 12 | 1.10 | 32 | 2.10 | 52 | 3.10 | 72 | 4.10 | 92 | 5.10 | +| 13 | 1.15 | 33 | 2.15 | 53 | 3.15 | 73 | 4.15 | 93 | 5.15 | +| 14 | 1.20 | 34 | 2.20 | 54 | 3.20 | 74 | 4.20 | 94 | 5.20 | +| 15 | 1.25 | 35 | 2.25 | 55 | 3.25 | 75 | 4.25 | 95 | 5.25 | +| 16 | 1.30 | 36 | 2.30 | 56 | 3.30 | 76 | 4.30 | | | +| 17 | 1.35 | 37 | 2.35 | 57 | 3.35 | 77 | 4.35 | | | +| 18 | 1.40 | 38 | 2.40 | 58 | 3.40 | 78 | 4.40 | | | +| 19 | 1.45 | 39 | 2.45 | 59 | 3.45 | 79 | 4.45 | | | +| 20 | 1.50 | 40 | 2.50 | 60 | 3.50 | 80 | 4.50 | | | +| 21 | 1.55 | 41 | 2.55 | 61 | 3.55 | 81 | 4.55 | | | +| 22 | 1.60 | 42 | 2.60 | 62 | 3.60 | 82 | 4.60 | | | +| 23 | 1.65 | 43 | 2.65 | 63 | 3.65 | 83 | 4.65 | | | +| 24 | 1.70 | 44 | 2.70 | 64 | 3.70 | 84 | 4.70 | | | + +공기질 센서 모드별 오염단계 임계 및 히스테리시스(하강) + +| 오염단계 | ECO CO2 | ECO PM2.5 | ECO PM10 | ECO VOC | NORMAL CO2 | NORMAL PM2.5 | NORMAL PM10 | NORMAL VOC | TURBO CO2 | TURBO PM2.5 | TURBO PM10 | TURBO VOC | 상태/색상 | +|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +| 0 | 0~1000 | 0~20 | 0~40 | 0~171 | 0~800 | 0~14 | 0~28 | 0~120 | 0~700 | 0~12 | 0~24 | 0~103 | 좋음(파랑) | +| 1 | 1001~1300 | 21~38 | 41~86 | 172~195 | 801~1100 | 15~29 | 29~66 | 121~150 | 701~1000 | 13~23 | 25~53 | 104~120 | 보통(초록) | +| 2 | 1301~1600 | 39~60 | 87~126 | 196~308 | 1101~1400 | 30~49 | 67~102 | 151~250 | 1001~1300 | 24~38 | 54~78 | 121~192 | 나쁨(노랑) | +| 3 | 1601~2000 | 61~86 | 127~173 | 309~438 | 1401~1700 | 50~69 | 103~138 | 251~350 | 1301~1600 | 39~52 | 79~104 | 193~263 | 매우나쁨(주황) | +| 4 | 2001~ | 87~ | 174~ | 439~ | 1701~ | 70~ | 139~ | 351~ | 1601~ | 53~ | 105~ | 264~ | 매우나쁨(빨강) | +| 히스(하강) | -50 | -2 | -5 | -5 | -50 | -2 | -5 | -5 | -30 | -2 | -5 | -3 | | + +각실제어 시나리오모드 : 자동(분산,집중), 안심회복, 스마트 수면, 쾌적조리 + +회로도 : HERV_MAIN_REV1.1_20240826(회로도).PDF + +EEPROM 저장 데이터 (My_define.h EEP_*, page 128B / 엔트리 약 122) + +| 인덱스 | 항목 | 비고 | +|---|---|---| +| 0~3 | 서명 0x55AA55AA | 초기화 마커 | +| 5 | Modbus ID | | +| 10~33 | 팬 VSP 프리셋 s_FAN1/2 (환기·공청·바이패스 1~4) | 1바이트, 대시보드 CTRL_VSP 반영 | +| 34~39 | 필터/소자 청소·교체 시간 | u16 | +| 40~42 | 정전복귀(전원/운전모드/풍량) | | +| 43 | 히스테리시스 활성 프리셋 (0 ECO/1 NORMAL/2 TURBO) | 유효성 마커 겸용 | +| 44~55 | 데드밴드(하강) Co2/Pm25/Pm10/Voc × 3프리셋 | u8 | +| 56~79 | CO2 임계 Co2_Thr[3][4] | u16 | +| 80~103 | VOC 임계 Voc_Thr[3][4] | u16 | +| 104~115 | PM2.5 임계 Pm25_Thr[3][4] | u8 | +| 116~127 | PM10 임계 Pm10_Thr[3][4] | u8 | + +- 대시보드에서 전원/모드/VSP/히스테리시스(프리셋·임계·데드밴드) 변경 → ERV가 EEPROM 저장(재부팅 유지). +- 구버전 펌웨어(STATUS 134B, 구 m_*_Level) EEPROM은 신규 영역 미초기화 → 기본값(사양값) 사용 후 변경 시 저장. + +BUNBAGI 사양 + +회로도 : HERV_MAIN_REV1.1_20240826(회로도).PDF +STATUS LED : STATUS_LED-PB.14, ACTIVE LOW + +DIFFUSER 사양 +급기(SA) DIFFUSER 구성 : 댐퍼 +배기(RA) DIFFUSER 구성 : 댐퍼, 공기질센서, LED + +회로도 : 전동디퓨져_REV1.0_20260130.PDF +STATUS LED : STATUS_LED-PA.11, ACTIVE LOW +SELECT SWITCH : SW1, DIPSW1-PA.10, LOW-SA, HIGH-RA +485 통신 : CN3, CN4, INT485TX-PB.5, INT485RX-PB.4, INT485DIR-PB.6 +댐퍼 : CN2, STEP1_A-PC.8,STEP1_B-PC.9,STEP1_C-PC.10,STEP1_D-PC.11 +공기질 센서 : CN5, SENSOR_ON-PA.3, SENSOR_SCL-PA.5, SENSOR_SDA-PA.4, SEN66 +LED : CN6, LED_ON-PA.15, LED_R-PA.14,LED_G-PA.13,LED_B-PA.12 + diff --git a/DL_Air Planner 사양/260428_제어로직/DL_동작로직_260318.pptx b/DL_Air Planner 사양/260428_제어로직/DL_동작로직_260318.pptx new file mode 100644 index 0000000..d4e9eff Binary files /dev/null and b/DL_Air Planner 사양/260428_제어로직/DL_동작로직_260318.pptx differ diff --git a/DL_Air Planner 사양/260428_제어로직/동작로직_이전_수정 사양_정밀비교_260507.docx b/DL_Air Planner 사양/260428_제어로직/동작로직_이전_수정 사양_정밀비교_260507.docx new file mode 100644 index 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수정/스마트스위치 월패드 UI_rev12_제습+버튼설명자료.pptx differ diff --git a/DL_Air Planner 사양/AirPlanner/AirPlanner.csproj b/DL_Air Planner 사양/AirPlanner/AirPlanner.csproj new file mode 100644 index 0000000..ccc8f4c --- /dev/null +++ b/DL_Air Planner 사양/AirPlanner/AirPlanner.csproj @@ -0,0 +1,18 @@ + + + + WinExe + net10.0-windows + true + enable + enable + AirPlanner + AirPlanner + AirPlanner.App + win-x64 + true + true + true + + + diff --git a/DL_Air Planner 사양/AirPlanner/App.xaml b/DL_Air Planner 사양/AirPlanner/App.xaml new file mode 100644 index 0000000..e2db824 --- /dev/null +++ b/DL_Air Planner 사양/AirPlanner/App.xaml @@ -0,0 +1,12 @@ + + + + + + + + + diff --git a/DL_Air Planner 사양/AirPlanner/App.xaml.cs b/DL_Air Planner 사양/AirPlanner/App.xaml.cs new file mode 100644 index 0000000..0a482af --- /dev/null +++ b/DL_Air Planner 사양/AirPlanner/App.xaml.cs @@ -0,0 +1,8 @@ +using System.Windows; + +namespace AirPlanner +{ + public partial class App : Application + { + } +} diff --git a/DL_Air Planner 사양/AirPlanner/ControlView.xaml b/DL_Air Planner 사양/AirPlanner/ControlView.xaml new file mode 100644 index 0000000..edca754 --- /dev/null +++ b/DL_Air Planner 사양/AirPlanner/ControlView.xaml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + +
만든이 : 전경선
만든날 : 2026.06.3
+ + + +
+ +
+
현장 개요
+
+
+ + +
+
ERV 제어 (원격)
+
+
+
전원 + ERV 리셋
+
운전모드
+
풍량 + 자동 프리셋
+
(꺼짐)예약 + +
+
+
+
부가모드
+
연동후드 +
+
스마트수면
시간설정 + ~ + + +
+
설정 + + +
+
+
+
+ + +
+
자동운전 상태 (표시 전용)
+
+
+ +
+
각실 모니터링 · 제어
+
+
+ + +
+
로그 그래프
+ + 날짜 선택 → 불러오기 → 좌측 시리즈 선택/해제 → (필요 시) 엑셀 저장 +
+ + + + + + + + + + diff --git a/TestProgram/WebDashBoard/ErvWebDashboard/index.html b/TestProgram/WebDashBoard/ErvWebDashboard/index.html new file mode 100644 index 0000000..d6071a2 --- /dev/null +++ b/TestProgram/WebDashBoard/ErvWebDashboard/index.html @@ -0,0 +1,597 @@ + + + + + +HuevenEco DL 각실제어 모니터링·제어 + + + +
+ +
+
+
HuevenEco DL 각실제어 모니터링·제어
+
EW11(RS-485↔WiFi) ↔ 미니PC 수집/제어 서버 · PC 대시보드 기능 통합
+
+
+ + +
만든이 : 전경선
만든날 : 2026.06.3
+
+
+ +
+ +
+
현장 개요
+
+
+ + +
+
ERV 제어 (원격)
+
+
+
전원 + ERV 리셋
+
운전모드
+
풍량 + 자동 프리셋
+
(꺼짐)예약 + +
+
+
+
부가모드
+
연동후드 +
+
스마트수면
시간설정 + ~ + + +
+
설정 + + +
+
+
+
+ + +
+
자동운전 상태 (표시 전용)
+
+
+ +
+
각실 모니터링 · 제어
+
+
+ + +
+
로그 그래프
+ + 날짜 선택 → 불러오기 → 좌측 시리즈 선택/해제 → (필요 시) 엑셀 저장 +
+ + + + + +
+ + + + diff --git a/TestProgram/WebDashBoard/HTTP_vs_MQTT_검토.md b/TestProgram/WebDashBoard/HTTP_vs_MQTT_검토.md new file mode 100644 index 0000000..fe8b161 --- /dev/null +++ b/TestProgram/WebDashBoard/HTTP_vs_MQTT_검토.md @@ -0,0 +1,89 @@ +# 통신 방식 검토 : HTTP vs MQTT + +- 작성일: 2026-06-03 +- 대상: HuevenEco DL 각실제어 원격 모니터링·제어 (EW11 ↔ 미니PC 수집서버 ↔ 웹 대시보드) +- 관련: `ErvCollector/`, `../TestProgram/PC_ERV_Protocol.md`, `../EW11_RS485 TO WIFI/260603_EW11_클라우드전송_검토.md` + +--- + +## 1. 현재 시스템의 통신 계층 (두 가지) + +| # | 구간 | 현재 방식 | 비고 | +|---|------|-----------|------| +| ① | ERV ↔ EW11 ↔ 수집서버 | **0xAA 바이너리 프레임 over TCP** | 장치 구간 (HTTP 아님) | +| ② | 브라우저 ↔ 수집서버 | **HTTP** (`/api/latest` 1초 폴링 + `/api/control` POST) | 대시보드 구간 | + +> "웹 프로토콜이 HTTP" = ②번. 일반적으로 IoT에서 MQTT가 거론되는 구간은 **①번(장치↔서버)** 이다. + +--- + +## 2. HTTP vs MQTT 핵심 차이 + +| 항목 | HTTP (현재) | MQTT | +|---|---|---| +| 모델 | 요청-응답 (Pull) | 발행-구독 (Pub/Sub), **브로커** 경유 | +| 연결 | 매 요청 단발 | **지속 TCP 1개 유지** | +| 방향 | 클라이언트가 물어봐야 받음(폴링) | 변화 시 **즉시 푸시** | +| 오버헤드 | 헤더 큼(매 요청 수백 B) | 헤더 2~수 B, **매우 경량** | +| 실시간성 | 폴링 주기만큼 지연 | 낮은 지연 | +| 다수 장치 | 서버가 일일이 응답 | 브로커가 **N:N 중계**, 확장 용이 | +| 신뢰성/오프라인 | 별도 구현 필요 | **QoS 0/1/2, retained, LWT(접속 끊김 자동 통지)** | +| 브라우저 | 기본 지원 | **직접 불가 → MQTT over WebSocket 필요** | +| 추가 인프라 | 없음(수집서버가 이미 제공) | **브로커(예: Mosquitto) 1개 필요** | + +--- + +## 3. 우리 프로젝트에 대입 + +### (A) EW11 → 서버 (3개 현장, 인터넷) — MQTT의 본 무대 +- EW11은 **MQTT 클라이언트 모드 지원** (매뉴얼 검토 완료). +- 토픽 설계(예): 각 EW11이 `erv/site01/status` 에 0xAA STATUS **발행**, 서버 구독. + 제어는 서버가 `erv/site01/control` 에 **발행** → EW11 구독. +- 이점: + - 변화 즉시 푸시(저지연) + - **LWT(Last Will & Testament)** 로 접속 끊김 자동 감지 (현재는 30초 추정 방식) + - QoS 로 유실 방지, retained 로 최신값 즉시 수신 + - 현장 수가 늘어도(10·50곳) 브로커가 확장 처리 +- **중요**: 0xAA 프레임/파서/빌더(공용 `ErvProtocol`)는 **그대로 유지**. "raw TCP" 대신 "MQTT 페이로드"로 운반만 바뀜. + +### (B) 브라우저 ↔ 서버 — 굳이 MQTT 아니어도 됨 +- 브라우저는 raw MQTT 불가 → **MQTT-over-WebSocket** 필요(복잡도 증가). +- 모니터링 대시보드엔 **현재 1초 HTTP 폴링으로 충분**(트래픽 미미). +- 진짜 실시간 푸시가 필요하면 WebSocket(또는 MQTT-WS)로 전환 가능하나 필수는 아님. + +--- + +## 4. 트레이드오프 / 주의 + +- MQTT는 **브로커(Mosquitto)** 를 미니PC에 추가로 운영해야 함(구성 요소 증가). +- **AWS IoT Core 직결은 EW11 클라이언트 인증서 미지원으로 곤란** (`260603_EW11_클라우드전송_검토.md` 참조) → MQTT로 간다면 **자체 Mosquitto(user/pass + 서버 TLS)** 가 현실적. +- 현재 raw TCP + HTTP 폴링도 3현장 모니터링·제어엔 충분히 동작 중. +- MQTT 이득이 큰 경우: **현장 수 증가 / 끊김 잦은 망 / 신뢰성·표준 IoT 스택 정렬**. + +--- + +## 5. 권장 + +| 상황 | 권장 | +|------|------| +| 현장 3곳 고정 + 단순 운영 | **현행 유지** (raw TCP + HTTP 폴링) — 가장 간단 | +| 현장 확장 / 끊김 감지·신뢰성·표준화 중요 | **(A) 장치↔서버만 MQTT(Mosquitto) 전환**, 브라우저는 HTTP 유지 | + +--- + +## 6. MQTT 전환 시 작업 범위 (참고) + +전환해도 **변경은 전송 계층에 한정**된다. + +- **EW11 설정**: TCP Client → **MQTT** 모드 (브로커 주소, Client ID, user/pass, publish/subscribe 토픽) +- **미니PC**: Mosquitto 브로커 설치(+user/pass, TLS) +- **수집서버(ErvCollector)**: 현장별 TCP 리스너 → **MQTT 구독자**로 교체 + - `erv/+/status` 구독 → 기존 `FrameParser`/`StatusDecoder` 그대로 사용 + - 제어 시 `erv/{site}/control` 에 `CtrlFrame.*` 결과를 **발행** + - 온라인/오프라인은 **LWT** + retained 로 처리(SiteHub 의 30초 추정 대체) +- **변경 없음**: 공용 프로토콜(`ErvProtocol` — 0xAA 프레임/CRC/STATUS/CTRL), 웹 대시보드(HTTP API 유지), WPF 대시보드, 프로토콜 문서(장치 페이로드 규격 동일) + +--- + +> 결론: MQTT는 **장치↔서버 구간(①)** 에 의미가 있고, 0xAA 규격을 유지한 채 전송만 교체하면 된다. +> 3현장 검증을 먼저 마치고, 확장 시점에 (A)만 MQTT로 전환하는 단계적 접근을 권장한다. diff --git a/TestProgram/WebDashBoard/WSL_설치_실행_가이드.md b/TestProgram/WebDashBoard/WSL_설치_실행_가이드.md new file mode 100644 index 0000000..dfd68ea --- /dev/null +++ b/TestProgram/WebDashBoard/WSL_설치_실행_가이드.md @@ -0,0 +1,289 @@ +# WSL2 설치 → ErvCollector 실행 가이드 (윈도우 PC) + +미니PC 구입 전, **윈도우 PC + WSL2(Ubuntu)** 에서 수집/모니터·제어 서버(`ErvCollector`)와 +InfluxDB·Grafana 를 띄워 전체 파이프라인을 검증하기 위한 단계별 가이드. + +> 대상: `TestProgram/WebDashBoard/ErvCollector` +> 순서대로 복사·붙여넣기 하면 됩니다. (Ubuntu 24.04 기준) + +--- + +## 0. 사전 요약 (무엇을 깔고 띄우나) + +| 구성요소 | 역할 | 포트 | +|---|---|---| +| ErvCollector(.NET) | 현장 EW11 TCP 수신 + 웹 대시보드/제어 API | 6001~6003(수집), 8080(HTTP) | +| InfluxDB OSS 2.x | 시계열 데이터 24시간 저장(1년 보관) | 8086 | +| Grafana | 장기 분석 대시보드(선택) | 3000 | + +--- + +## 1. WSL2 + Ubuntu 설치 (Windows PowerShell, 관리자) + +```powershell +wsl --install -d Ubuntu-24.04 +# 설치 후 재부팅 → Ubuntu 최초 실행 시 사용자/암호 설정 +wsl --status # 버전 2 확인 +wsl --update +``` + +이후 명령은 모두 **Ubuntu(WSL) 터미널** 안에서 실행한다. + +--- + +## 2. WSL systemd 활성화 (서비스 자동실행용) + +```bash +sudo tee /etc/wsl.conf >/dev/null <<'EOF' +[boot] +systemd=true +EOF +``` +```powershell +# Windows PowerShell 에서 WSL 재시작 +wsl --shutdown +``` +다시 Ubuntu 터미널을 열고 확인: +```bash +systemctl is-system-running # running 또는 degraded 면 OK +``` + +--- + +## 3. .NET 10 SDK 설치 + +```bash +sudo apt-get update +sudo apt-get install -y dotnet-sdk-10.0 || { + # 패키지가 없으면 공식 스크립트로 설치 + curl -sSL https://dot.net/v1/dotnet-install.sh | bash /dev/stdin --channel 10.0 + echo 'export PATH="$HOME/.dotnet:$PATH"' >> ~/.bashrc && source ~/.bashrc +} +dotnet --version +``` + +--- + +## 4. InfluxDB OSS 2.x 설치 + 초기 설정 + +```bash +# 저장소 등록 및 설치 +curl -s https://repos.influxdata.com/influxdata-archive_compat.key \ + | sudo gpg --dearmor -o /usr/share/keyrings/influxdata.gpg +echo "deb [signed-by=/usr/share/keyrings/influxdata.gpg] https://repos.influxdata.com/debian stable main" \ + | sudo tee /etc/apt/sources.list.d/influxdata.list +sudo apt-get update && sudo apt-get install -y influxdb2 influxdb2-cli +sudo systemctl enable --now influxdb + +# 초기 설정 : org=herv, bucket=erv, 보관 1년(8760h), 토큰을 직접 지정 +influx setup \ + --org herv --bucket erv --retention 8760h \ + --username admin --password 'change-this-pw' \ + --token herv-erv-token-0001 \ + --force +``` + +> 위 `--token herv-erv-token-0001` 값을 그대로 `appsettings.json` 의 `Influx.Token` 에 넣으면 된다. +> (토큰을 따로 확인하려면 `influx auth list`) + +--- + +## 5. (선택) Grafana 설치 + +```bash +sudo apt-get install -y apt-transport-https software-properties-common +curl -s https://apt.grafana.com/gpg.key | sudo gpg --dearmor -o /usr/share/keyrings/grafana.gpg +echo "deb [signed-by=/usr/share/keyrings/grafana.gpg] https://apt.grafana.com stable main" \ + | sudo tee /etc/apt/sources.list.d/grafana.list +sudo apt-get update && sudo apt-get install -y grafana +sudo systemctl enable --now grafana-server +``` +- 브라우저에서 `http://localhost:3000` (초기 admin / admin) +- Connections → Data sources → **InfluxDB** 추가 + - Query language: **Flux** + - URL: `http://localhost:8086` + - Organization: `herv`, Token: `herv-erv-token-0001`, Default bucket: `erv` +- 패널 쿼리 예시(거실 PM2.5 추이): + ```flux + from(bucket: "erv") + |> range(start: v.timeRangeStart, stop: v.timeRangeStop) + |> filter(fn: (r) => r._measurement == "erv_room" and r._field == "pm25" and r.site == "site01" and r.room == "1") + ``` + +--- + +## 6. 프로젝트 가져오기 + +> ⚠️ `ErvCollector` 는 공용 라이브러리 **`ErvProtocol`**(경로상 `HERV/TestProgram/ErvProtocol`)을 프로젝트 참조한다. +> (csproj: `..\..\ErvProtocol\ErvProtocol.csproj`) → 빌드 시 이 폴더가 **상대경로로 함께 있어야** 한다. + +**방법 1 — 원본 위치에서 바로 빌드 (가장 간단, 권장)** +```bash +cd /mnt/d/project/nuvoton/HERV/TestProgram/WebDashBoard/ErvCollector +# ../../ErvProtocol 가 /mnt/d/.../HERV/TestProgram/ErvProtocol 로 자동 해석됨 +``` +> `/mnt` 는 다소 느리지만 경로 문제 없이 동작. + +**방법 2 — 리눅스 홈으로 복사 (빌드 빠름, 상대구조 유지 필수)** +```bash +mkdir -p ~/herv +cp -r /mnt/d/project/nuvoton/HERV/TestProgram/ErvProtocol ~/herv/ErvProtocol +cp -r /mnt/d/project/nuvoton/HERV/TestProgram/WebDashBoard ~/herv/WebDashBoard +cd ~/herv/WebDashBoard/ErvCollector +# ../../ErvProtocol → ~/herv/ErvProtocol (깊이 일치) ✓ +``` + +### appsettings.json 수정 +```bash +nano appsettings.json +``` +- `Influx.Token` → `herv-erv-token-0001` (4장에서 지정한 값) +- `Http.Prefix` → 로컬 검증은 `http://localhost:8080/`, **LAN 의 EW11 접속까지** 받으려면 `http://*:8080/` +- (권장) `Http.Token` → 임의의 제어 인증 토큰 지정 + +--- + +## 7. 빌드 & 실행 + +```bash +# 6장에서 정한 ErvCollector 폴더에서 (방법1: /mnt/d/... , 방법2: ~/herv/WebDashBoard/ErvCollector) +dotnet run # 참조된 ErvProtocol 라이브러리도 자동으로 함께 빌드됨 +``` +정상 기동 로그: +``` +ErvCollector 시작. Influx=http://127.0.0.1:8086 bucket=erv 샘플주기=10s + HTTP 대시보드/제어 ← http://localhost:8080/ + 현장 'site01' ← TCP 포트 6001 대기 + 현장 'site02' ← TCP 포트 6002 대기 + 현장 'site03' ← TCP 포트 6003 대기 +``` +→ **Windows 브라우저**에서 `http://localhost:8080/` 접속(WSL localhost 는 Windows 와 공유됨). + +--- + +## 8. 동작 검증 (EW11 없이) + +`ErvCollector` 실행 중인 상태에서, **다른 Ubuntu 터미널**을 열고 데모 STATUS 프레임을 주입: + +```bash +python3 - <<'PY' +import socket +# STATUS(0x81) 78바이트 예시 프레임 (PC_ERV_Protocol.md) +frame = bytes.fromhex(("AA 81 49 01 02 01 03 01 01 01 00 1E 00 32 01 2C 02 BC 00 00 " + "01 00 16 00 23 00 B4 02 6C 03 05 00 2A 03 00 00 30 00 46 02 08 03 84 02 03 00 58 04 " + "01 00 0C 00 12 00 5A 01 E0 04 00 00 0F 01 00 00 21 00 37 01 2C 02 D0 02 09 00 3C 02 EB 43").replace(" ","")) +s=socket.create_connection(("127.0.0.1",6001)) # 현장1 포트 +import time +for _ in range(20): + s.sendall(frame); time.sleep(1) # 1초마다 1프레임 +s.close() +PY +``` + +확인: +```bash +# 최신 상태 JSON (site01 online:true 로 채워짐) +curl -s http://localhost:8080/api/latest | head -c 400; echo + +# 제어 테스트 (전원 OFF 프레임을 site01 소켓으로 송신 → 콜렉터 로그에 '송신' 찍힘) +curl -s -X POST http://localhost:8080/api/control \ + -H "Content-Type: application/json" \ + -H "X-Auth-Token: <설정한 Http.Token, 없으면 생략>" \ + -d '{"site":"site01","action":"power","value":0}' +``` +- 브라우저 `http://localhost:8080/` 상단 칩이 **서버연동**, 현장1 점이 초록(온라인)으로 표시. +- InfluxDB 적재 확인: + ```bash + influx query 'from(bucket:"erv") |> range(start:-10m) |> filter(fn:(r)=>r._measurement=="erv_room") |> limit(n:5)' + ``` + +--- + +## 9. (선택) 24시간 자동 실행 — systemd 서비스 + +```bash +# ErvCollector 폴더에서 게시(참조 ErvProtocol 포함 단일 폴더로 묶임) +dotnet publish -c Release -o ~/erv-publish + +sudo tee /etc/systemd/system/erv-collector.service >/dev/null < 방법 B 의 WSL 내부 IP 는 재부팅마다 바뀌므로 재실행 필요(방법 A 가 편함). + +**Windows 방화벽 인바운드 허용** (관리자 PowerShell): +```powershell +New-NetFirewallRule -DisplayName "ERV Collector" -Direction Inbound -Protocol TCP -LocalPort 6001-6003 -Action Allow +New-NetFirewallRule -DisplayName "ERV Web" -Direction Inbound -Protocol TCP -LocalPort 8080 -Action Allow +``` + +EW11(IOTService) 설정: TCP Client / Server=윈도우 PC IP / Port=현장별 6001~6003 / 115200 8N1 / AES / Keepalive. + +--- + +## 11. 종료 · 재시작 · 트러블슈팅 + +```bash +# 서비스 제어 +sudo systemctl restart erv-collector +sudo systemctl status influxdb grafana-server erv-collector + +# 포트 점유 확인 +ss -ltnp | grep -E '6001|6002|6003|8080|8086' +``` + +| 증상 | 원인 / 조치 | +|---|---| +| `HTTP 서버 시작 실패` | `Http.Prefix` 가 `+`/`*` 인데 권한 부족 → WSL(Linux)에선 보통 OK. Windows 직접 실행 시 `localhost` 사용 | +| `Influx write FAIL: 연결 거부` | InfluxDB 미기동 → `sudo systemctl start influxdb`, 토큰/org/bucket 확인 | +| 브라우저에서 8080 접속 안됨 | WSL localhost 공유는 보통 자동. 안되면 `wsl --shutdown` 후 재시도 / 방화벽 | +| EW11 이 못 붙음 | 10장(mirrored/portproxy + 방화벽), `Http.Prefix=http://*:8080/`, 같은 서브넷 여부 | +| `dotnet` 없음 | 3장 재확인, `source ~/.bashrc` | + +--- + +## 12. 참고 문서 +- 수집서버 상세: `ErvCollector/README.md` +- 프레임 규격: `../TestProgram/PC_ERV_Protocol.md` +- EW11 클라우드 전송 검토: `../EW11_RS485 TO WIFI/260603_EW11_클라우드전송_검토.md` diff --git a/TestProgram/사양서_260604.txt b/TestProgram/사양서_260604.txt new file mode 100644 index 0000000..c8f8c26 --- /dev/null +++ b/TestProgram/사양서_260604.txt @@ -0,0 +1,80 @@ +개발언어 : C# WPF DASHBOARD 스타일 +각 선택, 토글, 슬라이드, 숫자는 변경 가능하고 통신으로 해당 값 표시 +예외인 경우 (수정 못함) 표시 + +제 목 : HuevenEco DL 각실제어시스템 대시보드 +만든이 : 전경선 +만든날 : 2026.06.3 + +구성 : +통신 제어 및 상태 +통신포트 +보레이트 : 115200BPS N81 +연결 / 연결해제 +통신시작 / 통신 중지 + +ERV 제어 및 상태 +전원 ON / OFF > 토글 +ERV 리셋 > 토글 + +운전모드 +환기 / 자동 / 공청 / 바이패스 > 선택 +스마트수면 / 쾌적조리 / 안심회복 > 토글 +풍량 0 / 1 / 2 / 3 / 4 > 선택 (자동은 제외) +(꺼짐)예약 0 ~ 8시간 > 숫자 +후드연동 ON / OFF > 토글 +자동운전 상태 +분산 / 집중 > 표시 (수정 못함) +각실 부하점수 및 최종 풍량 > 표시 (수정 못함) +거실 / 침실1 / 침실2 / 침실3 > 숫자 표시 (수정 못함) +공기질센서 히스테리시스 제어 및 상태 + +ECO / NORMAL / TURBO > 선택 (공기질센서 히스테리시스값 적용) +공기질센서 히스테리시스값 PM2.5 PM10 VOC CO2 > 숫자 +풍량 VSP 제어 및 상태 +환기1 SA / EA > 숫자 +환기2 SA / EA > 숫자 +환기3 SA / EA > 숫자 +환기4 SA / EA > 숫자 +바이패스 SA / EA > 숫자 +공기청정1 SA / EA > 숫자 +공기청정2 SA / EA > 숫자 +공기청정3 SA / EA > 숫자 +공기청정4 SA / EA > 숫자 + + +각실 제어 및 상태 +거실 +댐퍼상태 ON / OFF > 토글 +공기질센서값 PM2.5 PM10 VOC CO2 > 숫자 +공기질 상태 좋음 / 보통 / 나쁨 / 매우나쁨 > LED 색상 및 숫자 표시 (수정 못함) +LED 디밍 0 ~ 9 > 슬라이드 + +침실1 +댐퍼상태 ON / OFF > 토글 +공기질센서값 PM2.5 PM10 VOC CO2 > 숫자 +공기질 상태 좋음 / 보통 / 나쁨 / 매우나쁨 > LED 색상 및 숫자 표시 (수정 못함) +LED 디밍 0 ~ 9 > 슬라이드 + +침실2 +댐퍼상태 ON / OFF > 토글 +공기질센서값 PM2.5 PM10 VOC CO2 > 숫자 +공기질 상태 좋음 / 보통 / 나쁨 / 매우나쁨 > LED 색상 및 숫자 표시 (수정 못함) +LED 디밍 0 ~ 9 > 슬라이드 + +침실3 +댐퍼상태 ON / OFF > 토글 +공기질센서값 PM2.5 PM10 VOC CO2 > 숫자 +공기질 상태 좋음 / 보통 / 나쁨 / 매우나쁨 > LED 색상 및 숫자 표시 (수정 못함) +LED 디밍 0 ~ 9 > 슬라이드 + +로그 데이터 출력 및 저장 +날짜.시간 +ERV 운전모드 및 풍량, 연동상태 +자동운전 상태 +분산 / 집중 상태 +각실 부하점수 및 최종 풍량 +거실 / 침실1 / 침실2 / 침실3 +ECO / NORMAL / TURBO +공기질센서 히스테리시스값 PM2.5 PM10 VOC CO2 +각실별 댐퍼 상태, 공기질센서값, 공기질 상태, LED 디밍값 \ No newline at end of file diff --git a/doc/260602_소스_개발사양서_260318.md b/doc/260602_소스_개발사양서_260318.md new file mode 100644 index 0000000..266cf65 --- /dev/null +++ b/doc/260602_소스_개발사양서_260318.md @@ -0,0 +1,110 @@ +# 소스 ↔ 개발사양서 비교 분석 + +- **작성일**: 2026-06-02 +- **대상 사양서**: `각실제어시스템_개발사양서_DL_동작로직_260318.pptx` (2026.03.18, 전경선 수석) +- **대상 소스**: `d:\project\nuvoton\HERV\program\User\` (Nuvoton NANO100SE3BN, arm-gnu-gcc 빌드) +- **시스템**: 각실제어 시스템(DL) — ERV 본체 + 각실 디퓨저(거실=room1, 침실1~3=room2~4) + +> 검증 방식: 핵심 불일치 항목(쾌적조리 풍량, 스마트수면, 공기질 색상등급)은 소스 직접 확인, +> 광범위 항목은 다중 탐색으로 수집 후 교차 확인. + +--- + +## 1. 요약 (Conclusion) + +| 구분 | 항목 수 | 비고 | +|------|--------|------| +| ✅ 일치 | 9 | 센서 임계값, 집중/전실 판정, 안심회복, LED 등 | +| ❌ 불일치/미반영 | 3 | 쾌적조리 풍량, 스마트수면 26.03.18 개정, 공기질 색상등급 | +| ⚠️ 확인 필요 | 2 | 팬 VSP 4단/공청 값, 센서 주기 | + +--- + +## 2. ✅ 일치하는 항목 + +| 사양 항목 | 사양값 | 코드 | 위치 | +|---|---|---|---| +| 센서→풍량단계 임계값 (슬라이드5) | CO2 600/700/800/900, VOC 250/300/350/400, PM2.5 15/30/50/70 | `m_CO2/VOC/PM2_5_Level_1~4` 기본값 동일 (CO2는 히스테리시스 50 적용) | `My_Uart.c:1313-1326` | +| 3종 센서 Max로 풍량 결정 | 최대 등급 채택 | CO2\|VOC\|PM2.5 OR 비트 → 0~4단 | `My_system.c:890-935` | +| 집중/전실 판정 | [최대−2번째]≥2 → 집중 | `(vars[0].value - vars[1].value) >= 2` | `My_system.c:1080, 1108` | +| 집중모드 최소시간 | 5분 (최신) | `Focus_Mode_RunTime = 3000` (=5분, 100ms×3000) | `My_system.c:1087, 1115` | +| 풍량 최대 4단 | 4단 | `if(Tmp_Air_Volume>4)=4` | `My_system.c:1179` | +| 안심회복 모드 | 침실1 음압(급기X/배기O), 타실 급기O/배기X, **2단** | 선택실 SA=0/RA=110, 타실 SA=110/RA=0, `Set_Fan_Mode=2` | `My_system.c:732-770` | +| 디퓨저 LED | 댐퍼 1개라도 열리면 ON, 밝기 0~9 | SA\|RA≠0 → ON, `Light_Bright` 0~9 | `My_system.c:714-724` | +| 공청 시 배기팬 OFF | 공청=급기만 | 공청 1~4단 EA팬 duty=0 | `MyMotor.c:1294-1307` | +| 팬 VSP 기본값(환기 1~3단) | 슬라이드13: 1단 EA56/SA57, 2단 65/67, 3단 72/75 | `s_FAN2/1_VEN_*` 동일값 | `MyControl.c:124-152` | + +### 안심회복 모드 상세 (사양 대비 정확 일치) +- 사양: 급기(SA) 거실O 침실1X 침실2O 침실3O / 배기(RA) 거실X 침실1O 침실2X 침실3X, 환기 2단 +- 코드: 전실 SA=110/RA=0으로 초기화 후 `Ext_Select_Room`(침실1)만 SA=0/RA=110 역전 → 사양과 동일 + +--- + +## 3. ❌ 불일치 / 미반영 항목 (소스 직접 확인) + +### 3.1 쾌적조리 모드 ERV 풍량 — 사양 3단 vs 코드 **4단** +- 사양(슬라이드9): "H-ERV 환기모드, 풍량 **3단계** (전실 급기 댐퍼 ON)" +- 코드: `Tmp_Air_Volume = 4;` → **4단** (`My_system.c:1030`) +- 운전모드도 사양은 환기모드(MODE_VENTILATION)이나 코드는 `Set_Run_Mode = MODE_AUTO` (`My_system.c:1026`) +- 급기 전실 ON / 배기 전실 OFF, 후드 3단 연동(`Hood_Fan_Mode=3`)은 일치 + +### 3.2 스마트수면 모드 — 26.03.18 개정분 **미반영** (코드는 구버전 로직) +이력관리 "2026.03.18 자동, 수면 모드 수정(9P)" 항목이 코드에 미적용: + +| 26.03.18 사양 | 코드 현재 | 위치 | +|---|---|---| +| 풍량 **1단 고정** | `if(Tmp_Air_Volume>=2) Tmp_Air_Volume-=1` (자동값 −1, 구버전) | `My_system.c:1191-1200` | +| 초기 **거실 CLOSE / 침실1~3 OPEN** | 전용 댐퍼 패턴 **없음** | - | +| **1시간마다 CO2≥1000 OPEN** | 미구현 (일반 focus mode `vars 차이≥2`만 사용) | `My_system.c:1080` | + +- 진입부(`Ext_Run_Mode==4`)는 `Set_Fan_Mode=1` 설정하나, 이후 PASS_VOLUME에서 매 주기 센서값 재계산 후 −1 → 실제로는 "자동−1"로 동작. + +### 3.3 공기질 색상등급(슬라이드6, 26.03.18) — **전체 비활성(dead code)** +- `Air_Quality_color_process()` 시작부 `return(0);` 로 즉시 반환 → 색상/문구(좋음·보통·나쁨·매우나쁨) 로직 전부 미동작 (`My_system.c:1216`) +- 임계값도 슬라이드6(CO2 700/1000/1300)이 아니라 `m_Level`(600/700/800/900) 기준으로 작성됨 → 살리더라도 26.03.18 등급표와 불일치 + +--- + +## 4. ⚠️ 확인·주의 필요 + +### 4.1 팬 VSP 4단 / 공청 값 +- 환기 4단: 코드 SA87/EA84 vs 슬라이드13 SA95/EA92 (단 슬라이드14·15 실측은 86/85 — "4단 250→230CMH 소음저감"(25.10.17) 반영값에 근접) +- 공청: 코드 SA 46/51/56/60 vs 사양 전압표 SA 66/70/77 → 상이 +- 이 값들은 VSP 테스트모드 + EEPROM으로 **현장 튜닝**되는 값이라 컴파일 기본값과 사양 실측표 차이는 정상일 수 있음. **EEPROM 저장값 별도 확인 권장** + +### 4.2 센서 주기 +- 사양: "센서 주기 30초 단위" +- 코드: 분배기 폴링 1초(`InCom_polling_timer=100`×10ms) → SEN66 내부 측정주기와 폴링주기 구분 확인 필요 + +--- + +## 5. 🔗 직전 작업(CVnet 삭제)과의 연관 — DL_Sinario 처리 + +- 월패드→각실 시나리오 명령 `DL_Sinario_Process()`(CMD 0~5: 전실/침실 급배기 패턴)는 **CVnet 홈넷통신으로만 트리거**되던 코드. +- 2026-06-02 작업에서 CVnet 삭제 → DL_Sinario가 dead code가 되어 **`DL_Sinario_Process()` 및 관련 참조 일괄 제거 완료**. + - 제거: `My_system.c`(함수+`DL_Sinario_CMD`), `My_Uart.c`(0x61 호출부+extern), `My_define.h`(extern) +- 안심회복/쾌적조리/스마트수면(`Ext_Run_Mode`)은 룸콘 "S Mode Select" 경로라 영향 없음. +- ※ 월패드(씨브이넷) 기반 각실 제어가 사양상 필요하면 CVnet 삭제와 충돌 → 방향 재확인 필요. + +--- + +## 6. 후속 작업 후보(TODO) + +1. 쾌적조리 ERV 풍량 4단 → **3단** 수정 (`My_system.c:1030`, 운전모드 검토) +2. 스마트수면 26.03.18 로직 구현 (1단 고정 / 거실 CLOSE·침실 OPEN / 1시간마다 CO2≥1000 OPEN) +3. 공기질 색상등급(`Air_Quality_color_process`) 활성화 + 슬라이드6 임계값 반영 +4. 팬 VSP 4단/공청 EEPROM 저장값 확인 +5. 260520(5월판) 사양서와 추가 비교 + +--- + +## 부록. 주요 소스 위치 + +| 파일 | 역할 | +|------|------| +| `My_system.c` | 모드 제어(`Ext_Run_Mode`), 센서→풍량/색상, 집중/전실, 팬 duty 변환 | +| `My_Uart.c` | 센서 임계값/기본값, 분배기 파싱, VSP 테스트, PC 메뉴 | +| `MyMotor.c` | 디퓨저 댐퍼(`Diffuser_Damper_process`), 팬 속도(`Fan_Speed_*`), BLDC_SPEED_TABLE | +| `MyControl.c` | 팬 duty 기본값 / EEPROM 저장·로드 | +| `My_define.h` | 모드·핀·EEPROM 주소 정의 | +| `My_RJ2.c` | 룸콘(232) 프로토콜, VSP 모드, Set_Run/Fan_Mode | diff --git a/doc/260602_소스_개발사양서_260520.md b/doc/260602_소스_개발사양서_260520.md new file mode 100644 index 0000000..baa62eb --- /dev/null +++ b/doc/260602_소스_개발사양서_260520.md @@ -0,0 +1,116 @@ +# 소스 ↔ 개발사양서 비교 분석 (260520) + +- **작성일**: 2026-06-02 +- **대상 사양서**: `각실제어시스템_개발사양서_DL_동작로직_260520.pptx` (2026.05.20, 전경선 수석) +- **대상 소스**: `d:\project\nuvoton\HERV\program\User\` (Nuvoton NANO100SE3BN, arm-gnu-gcc 빌드) +- **시스템**: 각실제어 시스템(DL) — ERV 본체 + 각실 디퓨저(거실=room1, 침실1~3=room2~4) +- **연관 문서**: `260602_소스_개발사양서_260318.md` + +> 검증 방식: 핵심 항목(자동모드 풍량 산출, 쾌적조리, 스마트수면)은 소스 직접 확인. + +--- + +## 0. 260318 → 260520 주요 변경점 + +- 이력관리에 **"2026.05.20 동작로직 수정 (26.04.28 DL 자료 기반) (9~10P)"** 추가 +- **자동모드 로직 전면 개편** (슬라이드9~10): + - 부하점수(Score) 기반 풍량 단수 결정 + - Eco / Normal / Turbo 모드별 임계값 (3세트) + - **4종 센서** (CO2 / PM2.5 / PM10 / VOC) — PM10 추가 + - **거실 가중치 및 P_max 강제보상 삭제** → 점수 기반으로 직관적 동작 + - 히스테리시스(데드밴드) 모드·센서별 정의 +- 용어 변경: 전실모드 → **분산모드**, 집중급기 → **집중모드** +- 배선도: 각실분배기 PBA가 휴벤ECO에 부착, AC전원 2구 필요 + +--- + +## 1. ✅ 일치 (260318과 동일 유지) + +| 항목 | 사양(260520) | 코드 | 위치 | +|---|---|---|---| +| 집중/분산 판정 | dP = P_max − P_2nd ≥ 2 → 집중, 아니면 분산, P_max=0 → 전체 OFF | `(vars[0].value - vars[1].value) >= 2` (qsort 내림차순) | `My_system.c:972, 1080` | +| 집중 시 댐퍼 | P_max 실만 ON(100%), 나머지 OFF | Focus_Mode 시 Focus_Room만 110, 타실 0 | `My_system.c:1126~` | +| 안심회복 | 침실1 음압(급기X/배기O), 환기 2단 | 선택실 SA=0/RA=110, 타실 SA=110/RA=0, Fan=2 | `My_system.c:732-770` | +| 공청 PM2.5 단계 | 0~14정지 / 15~29 / 30~49 / 50~69 / 70~ | `m_PM2_5_Level` 15/30/50/70 | `My_Uart.c:1323-1326` | +| 풍량 CMH | 환기 100/150/200/250, 공청 80/100/120/150, 바이패스 150 | 단계 구조 동일, 공청 EA팬 OFF | `MyMotor.c:1294-1307` | +| 디퓨저 LED | 댐퍼 1개라도 열리면 ON, 0~9 디밍, 단색 | SA\|RA≠0 → ON, `Light_Bright` 0~9 | `My_system.c:714-724` | +| 팬 VSP(환기 1~3단) | 1단 EA56/SA57, 2단 61/63, 3단 67/69 | `s_FAN*_VEN_*` 동일 | `MyControl.c:124-152` | + +--- + +## 2. ❌ 핵심 불일치 — 자동모드 로직(26.04.28 개정) 미반영 + +현재 코드는 **개정 전(점수기반 이전) 로직**으로, 사양이 삭제하라고 명시한 P_max 기반 동작이 남아 있음. + +### 2.1 풍량 단수 산출 방식 상이 (가장 큰 차이) +- **사양 260520**: 부하점수 Score = 4실 Level 합산(0~16) → + **0: OFF / 1~4: 1단 / 5~8: 2단 / 9~12: 3단 / 13~16: 4단** +- **코드 현재**: + - 분산: `Tmp_Air_Volume = 4실 합산` 후 `if(>=4) =4` (= min(합,4)) — `My_system.c:935, 948` + - 집중: `Tmp_Air_Volume = vars[0].value` (= P_max) — `My_system.c:1082` + +| 예시 (Score) | 사양 최종단수 | 코드 최종단수 | +|---|---|---| +| 합 3 (1,1,1,0) 분산 | 1단 | **3단** | +| 합 6 (2,2,1,1) 분산 | 2단 | **4단(cap)** | +| 침실 단독 4 (집중) | 1단 | **4단(P_max)** | +| 합 16 (4,4,4,4) | 4단 | 4단 | + +→ 슬라이드10 QA 진리표(7개 케이스)로 유닛 테스트 검증 필요. + +### 2.2 Eco / Normal / Turbo 모드별 임계값 미구현 +- 사양: 모드별 CO2/PM2.5/PM10/VOC 임계표 3세트 + (예: Normal CO2 0~700 / 701~1000 / 1001~1300 / 1301~1600 / 1601~) +- 코드: 단일 임계값 `m_*_Level`(CO2 600/700/800/900) 한 세트, 모드 분기 없음 + +### 2.3 4종 센서 중 PM10 미사용 +- 사양: CO2 / PM2.5 / PM10 / VOC **4종**으로 Level 산출 +- 코드: `room_CVP_quality = CO2 | VOC | PM2.5` (3종). `SEN66_pm10p0`는 수신만 하고 Level 계산에 미사용 — `My_system.c:890` + +### 2.4 히스테리시스(데드밴드) 부분 적용 +- 사양: 모드·센서별 하강 데드밴드 (CO2 −50, PM2.5 −2, PM10 −5, VOC −5/−3) +- 코드: **CO2만** `CO2_Histeresys=50` 적용, PM2.5/PM10/VOC 없음 — `My_system.c:673` + +--- + +## 3. ❌ 260318부터 이어진 미반영 (260520에서도 동일) + +| 항목 | 사양 260520 | 코드 | 위치 | +|---|---|---|---| +| 쾌적조리 ERV 풍량 | **3단** (각실 급기만 ON) | `Tmp_Air_Volume = 4` (4단), `Set_Run_Mode = MODE_AUTO` | `My_system.c:1026, 1030` | +| 스마트수면 | 1단 고정 / 초기 거실 CLOSE·침실 OPEN / 1시간마다 CO2≥1000 OPEN | 구버전 "자동−1", 전용 댐퍼·CO2 1시간 로직 없음 | `My_system.c:1191-1200` | +| 공기질 색상등급 | (구성 변경) | `Air_Quality_color_process()` `return(0)` dead code | `My_system.c:1216` | + +--- + +## 4. ⚠️ 확인 필요 (변동 없음) + +- 팬 VSP 4단: 코드 SA87/EA84 vs 사양(슬라이드11·12) SA86/EA85 (실측 기반) → EEPROM 저장값 확인 권장 +- 센서/제어 주기: 사양 "매 제어 주기(예 1분)" (슬라이드10) vs 코드 분배기 폴링 1초 + +--- + +## 5. 결론 + +260520의 핵심 개정(**자동모드 점수기반 풍량 + Eco/Normal/Turbo + PM10 + 모드별 히스테리시스**)은 현재 소스에 **거의 미반영** 상태. +다만 **집중/분산 판정(dP≥2) 및 댐퍼 개폐 패턴**은 이미 일치하므로, "풍량 단수 결정 로직"을 점수기반(Score 테이블 매핑)으로 교체하는 것이 핵심 작업. + +### 후속 작업 후보(TODO) +1. 자동모드 풍량을 **Score(0~16) → 단수(0/1/2/3/4)** 테이블 매핑으로 교체 (P_max·cap 방식 제거) +2. Eco/Normal/Turbo 모드별 임계표 도입 (현재 단일 `m_*_Level` → 3세트) +3. PM10(`SEN66_pm10p0`) Level 산출 반영 (3종 → 4종) +4. PM2.5/PM10/VOC 히스테리시스 추가 +5. 쾌적조리 3단 수정, 스마트수면 26.03.18 로직 구현 +6. 슬라이드10 QA 진리표(7케이스) 기반 검증 + +--- + +## 부록. 주요 소스 위치 + +| 파일 | 역할 | +|------|------| +| `My_system.c` | 자동모드 풍량 산출(`Air_Quality_damper_process`), 집중/분산, 시나리오 모드(`Ext_Run_Mode`) | +| `My_Uart.c` | 센서 임계값/기본값, 분배기 파싱(`Diffuser_parsing`), VSP 테스트 | +| `MyMotor.c` | 디퓨저 댐퍼, 팬 속도, BLDC_SPEED_TABLE | +| `MyControl.c` | 팬 duty 기본값 / EEPROM | +| `My_define.h` | 모드·핀·EEPROM 정의 | diff --git a/doc/HERV_Firmware_Analysis.pptx b/doc/HERV_Firmware_Analysis.pptx new file mode 100644 index 0000000..4b1e1db Binary files /dev/null and b/doc/HERV_Firmware_Analysis.pptx differ diff --git a/doc/HERV_MCU PINMAP & CONNECTOR.txt b/doc/HERV_MCU PINMAP & CONNECTOR.txt new file mode 100644 index 0000000..5c40168 --- /dev/null +++ b/doc/HERV_MCU PINMAP & CONNECTOR.txt @@ -0,0 +1,27 @@ +HERV MCU PIN-MAP & CONNECTOR + +MCU (STATUS_LED - PA.10) +MCU (CURRENT2 - PA.4) + +CN4, WHITE, TEMP1, ADC, MCU (TEMP_ADC1 - PA.0) +CN8, BLUE, TEMP2, ADC, MCU (TEMP_ADC2 - PA.1) + +CN11, WHITE, ROOM_UART, UART, MCU (ROOMCON_RX - PA.9, ROOMCON_TX - PA.8) +CN6, WHITE, HOOD, ACTIVE LOW, MCU (EX_SW - PA.11) +CN13, YELLOW, HOOD_485, 485, MCU (I485_TX - PB.1, I485_RX - PB.0, I485_DIR - PB.2) +CN17, BLACK, BUNBAGI_485, 485, MCU (E485_TX2 - PC.0, E485_RX2 - PC.1, E485_DIR2 - PC.7) +CN15, RED, HOMENET_485, 485, MCU (E485_TX - PB.5, E485_RX - PB.4, E485_DIR - PB.6) + +CN13, YELLOW, UV_LED1, MCU (UV_PW_ON - PA.5 , UV_ON - XT1_OUT) +CN16, YELLOW, UV_LED2, MCU (UV_PW_ON - PA.5 , UV_ON - XT1_OUT) + +CN12, BLUE, SA_FAN, MCU (BLDC_PW_ON - PB.7, VOLUME_1 - PA.2 , BLDC1_PWM_OUT - PB.11 , BLDC1_FG_IN - PE.5) +CN14, WHITE, EA_FAN, MCU (BLDC_PW_ON - PB.7, VOLUME_2 - PA.3 , BLDC2_PWM_OUT - PA.12, BLDC2_FG_IN - PA.13) + + +외기(OA), CN2 , GREEN, U1(15~18),MCU (PB.12,PB.13,PB.14,PB.8) +공청(AIR), CN10, YELLOW, U4 (11~14), MCU (PD.14,PD.7, PD.6,PB.3) +바이패스(BYPASS), CN5, RED, U2 (15~18), MCU (PA.6,PA.14,PA.15,PC.8) +배기(EA), CN3, BLACK, U1(11~14), MCU (PB.15,PC.14,PC.15,PC.6) +급기(SA), CN7, BLUE, U2(11~14), MCU (PC.9,PC.10,PC.11,PB.9) +환기(RA), CN9, WHITE, U4(15~18), MCU (PB.10,PC.2,PC.3,PD.15) \ No newline at end of file diff --git a/doc/VSP 테이블.pdf b/doc/VSP 테이블.pdf new file mode 100644 index 0000000..fae463b Binary files /dev/null and b/doc/VSP 테이블.pdf differ diff --git a/doc/VSP 테이블.pptx b/doc/VSP 테이블.pptx new file mode 100644 index 0000000..f335d26 Binary files /dev/null and b/doc/VSP 테이블.pptx differ diff --git a/doc/VSP 테이블_260615.png b/doc/VSP 테이블_260615.png new file mode 100644 index 0000000..c1c2113 Binary files /dev/null and b/doc/VSP 테이블_260615.png differ diff --git a/doc/pba_connector.png b/doc/pba_connector.png new file mode 100644 index 0000000..1027c66 Binary files /dev/null and b/doc/pba_connector.png differ diff --git a/doc/스마트폰_원격조종_RemoteControl_가이드.md b/doc/스마트폰_원격조종_RemoteControl_가이드.md new file mode 100644 index 0000000..2ad1494 --- /dev/null +++ b/doc/스마트폰_원격조종_RemoteControl_가이드.md @@ -0,0 +1,112 @@ +# 스마트폰에서 Claude Code 작업하기 — Remote Control 가이드 + +작성일: 2026-06-14 + +데스크톱(Windows + VS Code 확장)에서 진행 중인 Claude Code 세션을 스마트폰에서 그대로 조종하는 방법. +빌드·COM 포트·실보드 플래시 등 실제 작업은 **데스크톱에서** 실행되고, 폰은 지시·확인·승인 역할. + +--- + +## 0. 준비물 + +| 항목 | 내용 | +|---|---| +| 버전 | Claude Code **v2.1.51 이상** (모바일 푸시 알림은 v2.1.110+). 확인: 터미널 `claude --version` | +| 플랜 | **Pro / Max / Team / Enterprise** (API 키 인증 불가, claude.ai 계정 로그인 필요). 로그인/확인: `claude /login` | +| OS | Windows 지원. **터미널 CLI·VS Code 확장 둘 다 가능** | +| 팀/기업 | 관리자가 관리설정에서 "Remote Control" 토글을 켜둬야 함 | +| 폰 앱 | **Claude by Anthropic** (iOS App Store / Android Play) — 데스크톱과 같은 계정 로그인 | + +--- + +## 1. 데스크톱에서 Remote Control 시작 (택1) + +### A. VS Code 확장에서 (지금 쓰는 방식 — 가장 간단) +1. Claude 채팅 입력창에 **`/remote-control`** (또는 `/rc`) 입력 +2. 입력창 위 배너 → **"Open in browser"** 클릭하면 claude.ai/code로 연결 +3. ⚠️ VS Code에서는 QR 미표시·이름 지정 미지원 + +### B. 터미널 CLI에서 (QR·이름 지원, 권장) +```powershell +cd D:\project\nuvoton\HERV +claude remote-control --name "HERV" +``` +- 세션 URL 출력 + **스페이스바**를 누르면 QR 코드 표시 +- 터미널은 켜둔 채 유지(**Ctrl+C 금지**). 네트워크 끊겨도 ≤10분이면 자동 재연결 + +**선택 플래그** +- `--name "HERV"` : 세션 제목(목록에 표시) +- `--spawn worktree` : 기기별 독립 git worktree(파일 충돌 방지, git 저장소 필요) +- `--spawn session` : 정확히 1기기만 연결 허용 +- `--verbose` : 연결/도구 상세 로그 +- `--sandbox` : 파일시스템/네트워크 격리 + +### C. 이미 진행 중인 세션을 전환 +실행 중인 세션 입력창에 `/remote-control HERV` → 기존 대화 유지하며 활성화 + +--- + +## 2. 스마트폰에서 연결 + +1. **Claude 앱** 설치(데스크톱에서 `/mobile` 치면 다운로드 QR 표시) → 데스크톱과 **같은 계정** 로그인 +2. 연결 3가지: + - **QR 스캔**: 터미널 스페이스바로 띄운 QR을 앱으로 스캔 + - **세션 URL**: 터미널/배너의 URL 복사 → 폰 브라우저 붙여넣기 + - **세션 목록**: 앱 하단 **"Code" 탭** → 목록에서 "HERV"(**녹색 점 컴퓨터 아이콘**) 선택 + +--- + +## 3. 폰에서 할 수 있는 것 + +**가능** +- 메시지 전송 / 답변·변경(diff) 확인 +- **도구 권한 승인·거부** (Allow / Deny / Allow always) — 데스크톱과 실시간 동기화 +- `@`로 로컬 파일경로 자동완성 +- `/clear` `/compact` `/context` `/usage` `/exit` 등 + +**불가(로컬 전용)** +- `/plugin`(플러그인 선택기), `/resume`(세션 복구 대화) + +**푸시 알림(선택, v2.1.110+)** +- 폰 앱 로그인 → OS 알림 허용 → 데스크톱 `/config` → **"Push when Claude decides"** 켜기 +- 긴 작업 완료/결정 필요 시 알림. "notify me when X finishes" 식 요청도 알림 + +--- + +## 4. 핵심 제약 (이 프로젝트 기준 중요) + +- **데스크톱이 계속 켜져 있어야 함** — 절전/잠금 금지, 터미널·VS Code 종료 금지, 네트워크 유지 +- 빌드(`dotnet`, `bash build.sh`), **COM 포트 통신**, **실보드 플래시(`bash build.sh flash`)** 는 전부 데스크톱 실행 → 폰은 지시·확인 역할 +- 기본은 한 번에 한 기기 입력. 단절 >10분이면 세션 종료 → 재시작 필요 +- 보안: 아웃바운드 443(HTTPS)만 사용(인바운드 포트 안 염), TLS 암호화·단기 자격증명 + +--- + +## 5. 연결 종료 +- VS Code: 배너 X 버튼 +- 터미널: Ctrl+C +- 어디서나: `/exit` + +--- + +## 6. 문제 해결 + +| 증상/메시지 | 해결 | +|---|---| +| "claude.ai subscription / full-scope token 필요" | `claude /login` 재로그인 | +| "organization 정책으로 비활성" | 관리자가 claude.ai 관리설정에서 Remote Control 토글 켜기 | +| "Remote Control not yet enabled" | `CLAUDE_CODE_DISABLE_NONESSENTIAL_TRAFFIC`·`DISABLE_TELEMETRY`·`CLAUDE_CODE_USE_BEDROCK` 등 환경변수 제거 | +| QR 안 보임 | 터미널 창 넓히고 스페이스바 다시 | +| 세션 목록에 없음 | 데스크톱에서 `claude remote-control` 다시 실행, 터미널 실행 중인지 확인 | +| 상세 디버깅 | `claude remote-control --verbose` | + +--- + +## 7. 권장 사용 흐름 (이 프로젝트) + +1. 평소엔 데스크톱 VS Code 확장에서 작업 +2. 자리 비울 때 **`/rc` → Open in browser**(또는 터미널 `claude remote-control --name "HERV"` + QR)로 폰 연결 +3. 폰에서 진행 확인·권한 승인·간단 지시(예: "다음 단계 진행해", "빌드 결과 보여줘") +4. 실보드/COM 검증은 데스크톱을 켜둔 상태로 폰에서 원격 지시 + +> 공식 문서: https://code.claude.com/docs/en/remote-control diff --git a/doc/팀공유_이동작업_환경구성.md b/doc/팀공유_이동작업_환경구성.md new file mode 100644 index 0000000..60fbbcb --- /dev/null +++ b/doc/팀공유_이동작업_환경구성.md @@ -0,0 +1,64 @@ +# 팀 공유 · 이동 중 작업 환경 구성 (검토 메모) + +작성일: 2026-06-15 + +## 1. 배경 / 요구사항 +- 이동 중에도 지금처럼 **VS Code로 수정·저장**하는 방식을 유지하고 싶다. +- 기존 Google Drive 방식(수동 다운로드/업로드)은 번거롭고 버전 꼬임이 생겨 개선 필요. +- **다른 직원과 소스 공유**도 해야 한다. + +## 2. 결론 +**Git + 사내 원격 저장소(private)** 로 간다. +한 번에 세 가지를 해결: +1. 팀 공유 — 각자 clone, 수정 후 push, 누가 뭘 바꿨는지 추적 +2. 이동 중 작업 — 노트북에서 clone, 또는 브라우저 웹 IDE로 편집 +3. 변경 이력 — 현재 이 폴더는 git 저장소가 아니라 diff 추적 불가 → git 도입으로 영구 해결 + +> 폴더 동기화(Google Drive / OneDrive / Syncthing)는 여러 명이 동시에 수정하면 충돌 파일이 쌓여 **팀 공유에는 부적합**. 단독 백업 용도라면 OneDrive/Syncthing이 Drive보다 낫지만, 본 목적에는 Git 채택. + +## 3. 호스팅: 회사 Synology NAS (확정) +사내에 소스가 머무르고 직원 공유가 깔끔함. 내일 NAS에 Git 설치 후 진행 예정. + +### 방식 비교 +| 방식 | 특징 | 추천 상황 | +|---|---|---| +| **Git Server 패키지 (추천)** | 패키지 센터에서 `Git Server` 설치, SSH로 bare repo 접근. 가볍고 간단. | 소규모 팀(현재) | +| **GitLab (패키지/Docker)** | 머지요청·이슈·권한관리·웹 편집 등 풀기능 웹 UI. 무겁고 RAM 사용 큼. | 코드리뷰/PR 문화 필요 시 | + +→ 우선 **Git Server 패키지**로 시작, 필요해지면 GitLab으로 확장. + +### Git Server 방식 절차 (예시) +```bash +# NAS 측 (SSH 접속 후) — bare 저장소 생성 +git init --bare /volume1/git/HERV.git + +# 직원 PC 측 — clone +git clone ssh://사용자@NAS주소:포트/volume1/git/HERV.git +``` + +## 4. 로컬 준비 (NAS 연결 전, 오늘 가능) +원격 설정만 내일 하면 되도록 로컬 git을 먼저 초기화: +1. `.gitignore` 생성 — 빌드 산출물 제외, 소스·문서·PDF만 추적 + - 제외 대상: `program/build/`, C# `bin/` · `obj/`, `*.o *.d *.elf *.bin *.hex *.map` +2. `git init` + 첫 커밋 (현재 상태 스냅샷 → **이 시점부터 변경 이력 남음**) + +내일 NAS 작업: +```bash +git remote add origin ssh://사용자@NAS주소:포트/volume1/git/HERV.git +git push -u origin main +``` + +## 5. 이동 중 작업 옵션 (참고) +- **노트북 + git clone**: 가장 일반적. 평소처럼 VS Code 편집. +- **브라우저 웹 IDE**: GitLab 도입 시 웹 편집 가능(Git Server 단독은 미지원). +- **VS Code Remote Tunnel**: 집/사무실 PC에 `code tunnel` 켜두고 원격 접속 → 그 PC의 실제 파일·빌드툴·연결된 PBA 보드까지 그대로 사용. (빌드·실보드 시험을 이동 중에도 해야 할 때 유용) + +## 6. 주의 / 작업 범위 +- 모든 작업은 `D:\project\nuvoton\HERV` 폴더 내부에서만 진행 (외부 `D:\project\C#\` 등은 건드리지 않음). +- 빌드 산출물은 git에 올리지 않음(.gitignore 처리) — 저장소를 소스·문서 위주로 깨끗하게 유지. + +## 7. 다음 할 일 +- [ ] (오늘/원하면) 로컬 `git init` + `.gitignore` + 첫 커밋 +- [ ] (내일) NAS에 Git Server 패키지 설치, bare repo 생성 +- [ ] NAS를 remote로 추가하고 push +- [ ] 직원 계정/접근 권한 부여 및 clone 테스트 diff --git a/doc/펌웨어_정적분석_버그리포트.md b/doc/펌웨어_정적분석_버그리포트.md new file mode 100644 index 0000000..0c2c384 --- /dev/null +++ b/doc/펌웨어_정적분석_버그리포트.md @@ -0,0 +1,121 @@ +# HERV 펌웨어 정적분석 버그 리포트 + +작성일: 2026-06-15 +대상: `program/User/*.c`, `*.h` (펌웨어 전체) +방식: 영역별 정적분석(읽기 전용). **코드 수정 없음 — 검토용 목록** +표기: ✓ = 작성자가 직접 코드 확인 / (분석) = 분석에서 도출(미재확인) / [의심] = 추가 검증 필요 + +--- + +## 0. 우선순위 요약 (먼저 고칠 것) + +| # | 위치 | 심각도 | 한줄 | 검증 | +|---|------|--------|------|------| +| 1 | My_RJ2.c:617 | High | switch case 8 `break` 누락 → 공청3단 세팅이 4단 프리셋 덮어씀 | ✓ | +| 2 | My_RJ2.c:400 | High | `Command_request_type = 0;` 로 보류비트(HOOD/예약/Homenet래치) 전멸 | ✓ | +| 3 | My_bunbaeggi.c:869 | High | 예약시간 offset 오류: `[8]` 검사하고 값은 `[7]`(풍량)에서 읽음 | ✓ | +| 4 | MyControl.c:595 | High | 필터리셋 조건에 `Filter_timer_change` 중복(`Soja_timer_change` 오타) → 소자 리셋 누락 | (분석) | +| 5 | My_bunbaeggi.c:708·898 | Med | 수신 id(`buffer[3]`) 범위검증 없이 크기7 배열 인덱싱 → OOB 쓰기 가능 | (분석) | +| 6 | My_bunbaeggi.c:280 | Med | `Light_Bright[6]` 만 크기6(형제 배열은 7) → 거실2(id_2=6) 접근 시 OOB | ✓ | +| 7 | My_RJ2.c:110 | Med | `Reservation_process()` 주석처리 → 룸컨 예약(`Reserve_timer_sec`) 카운트다운 안 함 | ✓ | + +--- + +## 1. 통신 / 프로토콜 + +### My_RJ2.c (룸컨) +- **[High] My_RJ2.c:617 — `case 8` break 누락 (fall-through)** ✓ + - `case 8`(공청 3단 VSP) 끝에 `break`가 없어 `case 9`(4단)로 흘러감 → 공청 3단 세팅 시 4단 프리셋(`Test_Fan*_Air_4_dan`)까지 같은 값으로 오염. + - 제안: `case 8` 끝에 `break;` 추가. +- **[High] My_RJ2.c:400 — `Command_request_type = 0;` 전체 클리어** ✓ + - `if(Command_request_type & TYPE_SEND_FLAG)` 블록에서 `= 0;` 후 `&= ~TYPE_SEND_FLAG;`(죽은 코드). SEND_FLAG만 소비해야 하는데 같은 사이클에 set된 `TYPE_HOOD_STATE`/`TYPE_RESERVATION`/병합된 `Homenet_RJ_Request` 비트가 한 번에 사라져 후드·예약 변경이 룸컨에 유실. + - 비교: line 690~의 같은 패턴은 `&= ~TYPE_SEND_FLAG`만 함(불일치). + - 제안: `= 0;` → `&= ~TYPE_SEND_FLAG;` 로 교체, 필요한 비트만 명시적으로 클리어. +- **[Med] My_RJ2.c:712 — `Filter_Reset_Flag |= buffer[7]` 마스크 누락** + - EVENT 경로(line 462)는 `& 0x01` 마스크를 쓰는데 여기선 통째 OR → 상위비트 오염으로 의도치 않은 필터 리셋 가능. 제안: `& 0x01` 적용. +- **[Med][의심] My_RJ2.c:702-705 — AUTO 수신 시 `Fan_Mode` 미갱신** + - else 분기에서 AUTO면 `Set_Fan_Mode/Fan_Mode`를 갱신 안 한 채 line 718 `Set_Fan_Mode==Fan_Mode` 비교 → TYPE_FAN_SPEED 비트가 옛값으로 클리어/유지되어 풍량 명령 어긋남 가능. EVENT 분기(414-415)와 기준 통일 검토. + +### My_bunbaeggi.c (분배기/디퓨저 마스터) +- **[High] My_bunbaeggi.c:869 — 예약시간 byte offset 오류** ✓ + - `if(Rx_bunbaegi_buffer[8] & 0x80){ Set_Reserve_timer_sec = (uint32_t)(Rx_bunbaegi_buffer[7] & 0x7f)*3600; }` — 요청비트는 `[8]`에서 보고 값은 `[7]`(풍량 바이트)에서 읽음 → 예약시간이 풍량값으로 들어감. 제안: `[8]`에서 읽기. +- **[Med] My_bunbaeggi.c:708·898 (Diffuser/EachRoomCon parsing) — 수신 id 범위검증 없음** (분석) + - `id = Rx_bunbaegi_buffer[3];` 후 `SEN66_*[id]`, `Diffuser_Power[id]` 등 크기7 배열에 상한 체크 없이 인덱싱. 오염된 id(≥7)면 OOB 쓰기로 전역 손상. 제안: `if(id < 7)` 가드. +- **[Med] My_bunbaeggi.c:183/191 — RoomCon `Packet_Length`가 절대 29가 안 됨** (분석) + - case 3에서 무조건 39, case 4 RoomCon 분기도 39(주석은 `//29byte`). → case 28의 29B 완료처리 분기가 죽은 코드. 29B 응답 파싱 불가. 제안: 의도대로 case 4에서 `Packet_Length = 29;`. +- **[Low] My_bunbaeggi.c:813 — VSP 저장 트리거가 case 3(BYPASS)에만 존재** (분석) + - VEN/AIR VSP를 룸컨에서 바꾸면 `EEP_Save_Flag` 미설정 → 재부팅 후 유실 가능. 제안: case 1/2에도 동일 저장 조건. + +### My_Homenet.c (PC 대시보드) +- **[Low/설계확인] My_Homenet.c:366 — CTRL_VSP u16→u8 truncation** ✓ + - `(uint8_t)(((uint16_t)pl[2]<<8)|pl[3])` 는 상위바이트를 시프트 후 캐스팅으로 버려 사실상 `pl[3]`(하위)만 사용. VSP가 0~255라 실사용은 무해하나, 의도 명확화를 위해 `pl[3]`만 쓰는 게 안전. (확정 손상 아님) +- **[Low/의심] My_Homenet.c:410 — `hn_apply_cmd(cmd, pl, HN_DATA_LEN)` 로 len 항상 240** (분석) + - 모든 `if(len >= N)` 검증이 무조건 통과 → 짧은 명령 의미검증이 사실상 무력. 고정 244B 구조라 오버런은 없음. 동작 영향 낮음. + +### My_Hood.c (후드) +- **[Med] My_Hood.c:64 — 헤더 불일치 바이트를 버퍼에 기록** (분석) + - case 1에서 0x11 불일치 시 `Rx_hood_Pos=0` 후에도 `Rx_Hood_Buff[Pos++]=data` 실행 → 잘못된 바이트가 buffer[0]에 들어가 프레임 한 칸 밀림. 제안: 불일치 시 `Pos=0; break;` 로 즉시 반환. + +--- + +## 2. 시스템 / 전원 / 예약 + +### main.c +- **[Low] main.c:116-119 — `Process_10ms` 재장전값 3000, 본문 비어있음(데드/오타)** ✓ + - `Process_5ms`/`Process_10ms` 블록 모두 카운터만 재장전하고 작업 없음(no-op). 동작 영향은 없으나 `=3000`은 명백한 leftover. 제안: 블록 제거 또는 의도값 복원. + +### My_system.c +- **[Med] My_system.c (예약 카운터 이원화) — `Reserve_Remain_Sec`(HomeNet) vs `Reserve_timer_sec`(룸컨)** ✓ + - main.c 1초 루프는 `Reserve_Remain_Sec`만 감산. 룸컨용 `Reserve_timer_sec`를 감산하는 `Reservation_process()`는 **My_RJ2.c:110에서 주석처리** → 룸컨이 설정한 예약은 카운트다운/전원OFF가 안 됨. 제안: 카운터 단일화 또는 `Reservation_process()` 호출 복원. +- **[Med] My_system.c:728 부근 `sensor_level()` — `T[i] - db` unsigned 언더플로** (분석) + - `uint16_t` 임계-데드밴드. 대시보드로 임계를 작게 설정하면 래핑되어 단계판정 폭주. 정상 사양값에선 미발생. 제안: 뺄셈 전 `T>=db` 가드 또는 signed 후 0 클램프. +- **[Med] My_system.c (Air_Quality_color_process 선두 `return(0)`) — 본문 도달불가(데드코드)** (분석) + - 매초 호출되나 색상/quality 계산 전체가 실행 안 됨. 의도된 비활성화인지 확인 필요(색상은 Air_Quality_damper_process가 별도 세팅). + +--- + +## 3. 모터 / 댐퍼 / PWM (MyMotor.c) + +- **[Med] MyMotor.c:893·897 — 팬 PWM 보정항 정수 오버플로/truncation** (분석) + - `BLDC_SPEED_TABLE[..]*Volum_value/1000` 이 int로 먼저 계산 → 큰 값/음수 Volum에서 오버플로·정밀손실. 제안: float 우선 캐스팅 또는 Volum 범위 클램프. +- **[Med] MyMotor.c — `BLDC_SPEED_TABLE[Fan_Speed]`(크기100), `Target_Step_Count[damper_num]`(크기7) 인덱스 미검증** (분석) + - 정상 VSP/모드값에선 안전하나 방어 없음. Fan_Speed≥100 또는 damper_num≥7 시 OOB. 제안: 접근 전 클램프/가드. +- **[Med][의심] MyMotor.c:1011 외 — `Step_Status != 0x3F` 수렴 대기 무한블록 가능** + - 특정 타이밍에 6댐퍼 전부 0x3F 미도달 시 후속(팬 목표갱신) 진입 불가. 타임아웃/완료플래그 보강 검토. +- **[Low][의심] MyMotor.c:962-979 — `Vsp_Select` if-else 체인 공백구간** + - 10~15, 0x21~0x24 등 미정의 값은 어느 분기에도 안 걸려 Target/Damper 미설정. 정상 범위면 무해. default 처리 검토. + +--- + +## 4. 제어 / EEPROM (MyControl.c) + +- **[High] MyControl.c:595 — 필터리셋 조건 `Filter_timer_change` 중복(오타)** (분석) + - `if((Filter_timer_clean==0)&&(Filter_timer_change==0)&&(Filter_timer_change==0))` 세 번째는 `Soja_timer_change==0` 이어야 함 → 소자 청소/교체 카운터 리셋 누락. 제안: 세 번째를 `Soja_timer_change`로 교정. +- **[Med] MyControl.c:659 — `Pre_Mode_Control` 부분쓰기 루프 상한이 127** (분석) + - 정전복귀 3바이트(40~42)만 필요한데 `i>8` 배치로 상쇄 → 와이어는 표준 리틀엔디안. 정상. (시뮬레이터는 lo-first로 일치시킴) +- **CTRL_RESERVE 곱셈(My_Homenet.c:385)**: `pl[0]*3600` int 승격으로 최대 28800 정상. +- **EEPROM 인덱스/페이지 경계(MyControl.c)**: 히스테리시스/임계 영역 최댓값 127(=EEP_SIZE-1), 페이지(128B) 침범 없음. 서명 0x55AA55AA + 별도 유효성 마커 검증 정상. +- **pwm_duty10000.c**: 룩업테이블이 아니라 표준 Nuvoton PWM 드라이버. 범위초과 없음. + +--- + +## 참고 +- 본 리포트는 분석만 수행했고 소스는 수정하지 않았습니다. +- (분석) 표기 항목은 영역별 분석에서 도출됐고 작성자 재확인 전입니다. 수정 착수 전 해당 라인을 함께 열어 확정하는 것을 권장합니다. +- 우선순위 1~4(High)는 동작 증상으로 이어질 가능성이 가장 높습니다. diff --git a/program/.gitignore b/program/.gitignore new file mode 100644 index 0000000..b428225 --- /dev/null +++ b/program/.gitignore @@ -0,0 +1,40 @@ +# ============================================================================= +# HERV .gitignore +# ============================================================================= + +# VS Code/Make 빌드 산출물 +build/ + +# Eclipse(Nueclipse) 빌드 산출물 +Release/*.elf +Release/*.hex +Release/*.bin +Release/*.map +Release/*.siz +Release/**/*.o +Release/**/*.d + +# OS +.DS_Store +Thumbs.db +desktop.ini + +# 에디터 백업 +*.bak +*.swp +*~ +.#* + +# VS Code 사용자별 로컬 설정 (공유 설정은 .vscode/ 에 그대로 둠) +.vscode/*.local.json +.vscode/ipch/ + +# Eclipse 사용자별 (선택 - 팀 공유 시 주석 해제) +# .metadata/ +# .settings/ + +# 로그 +*.log + +# Claude Code 로컬 설정 +.claude/ diff --git a/program/.vscode/c_cpp_properties.json b/program/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..3bc9054 --- /dev/null +++ b/program/.vscode/c_cpp_properties.json @@ -0,0 +1,30 @@ +{ + "configurations": [ + { + "name": "Nano100B", + "compilerPath": "C:/Program Files (x86)/GNU Arm Embedded Toolchain/10 2021.10/bin/arm-none-eabi-gcc.exe", + "compilerArgs": [ + "-mcpu=cortex-m0", + "-mthumb" + ], + "intelliSenseMode": "gcc-arm", + "includePath": [ + "${workspaceFolder}/User", + "${workspaceFolder}/Library/CMSIS/Include", + "${workspaceFolder}/Library/Device/Nuvoton/Nano100Series/Include", + "${workspaceFolder}/Library/StdDriver/inc" + ], + "defines": [], + "cStandard": "gnu11", + "cppStandard": "gnu++14", + "browse": { + "path": [ + "${workspaceFolder}/User", + "${workspaceFolder}/Library" + ], + "limitSymbolsToIncludedHeaders": true + } + } + ], + "version": 4 +} diff --git a/program/.vscode/launch.json b/program/.vscode/launch.json new file mode 100644 index 0000000..c4c1eb0 --- /dev/null +++ b/program/.vscode/launch.json @@ -0,0 +1,34 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Debug HERV (Nu-Link)", + "type": "cortex-debug", + "request": "launch", + "servertype": "openocd", + "cwd": "${workspaceFolder}", + "executable": "${workspaceFolder}/build/HERV.elf", + "device": "NANO100SE3BN", + "configFiles": [ + "openocd.cfg" + ], + "runToEntryPoint": "main", + "preLaunchTask": "build", + "showDevDebugOutput": "none" + // SVD 파일 있으면 아래 주석 풀고 경로 지정 (디버그시 레지스터 이름으로 표시) + // "svdFile": "${workspaceFolder}/Nano100B.svd" + }, + { + "name": "Attach to HERV (Nu-Link)", + "type": "cortex-debug", + "request": "attach", + "servertype": "openocd", + "cwd": "${workspaceFolder}", + "executable": "${workspaceFolder}/build/HERV.elf", + "device": "NANO100SE3BN", + "configFiles": [ + "openocd.cfg" + ] + } + ] +} diff --git a/program/.vscode/settings.json b/program/.vscode/settings.json new file mode 100644 index 0000000..beeb296 --- /dev/null +++ b/program/.vscode/settings.json @@ -0,0 +1,34 @@ +{ + "files.associations": { + "*.h": "c", + "*.c": "c", + "Nano100Series.h": "c", + "system_Nano100Series.h": "c" + }, + "C_Cpp.default.intelliSenseMode": "gcc-arm", + "C_Cpp.errorSquiggles": "enabled", + "[c]": { + "editor.tabSize": 4, + "editor.insertSpaces": true, + "editor.detectIndentation": false + }, + "[makefile]": { + "editor.insertSpaces": false, + "editor.tabSize": 8 + }, + "files.encoding": "utf8", + "files.eol": "\r\n", + "search.exclude": { + "**/build": true, + "**/Release": true + }, + "files.exclude": { + "**/.cproject": false, + "**/.project": false, + "**/.settings": true + }, + "terminal.integrated.defaultProfile.windows": "PowerShell", + "terminal.integrated.env.windows": { + "CLAUDE_CODE_USE_POWERSHELL_TOOL": "1" + } +} diff --git a/program/.vscode/tasks.json b/program/.vscode/tasks.json new file mode 100644 index 0000000..6281ab9 --- /dev/null +++ b/program/.vscode/tasks.json @@ -0,0 +1,60 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "shell", + "command": "make", + "args": ["-j8"], + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": ["$gcc"], + "presentation": { + "echo": true, + "reveal": "always", + "panel": "shared", + "clear": true + } + }, + { + "label": "rebuild", + "type": "shell", + "command": "make", + "args": ["rebuild", "-j8"], + "problemMatcher": ["$gcc"], + "presentation": { + "clear": true + } + }, + { + "label": "clean", + "type": "shell", + "command": "make", + "args": ["clean"] + }, + { + "label": "flash", + "type": "shell", + "command": "make", + "args": ["flash"], + "dependsOn": "build", + "problemMatcher": [] + }, + { + "label": "erase", + "type": "shell", + "command": "make", + "args": ["erase"], + "problemMatcher": [] + }, + { + "label": "size", + "type": "shell", + "command": "make", + "args": ["size"], + "problemMatcher": [] + } + ] +} diff --git a/program/Library/CMSIS/Include/arm_common_tables.h b/program/Library/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000..d42f8ed --- /dev/null +++ b/program/Library/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 16/06/16 3:46p $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/program/Library/CMSIS/Include/arm_const_structs.h b/program/Library/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000..4be1a88 --- /dev/null +++ b/program/Library/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 16/06/16 3:46p $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/program/Library/CMSIS/Include/arm_math.h b/program/Library/CMSIS/Include/arm_math.h new file mode 100644 index 0000000..0058f0d --- /dev/null +++ b/program/Library/CMSIS/Include/arm_math.h @@ -0,0 +1,7153 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 16/06/16 3:46p $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/program/Library/CMSIS/Include/cmsis_armcc.h b/program/Library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..74c49c6 --- /dev/null +++ b/program/Library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/program/Library/CMSIS/Include/cmsis_armcc_V6.h b/program/Library/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000..cd13240 --- /dev/null +++ b/program/Library/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/program/Library/CMSIS/Include/cmsis_gcc.h b/program/Library/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..bb89fbb --- /dev/null +++ b/program/Library/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/program/Library/CMSIS/Include/core_cm0.h b/program/Library/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..711dad5 --- /dev/null +++ b/program/Library/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/CMSIS/Include/core_cm0plus.h b/program/Library/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..b04aa39 --- /dev/null +++ b/program/Library/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/CMSIS/Include/core_cm3.h b/program/Library/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..b4ac4c7 --- /dev/null +++ b/program/Library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/CMSIS/Include/core_cm4.h b/program/Library/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..dc840eb --- /dev/null +++ b/program/Library/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/CMSIS/Include/core_cm4_simd.h b/program/Library/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 0000000..3bc7906 --- /dev/null +++ b/program/Library/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,649 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/program/Library/CMSIS/Include/core_cm7.h b/program/Library/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..3b7530a --- /dev/null +++ b/program/Library/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/CMSIS/Include/core_cmFunc.h b/program/Library/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..652a48a --- /dev/null +++ b/program/Library/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/program/Library/CMSIS/Include/core_cmInstr.h b/program/Library/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..f474b0e --- /dev/null +++ b/program/Library/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/program/Library/CMSIS/Include/core_cmSimd.h b/program/Library/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000..66bf5c2 --- /dev/null +++ b/program/Library/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/program/Library/CMSIS/Include/core_sc000.h b/program/Library/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..514dbd8 --- /dev/null +++ b/program/Library/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/CMSIS/Include/core_sc300.h b/program/Library/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..8bd18aa --- /dev/null +++ b/program/Library/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/_syscalls.c b/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/_syscalls.c new file mode 100644 index 0000000..a5f6166 --- /dev/null +++ b/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/_syscalls.c @@ -0,0 +1,1168 @@ +// +// This file is part of the uOS++ III distribution +// Parts of this file are from the newlib sources, issued under GPL. +// Copyright (c) 2014 Liviu Ionescu +// + +// ---------------------------------------------------------------------------- + +int errno; +void *__dso_handle __attribute__ ((weak)); + +// ---------------------------------------------------------------------------- + +#if !defined(OS_USE_SEMIHOSTING) + +#include <_ansi.h> +#include <_syslist.h> +#include +//#include +#include +#include +#include +#include +#include + +void +__initialize_args(int* p_argc, char*** p_argv); + +// This is the standard default implementation for the routine to +// process args. It returns a single empty arg. +// For semihosting applications, this is redefined to get the real +// args from the debugger. You can also use it if you decide to keep +// some args in a non-volatile memory. + +void __attribute__((weak)) +__initialize_args(int* p_argc, char*** p_argv) +{ + // By the time we reach this, the data and bss should have been initialised. + + // The strings pointed to by the argv array shall be modifiable by the + // program, and retain their last-stored values between program startup + // and program termination. (static, no const) + static char name[] = ""; + + // The string pointed to by argv[0] represents the program name; + // argv[0][0] shall be the null character if the program name is not + // available from the host environment. argv[argc] shall be a null pointer. + // (static, no const) + static char* argv[2] = + { name, NULL }; + + *p_argc = 1; + *p_argv = &argv[0]; + return; +} + +// These functions are defined here to avoid linker errors in freestanding +// applications. They might be called in some error cases from library +// code. +// +// If you detect other functions to be needed, just let us know +// and we'll add them. + +int +raise(int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int +kill(pid_t pid, int sig); + +int +kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +#endif // !defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +// If you need the empty definitions, remove the -ffreestanding option. + +#if __STDC_HOSTED__ == 1 + +char* __env[1] = +{ 0 }; +char** environ = __env; + +#if !defined(OS_USE_SEMIHOSTING) + +// Forward declarations + +int +_chown(const char* path, uid_t owner, gid_t group); + +int +_close(int fildes); + +int +_execve(char* name, char** argv, char** env); + +int +_fork(void); + +int +_fstat(int fildes, struct stat* st); + +int +_getpid(void); + +int +_gettimeofday(struct timeval* ptimeval, void* ptimezone); + +int +_isatty(int file); + +int +_kill(int pid, int sig); + +int +_link(char* existing, char* _new); + +int +_lseek(int file, int ptr, int dir); + +int +_open(char* file, int flags, int mode); + +int +_read(int file, char* ptr, int len); + +int +_readlink(const char* path, char* buf, size_t bufsize); + +int +_stat(const char* file, struct stat* st); + +int +_symlink(const char* path1, const char* path2); + +clock_t +_times(struct tms* buf); + +int +_unlink(char* name); + +int +_wait(int* status); + +int +_write(int file, char* ptr, int len); + +// Definitions + +int __attribute__((weak)) +_chown(const char* path __attribute__((unused)), + uid_t owner __attribute__((unused)), gid_t group __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_close(int fildes __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)), + char** env __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fork(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fstat(int fildes __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_getpid(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_gettimeofday(struct timeval* ptimeval __attribute__((unused)), + void* ptimezone __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_isatty(int file __attribute__((unused))) +{ + errno = ENOSYS; + return 0; +} + +int __attribute__((weak)) +_kill(int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_link(char* existing __attribute__((unused)), + char* _new __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)), + int dir __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_open(char* file __attribute__((unused)), int flags __attribute__((unused)), + int mode __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_read(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_readlink(const char* path __attribute__((unused)), + char* buf __attribute__((unused)), size_t bufsize __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_stat(const char* file __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_symlink(const char* path1 __attribute__((unused)), + const char* path2 __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +clock_t __attribute__((weak)) +_times(struct tms* buf __attribute__((unused))) +{ + errno = ENOSYS; + return ((clock_t) -1); +} + +int __attribute__((weak)) +_unlink(char* name __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_wait(int* status __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_write(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +#else // defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "semihosting.h" + +int _kill (int pid, int sig); + +void __attribute__((noreturn)) _exit (int status); + +// Forward declarations. +int _system (const char*); +int _rename (const char*, const char*); +int _isatty (int); +clock_t _times (struct tms*); +int _gettimeofday (struct timeval *, void*); +int _unlink (const char*); +int _link (void); + +int _stat (const char*, struct stat*); + +int _fstat (int, struct stat*); +int _swistat (int fd, struct stat* st); +int _getpid (int); +int _close (int); +clock_t _clock (void); +int _swiclose (int); +int _open (const char*, int, ...); +int _swiopen (const char*, int); +int _write (int, char*, int); +int _swiwrite (int, char*, int); +int _lseek (int, int, int); +int _swilseek (int, int, int); +int _read (int, char*, int); +int _swiread (int, char*, int); + +void initialise_monitor_handles (void); + +void __initialize_args (int* p_argc, char*** p_argv); + +static int +checkerror (int); +static int +error (int); +static int +get_errno (void); + +// ---------------------------------------------------------------------------- + +#define ARGS_BUF_ARRAY_SIZE 80 +#define ARGV_BUF_ARRAY_SIZE 10 + +typedef struct +{ + char* pCommandLine; + int size; +} CommandLineBlock; + +void __initialize_args (int* p_argc, char*** p_argv) +{ + // Array of chars to receive the command line from the host + static char args_buf[ARGS_BUF_ARRAY_SIZE]; + + // Array of pointers to store the final argv pointers (pointing + // in the above array). + static char* argv_buf[ARGV_BUF_ARRAY_SIZE]; + + int argc = 0; + int isInArgument = 0; + + CommandLineBlock cmdBlock; + cmdBlock.pCommandLine = args_buf; + cmdBlock.size = sizeof(args_buf) - 1; + + int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock); + if (ret == 0) + { + + // In case the host send more than we can chew, limit the + // string to our buffer. + args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0'; + + // The command line is a null terminated string + char* p = cmdBlock.pCommandLine; + + int delim = '\0'; + int ch; + + while ((ch = *p) != '\0') + { + if (isInArgument == 0) + { + if (!isblank(ch)) + { + if (argc >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1)) + break; + + if (ch == '"' || ch == '\'') + { + // Remember the delimiter to search for the + // corresponding terminator + delim = ch; + ++p; // skip the delimiter + ch = *p; + } + // Remember the arg beginning address + argv_buf[argc++] = p; + isInArgument = 1; + } + } + else if (delim != '\0') + { + if ((ch == delim)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + } + else if (isblank(ch)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + ++p; + } + } + + if (argc == 0) + { + // No args found in string, return a single empty name. + args_buf[0] = '\0'; + argv_buf[0] = &args_buf[0]; + ++argc; + } + + // Must end the array with a null pointer. + argv_buf[argc] = NULL; + + *p_argc = argc; + *p_argv = &argv_buf[0]; + + // temporary here + initialise_monitor_handles (); + + return; +} + +// ---------------------------------------------------------------------------- + +void _exit (int status) +{ + /* There is only one SWI for both _exit and _kill. For _exit, call + the SWI with the second argument set to -1, an invalid value for + signum, so that the SWI handler can distinguish the two calls. + Note: The RDI implementation of _kill throws away both its + arguments. */ + report_exception (status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError); +} + +// ---------------------------------------------------------------------------- + +int __attribute__((weak)) +_kill (int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +/* Struct used to keep track of the file position, just so we + can implement fseek(fh,x,SEEK_CUR). */ +struct fdent +{ + int handle; + int pos; +}; + +#define MAX_OPEN_FILES 20 + +/* User file descriptors (fd) are integer indexes into + the openfiles[] array. Error checking is done by using + findslot(). + + This openfiles array is manipulated directly by only + these 5 functions: + + findslot() - Translate entry. + newslot() - Find empty entry. + initilise_monitor_handles() - Initialize entries. + _swiopen() - Initialize entry. + _close() - Handle stdout == stderr case. + + Every other function must use findslot(). */ + +static struct fdent openfiles[MAX_OPEN_FILES]; + +static struct fdent* findslot (int); +static int newslot (void); + +/* Register name faking - works in collusion with the linker. */ +register char* stack_ptr asm ("sp"); + +/* following is copied from libc/stdio/local.h to check std streams */ +extern void __sinit(struct _reent*); +#define CHECK_INIT(ptr) \ + do \ + { \ + if ((ptr) && !(ptr)->__sdidinit) \ + __sinit (ptr); \ + } \ + while (0) + +static int monitor_stdin; +static int monitor_stdout; +static int monitor_stderr; + +/* Return a pointer to the structure associated with + the user file descriptor fd. */ +static struct fdent* +findslot (int fd) +{ + CHECK_INIT(_REENT); + + /* User file descriptor is out of range. */ + if ((unsigned int) fd >= MAX_OPEN_FILES) + { + return NULL; + } + + /* User file descriptor is open? */ + if (openfiles[fd].handle == -1) + { + return NULL; + } + + /* Valid. */ + return &openfiles[fd]; +} + +/* Return the next lowest numbered free file + structure, or -1 if we can't find one. */ +static int +newslot (void) +{ + int i; + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + if (openfiles[i].handle == -1) + { + break; + } + } + + if (i == MAX_OPEN_FILES) + { + return -1; + } + + return i; +} + +void +initialise_monitor_handles (void) +{ + int i; + + /* Open the standard file descriptors by opening the special + * teletype device, ":tt", read-only to obtain a descriptor for + * standard input and write-only to obtain a descriptor for standard + * output. Finally, open ":tt" in append mode to obtain a descriptor + * for standard error. Since this is a write mode, most kernels will + * probably return the same value as for standard output, but the + * kernel can differentiate the two using the mode flag and return a + * different descriptor for standard error. + */ + + int volatile block[3]; + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 0; /* mode "r" */ + monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 4; /* mode "w" */ + monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 8; /* mode "a" */ + monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + /* If we failed to open stderr, redirect to stdout. */ + if (monitor_stderr == -1) + { + monitor_stderr = monitor_stdout; + } + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + openfiles[i].handle = -1; + } + + openfiles[0].handle = monitor_stdin; + openfiles[0].pos = 0; + openfiles[1].handle = monitor_stdout; + openfiles[1].pos = 0; + openfiles[2].handle = monitor_stderr; + openfiles[2].pos = 0; +} + +static int +get_errno (void) +{ + return call_host (SEMIHOSTING_SYS_ERRNO, NULL); +} + +/* Set errno and return result. */ +static int +error (int result) +{ + errno = get_errno (); + return result; +} + +/* Check the return and set errno appropriately. */ +static int +checkerror (int result) +{ + if (result == -1) + { + return error (-1); + } + + return result; +} + +/* fh, is a valid internal file handle. + ptr, is a null terminated string. + len, is the length in bytes to read. + Returns the number of bytes *not* written. */ +int +_swiread (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_READ, block)); +} + +/* fd, is a valid user file handle. + Translates the return of _swiread into + bytes read. */ +int +_read (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiread (pfd->handle, ptr, len); + + if (res == -1) + { + return res; + } + + pfd->pos += len - res; + + /* res == len is not an error, + at least if we want feof() to work. */ + return len - res; +} + +/* fd, is a user file descriptor. */ +int _swilseek (int fd, int ptr, int dir) +{ + int res; + struct fdent *pfd; + + /* Valid file descriptor? */ + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Valid whence? */ + if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END)) + { + errno = EINVAL; + return -1; + } + + /* Convert SEEK_CUR to SEEK_SET */ + if (dir == SEEK_CUR) + { + ptr = pfd->pos + ptr; + /* The resulting file offset would be negative. */ + if (ptr < 0) + { + errno = EINVAL; + if ((pfd->pos > 0) && (ptr > 0)) + { + errno = EOVERFLOW; + } + return -1; + } + dir = SEEK_SET; + } + + int block[2]; + if (dir == SEEK_END) + { + block[0] = pfd->handle; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block)); + if (res == -1) + { + return -1; + } + ptr += res; + } + + /* This code only does absolute seeks. */ + block[0] = pfd->handle; + block[1] = ptr; + res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block)); + + /* At this point ptr is the current file position. */ + if (res >= 0) + { + pfd->pos = ptr; + return ptr; + } + else + { + return -1; + } +} + +int _lseek (int fd, int ptr, int dir) +{ + return _swilseek (fd, ptr, dir); +} + +/* fh, is a valid internal file handle. + Returns the number of bytes *not* written. */ +int _swiwrite (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block)); +} + +/* fd, is a user file descriptor. */ +int _write (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiwrite (pfd->handle, ptr, len); + + /* Clearly an error. */ + if (res < 0) + { + return -1; + } + + pfd->pos += len - res; + + /* We wrote 0 bytes? + Retrieve errno just in case. */ + if ((len - res) == 0) + { + return error (0); + } + + return (len - res); +} + +int _swiopen (const char* path, int flags) +{ + int aflags = 0, fh; + uint32_t block[3]; + + int fd = newslot (); + + if (fd == -1) + { + errno = EMFILE; + return -1; + } + + /* It is an error to open a file that already exists. */ + if ((flags & O_CREAT) && (flags & O_EXCL)) + { + struct stat st; + int res; + res = _stat (path, &st); + if (res != -1) + { + errno = EEXIST; + return -1; + } + } + + /* The flags are Unix-style, so we need to convert them. */ +#ifdef O_BINARY + if (flags & O_BINARY) + { + aflags |= 1; + } +#endif + + /* In O_RDONLY we expect aflags == 0. */ + + if (flags & O_RDWR) + { + aflags |= 2; + } + + if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY)) + { + aflags |= 4; + } + + if (flags & O_APPEND) + { + /* Can't ask for w AND a; means just 'a'. */ + aflags &= ~4; + aflags |= 8; + } + + block[0] = (uint32_t) path; + block[2] = strlen (path); + block[1] = (uint32_t) aflags; + + fh = call_host (SEMIHOSTING_SYS_OPEN, block); + + /* Return a user file descriptor or an error. */ + if (fh >= 0) + { + openfiles[fd].handle = fh; + openfiles[fd].pos = 0; + return fd; + } + else + { + return error (fh); + } +} + +int _open (const char* path, int flags, ...) +{ + return _swiopen (path, flags); +} + +/* fh, is a valid internal file handle. */ +int _swiclose (int fh) +{ + return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh)); +} + +/* fd, is a user file descriptor. */ +int _close (int fd) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Handle stderr == stdout. */ + if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle)) + { + pfd->handle = -1; + return 0; + } + + /* Attempt to close the handle. */ + res = _swiclose (pfd->handle); + + /* Reclaim handle? */ + if (res == 0) + { + pfd->handle = -1; + } + + return res; +} + +int __attribute__((weak)) +_getpid (int n __attribute__ ((unused))) +{ + return 1; +} + +int +_swistat (int fd, struct stat* st) +{ + struct fdent *pfd; + int res; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Always assume a character device, + with 1024 byte blocks. */ + st->st_mode |= S_IFCHR; + st->st_blksize = 1024; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle)); + if (res == -1) + { + return -1; + } + + /* Return the file size. */ + st->st_size = res; + return 0; +} + +int __attribute__((weak)) +_fstat (int fd, struct stat* st) +{ + memset (st, 0, sizeof(*st)); + return _swistat (fd, st); +} + +int __attribute__((weak)) +_stat (const char*fname, struct stat *st) +{ + int fd, res; + memset (st, 0, sizeof(*st)); + /* The best we can do is try to open the file readonly. + If it exists, then we can guess a few things about it. */ + if ((fd = _open (fname, O_RDONLY)) == -1) + { + return -1; + } + st->st_mode |= S_IFREG | S_IREAD; + res = _swistat (fd, st); + /* Not interested in the error. */ + _close (fd); + return res; +} + +int __attribute__((weak)) +_link (void) +{ + errno = ENOSYS; + return -1; +} + +int _unlink (const char* path) +{ + int res; + uint32_t block[2]; + block[0] = (uint32_t) path; + block[1] = strlen (path); + res = call_host (SEMIHOSTING_SYS_REMOVE, block); + + if (res == -1) + { + return error (res); + } + return 0; +} + +int _gettimeofday (struct timeval* tp, void* tzvp) +{ + struct timezone* tzp = tzvp; + if (tp) + { + /* Ask the host for the seconds since the Unix epoch. */ + tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL); + tp->tv_usec = 0; + } + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t _clock (void) +{ + clock_t timeval; + + timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL); + return timeval; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t +_times (struct tms* tp) +{ + clock_t timeval = _clock (); + + if (tp) + { + tp->tms_utime = timeval; /* user time */ + tp->tms_stime = 0; /* system time */ + tp->tms_cutime = 0; /* user time, children */ + tp->tms_cstime = 0; /* system time, children */ + } + + return timeval; +} + +int _isatty (int fd) +{ + struct fdent *pfd; + int tty; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return 0; + } + + tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle); + + if (tty == 1) + { + return 1; + } + + errno = get_errno (); + return 0; +} + +int _system (const char* s) +{ + uint32_t block[2]; + int e; + + /* Hmmm. The ARM debug interface specification doesn't say whether + SYS_SYSTEM does the right thing with a null argument, or assign any + meaning to its return value. Try to do something reasonable.... */ + if (!s) + { + return 1; /* maybe there is a shell available? we can hope. :-P */ + } + block[0] = (uint32_t) s; + block[1] = strlen (s); + e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block)); + if ((e >= 0) && (e < 256)) + { + /* We have to convert e, an exit status to the encoded status of + the command. To avoid hard coding the exit status, we simply + loop until we find the right position. */ + int exit_code; + + for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1) + { + continue; + } + } + return e; +} + +int _rename (const char* oldpath, const char* newpath) +{ + uint32_t block[4]; + block[0] = (uint32_t) oldpath; + block[1] = strlen (oldpath); + block[2] = (uint32_t) newpath; + block[3] = strlen (newpath); + return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0; +} + +// ---------------------------------------------------------------------------- +// Required by Google Tests + +int mkdir (const char *path __attribute__((unused)), mode_t mode __attribute__((unused))) +{ +#if 0 + // always return true + return 0; +#else + errno = ENOSYS; + return -1; +#endif +} + +char *getcwd (char *buf, size_t size) +{ + // no cwd available via semihosting, so we use the temporary folder + strncpy (buf, "/tmp", size); + return buf; +} + +#endif // defined OS_USE_SEMIHOSTING + +#endif // __STDC_HOSTED__ == 1 diff --git a/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/gcc_arm.ld b/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/gcc_arm.ld new file mode 100644 index 0000000..973edc8 --- /dev/null +++ b/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/gcc_arm.ld @@ -0,0 +1,195 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000 /* 512k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/semihosting.h b/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/semihosting.h new file mode 100644 index 0000000..3370854 --- /dev/null +++ b/program/Library/Device/Nuvoton/Nano100Series/Source/GCC/semihosting.h @@ -0,0 +1,116 @@ + +#ifndef ARM_SEMIHOSTING_H_ +#define ARM_SEMIHOSTING_H_ + +// ---------------------------------------------------------------------------- + +// Semihosting operations. +enum OperationNumber +{ + // Regular operations + SEMIHOSTING_EnterSVC = 0x17, + SEMIHOSTING_ReportException = 0x18, + SEMIHOSTING_SYS_CLOSE = 0x02, + SEMIHOSTING_SYS_CLOCK = 0x10, + SEMIHOSTING_SYS_ELAPSED = 0x30, + SEMIHOSTING_SYS_ERRNO = 0x13, + SEMIHOSTING_SYS_FLEN = 0x0C, + SEMIHOSTING_SYS_GET_CMDLINE = 0x15, + SEMIHOSTING_SYS_HEAPINFO = 0x16, + SEMIHOSTING_SYS_ISERROR = 0x08, + SEMIHOSTING_SYS_ISTTY = 0x09, + SEMIHOSTING_SYS_OPEN = 0x01, + SEMIHOSTING_SYS_READ = 0x06, + SEMIHOSTING_SYS_READC = 0x07, + SEMIHOSTING_SYS_REMOVE = 0x0E, + SEMIHOSTING_SYS_RENAME = 0x0F, + SEMIHOSTING_SYS_SEEK = 0x0A, + SEMIHOSTING_SYS_SYSTEM = 0x12, + SEMIHOSTING_SYS_TICKFREQ = 0x31, + SEMIHOSTING_SYS_TIME = 0x11, + SEMIHOSTING_SYS_TMPNAM = 0x0D, + SEMIHOSTING_SYS_WRITE = 0x05, + SEMIHOSTING_SYS_WRITEC = 0x03, + SEMIHOSTING_SYS_WRITE0 = 0x04, + + // Codes returned by SEMIHOSTING_ReportException + ADP_Stopped_ApplicationExit = ((2 << 16) + 38), + ADP_Stopped_RunTimeError = ((2 << 16) + 35), + +}; + +// ---------------------------------------------------------------------------- + +// SWI numbers and reason codes for RDI (Angel) monitors. +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +// For thumb only architectures use the BKPT instruction instead of SWI. +#if defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) \ + || defined(__ARM_ARCH_6M__) +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) +// Testing the local semihosting handler cannot use another BKPT, since this +// configuration cannot trigger HaedFault exceptions while the debugger is +// connected, so we use an illegal op code, that will trigger an +// UsageFault exception. +#define AngelSWITestFault "setend be" +#define AngelSWITestFaultOpCode (0xB658) +#endif + +static inline int +__attribute__ ((always_inline)) +call_host (int reason, void* arg) +{ + int value; + asm volatile ( + + " mov r0, %[rsn] \n" + " mov r1, %[arg] \n" +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + " " AngelSWITestFault " \n" +#else + " " AngelSWIInsn " %[swi] \n" +#endif + " mov %[val], r0" + + : [val] "=r" (value) /* Outputs */ + : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + // Clobbers r0 and r1, and lr if in supervisor mode + ); + + // Accordingly to page 13-77 of ARM DUI 0040D other registers + // can also be clobbered. Some memory positions may also be + // changed by a system call, so they should not be kept in + // registers. Note: we are assuming the manual is right and + // Angel is respecting the APCS. + return value; +} + +// ---------------------------------------------------------------------------- + +// Function used in _exit() to return the status code as Angel exception. +static inline void +__attribute__ ((always_inline,noreturn)) +report_exception (int reason) +{ + call_host (SEMIHOSTING_ReportException, (void*) reason); + + for (;;) + ; +} + +// ---------------------------------------------------------------------------- + +#endif // ARM_SEMIHOSTING_H_ diff --git a/program/Library/StdDriver/inc/EEPROM_Emulate.h b/program/Library/StdDriver/inc/EEPROM_Emulate.h new file mode 100644 index 0000000..af76d63 --- /dev/null +++ b/program/Library/StdDriver/inc/EEPROM_Emulate.h @@ -0,0 +1,120 @@ +/**************************************************************************//** + * @file EEPROM_Emulate.h + * @brief Flash-based EEPROM emulation library for Nuvoton Nano100B series. + * + * @note + * NEW IMPLEMENTATION - reverse-engineered from caller-side API only. + * NOT BINARY COMPATIBLE with the original (factory) EEPROM_Emulate library. + * If a board already has data written by the original library, this version + * will treat that data as invalid and reset all settings to default (0xFF). + * + * Public API kept identical to the original so the application code compiles + * without changes: + * - Init_EEPROM(data_size, page_amount) + * - Search_Valid_Page() + * - Read_Data(index, *data) -> 0=OK, non-zero=error + * - Write_Data(index, value) -> 0=OK, non-zero=error + * + * Implementation summary: + * - Uses the last 1KB of APROM (2 flash pages, 512 bytes each). + * - Append-only entry log inside each page (wear-leveled). + * - Each entry is one 32-bit word: [TAG][index][~index][value]. + * - When active page is full, contents are compacted into the other page. + * - RAM mirror of the data array for fast Read_Data(). + * + ******************************************************************************/ +#ifndef __EEPROM_EMULATE_H__ +#define __EEPROM_EMULATE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------------------*/ +/* Configuration */ +/*--------------------------------------------------------------------------*/ + +/* Maximum number of bytes the EEPROM can hold. + * Must be >= the largest index your application uses (EEP_SIZE in My_define.h). + * Current application uses EEP_SIZE = 69, so 128 leaves headroom. */ +#define EEP_DATA_SIZE 128u + +/* Number of flash pages used for the emulation (must be >= 2). */ +#define EEP_PAGE_COUNT 2u + +/* Flash page size on Nano100B series (do not change). */ +#define EEP_FLASH_PAGE_SIZE 0x200u /* 512 bytes */ + +/* Base address of the EEPROM region inside APROM. + * Default: last 1 KB of a 64 KB APROM (NANO100SE3BN has 64 KB). + * + * IMPORTANT - Linker script must guarantee that application code never + * occupies this region. With the default linker script provided by Nuvoton + * BSP this is fine as long as your firmware is < 63 KB. Verify with the + * map file after build. + * + * If your part has a different APROM size, change this: + * - 32 KB part : 0x7C00 + * - 64 KB part : 0xFC00 (default) + * - 128 KB part: 0x1FC00 + */ +#define EEP_FLASH_BASE 0xFC00u + +/*--------------------------------------------------------------------------*/ +/* Compatibility: variables expected by the application's main.c */ +/* Init_EEPROM(eep_data_size, eep_page_amount); */ +/*--------------------------------------------------------------------------*/ +extern const uint32_t eep_data_size; +extern const uint32_t eep_page_amount; + +/*--------------------------------------------------------------------------*/ +/* Public API */ +/*--------------------------------------------------------------------------*/ + +/** + * @brief Initialize the EEPROM emulation layer. + * @param data_size Logical size in bytes (clamped to EEP_DATA_SIZE). + * @param page_amount Number of physical pages to use (currently fixed = 2). + * + * Must be called once before any Read/Write/Search call. + * Enables FMC and unlocks protected registers. + */ +void Init_EEPROM(uint32_t data_size, uint32_t page_amount); + +/** + * @brief Locate the active flash page and load its contents into the RAM + * mirror. If no valid page is found, formats page 0 and starts fresh. + * + * Must be called once after Init_EEPROM(). After this call, Read_Data() + * returns the latest committed value for each index. + */ +void Search_Valid_Page(void); + +/** + * @brief Read one byte from the EEPROM mirror. + * @param index Index into the data array (0 .. EEP_DATA_SIZE-1). + * @param data Output pointer. Receives 0xFF if the byte was never written. + * @return 0 on success, non-zero on parameter error. + */ +uint32_t Read_Data(uint8_t index, uint8_t *data); + +/** + * @brief Write one byte to the EEPROM (RAM mirror + flash). + * @param index Index into the data array (0 .. EEP_DATA_SIZE-1). + * @param data Value to store. + * @return 0 on success, non-zero on parameter error. + * + * If the active flash page becomes full, contents are automatically + * compacted into the other page. + * + * If the value is unchanged, no flash write is performed (saves wear). + */ +uint32_t Write_Data(uint8_t index, uint8_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* __EEPROM_EMULATE_H__ */ diff --git a/program/Library/StdDriver/inc/adc.h b/program/Library/StdDriver/inc/adc.h new file mode 100644 index 0000000..75e7d0d --- /dev/null +++ b/program/Library/StdDriver/inc/adc.h @@ -0,0 +1,368 @@ +/**************************************************************************//** + * @file adc.h + * @version V1.00 + * $Revision: 10 $ + * $Date: 15/06/30 2:50p $ + * @brief NANO100 series ADC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup NANO100_ADC_EXPORTED_CONSTANTS ADC Exported Constants + @{ +*/ + +#define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask */ +#define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask */ +#define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask */ +#define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask */ +#define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask */ +#define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask */ +#define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask */ +#define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask */ +#define ADC_CH_8_MASK (1UL << 8) /*!< ADC channel 8 mask */ +#define ADC_CH_9_MASK (1UL << 9) /*!< ADC channel 9 mask */ +#define ADC_CH_10_MASK (1UL << 10) /*!< ADC channel 10 mask */ +#define ADC_CH_11_MASK (1UL << 11) /*!< ADC channel 11 mask */ +#define ADC_CH_12_MASK (1UL << 12) /*!< ADC channel 12 mask */ +#define ADC_CH_13_MASK (1UL << 13) /*!< ADC channel 13 mask */ +#define ADC_CH_14_MASK (1UL << 14) /*!< ADC channel 14 mask */ +#define ADC_CH_15_MASK (1UL << 15) /*!< ADC channel 15 mask */ +#define ADC_CH_16_MASK (1UL << 16) /*!< ADC channel 16 mask */ +#define ADC_CH_17_MASK (1UL << 17) /*!< ADC channel 17 mask */ +#define ADC_CHEN_Msk (0x3FFFF) /*!< ADC channel 0 ~ 17 mask */ +#define ADC_PDMADATA_AD_PDMA_Msk (0xFFF) /*!< ADC PDMA current transfer data */ +#define ADC_CMP_LESS_THAN (0UL) /*!< ADC compare condition less than */ +#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR_CMPCOND_Msk) /*!< ADC compare condition greater or equal to */ +#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC (P3.2) pin */ +#define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) /*!< External pin low level trigger ADC */ +#define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) /*!< External pin high level trigger ADC */ +#define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) /*!< External pin falling edge trigger ADC */ +#define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) /*!< External pin rising edge trigger ADC */ +#define ADC_ADF_INT (ADC_SR_ADF_Msk) /*!< ADC convert complete interrupt */ +#define ADC_CMP0_INT (ADC_SR_CMPF0_Msk) /*!< ADC comparator 0 interrupt */ +#define ADC_CMP1_INT (ADC_SR_CMPF1_Msk) /*!< ADC comparator 1 interrupt */ +#define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CR_DIFF_Pos) /*!< ADC input mode set to single end */ +#define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CR_DIFF_Pos) /*!< ADC input mode set to differential */ +#define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to single conversion */ +#define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to single cycle scan */ +#define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to continuous scan */ +#define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CR_DIFF_Pos) /*!< ADC differential mode output format with unsigned */ +#define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CR_DIFF_Pos) /*!< ADC differential mode output format with 2's complement */ +#define ADC_RESSEL_6_BIT (0UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 6 bit */ +#define ADC_RESSEL_8_BIT (1UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 8 bit */ +#define ADC_RESSEL_10_BIT (2UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 10 bit */ +#define ADC_RESSEL_12_BIT (3UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 12 bit */ +#define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to power */ +#define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to Int_VREF */ +#define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to VREF */ + +/*@}*/ /* end of group NANO100_ADC_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions + @{ +*/ + +/** + * @brief Get the latest ADC conversion data + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum Channel number + * @return Latest ADC conversion data + * \hideinitializer + */ +#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_RSLT_Msk) + +/** + * @brief Return the user-specified interrupt flags + * @param[in] adc Base address of ADC module + * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status. + * - \ref ADC_ADF_INT + * - \ref ADC_CMP0_INT + * - \ref ADC_CMP1_INT + * @return User specified interrupt flags + * \hideinitializer + */ +#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->SR & (u32Mask)) + +/** + * @brief This macro clear the selected interrupt status bits + * @param[in] adc Base address of ADC module + * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status. + * - \ref ADC_ADF_INT + * - \ref ADC_CMP0_INT + * - \ref ADC_CMP1_INT + * @return None + * \hideinitializer + */ +#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->SR = (ADC->SR & ~(ADC_SR_ADF_Msk | \ + ADC_SR_CMPF0_Msk | \ + ADC_SR_CMPF1_Msk)) | (u32Mask)) + +/** + * @brief Get the busy state of ADC + * @param[in] adc Base address of ADC module + * @return busy state of ADC + * @retval 0 ADC is not busy + * @retval 1 ADC is busy + * \hideinitializer + */ +#define ADC_IS_BUSY(adc) (ADC->SR & ADC_SR_BUSY_Msk ? 1 : 0) + +/** + * @brief Check if the ADC conversion data is over written or not + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum Currently not used + * @return Over run state of ADC data + * @retval 0 ADC data is not overrun + * @retval 1 ADC data us overrun + * \hideinitializer + */ +#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_OVERRUN_Msk ? 1 : 0) + +/** + * @brief Check if the ADC conversion data is valid or not + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum Currently not used + * @return Valid state of ADC data + * @retval 0 ADC data is not valid + * @retval 1 ADC data us valid + * \hideinitializer + */ +#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_VALID_Msk ? 1 : 0) + +/** + * @brief Power down ADC module + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_POWER_DOWN(adc) (ADC->CR &= ~ADC_CR_ADEN_Msk) + +/** + * @brief Power on ADC module + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_POWER_ON(adc) \ +do { \ + ADC->CR |= ADC_CR_ADEN_Msk; \ + while ((!(ADC->SR & ADC_SR_INITRDY_Msk)) || (!(ADC->PWRCTL & ADC_PWRCTL_PWUPRDY_Msk))); \ +} while(0) + +/** + * @brief Configure the comparator 0 and enable it + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7 + * @param[in] u32Condition Specifies the compare condition + * - \ref ADC_CMP_LESS_THAN + * - \ref ADC_CMP_GREATER_OR_EQUAL_TO + * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF + * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16 + * @return None + * @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10); + * Means ADC will assert comparator 0 flag if channel 5 conversion result is + * greater or equal to 0x800 for 10 times continuously. + * \hideinitializer + */ +#define ADC_ENABLE_CMP0(adc, \ + u32ChNum, \ + u32Condition, \ + u32Data, \ + u32MatchCount) (ADC->CMPR0 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \ + (u32Condition) | \ + ((u32Data) << ADC_CMPR_CMPD_Pos) | \ + (((u32MatchCount) - 1) << ADC_CMPR_CMPMATCNT_Pos) |\ + ADC_CMPR_CMPEN_Msk) + +/** + * @brief Disable comparator 0 + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_DISABLE_CMP0(adc) (ADC->CMPR0 = 0) + +/** + * @brief Configure the comparator 1 and enable it + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7 + * @param[in] u32Condition Specifies the compare condition + * - \ref ADC_CMP_LESS_THAN + * - \ref ADC_CMP_GREATER_OR_EQUAL_TO + * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF + * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16 + * @return None + * @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10); + * Means ADC will assert comparator 1 flag if channel 5 conversion result is + * greater or equal to 0x800 for 10 times continuously. + * \hideinitializer + */ +#define ADC_ENABLE_CMP1(adc, \ + u32ChNum, \ + u32Condition, \ + u32Data, \ + u32MatchCount) (ADC->CMPR1 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \ + (u32Condition) | \ + ((u32Data) << ADC_CMPR_CMPD_Pos) | \ + ((u32MatchCount - 1) << ADC_CMPR_CMPMATCNT_Pos) |\ + ADC_CMPR_CMPEN_Msk) + +/** + * @brief Disable comparator 1 + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_DISABLE_CMP1(adc) (ADC->CMPR1 = 0) + +/** + * @brief Set ADC input channel. Enabled channel will be converted while ADC starts. + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * \hideinitializer + */ +#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_Msk) | (u32Mask)) + +/** + * @brief Start the A/D conversion. + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_START_CONV(adc) (ADC->CR |= ADC_CR_ADST_Msk) + +/** + * @brief Stop the A/D conversion. + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_STOP_CONV(adc) (ADC->CR &= ~ADC_CR_ADST_Msk) + +/** + * @brief Set the output format in differential input mode. + * @param[in] adc Base address of ADC module + * @param[in] u32Format Differential input mode output format. Valid values are: + * - \ref ADC_DMODE_OUT_FORMAT_UNSIGNED + * - \ref ADC_DMODE_OUT_FORMAT_2COMPLEMENT + * @return None + * \hideinitializer + */ +#define ADC_SET_DMOF(adc, u32Format) (ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32Format) + +/** + * @brief Set the resolution of conversion result. + * @param[in] adc Base address of ADC module + * @param[in] u32Resolution The resolution of conversion result. Valid values are: + * - \ref ADC_RESSEL_6_BIT + * - \ref ADC_RESSEL_8_BIT + * - \ref ADC_RESSEL_10_BIT + * - \ref ADC_RESSEL_12_BIT + * @return None + * \hideinitializer + */ +#define ADC_SET_RESOLUTION(adc, u32Resolution) (ADC->CR = (ADC->CR & ~ADC_CR_RESSEL_Msk) | u32Resolution) + +/** + * @brief Set the reference voltage selection. + * @param[in] adc Base address of ADC module + * @param[in] u32Ref The reference voltage selection. Valid values are: + * - \ref ADC_REFSEL_POWER + * - \ref ADC_REFSEL_INT_VREF + * - \ref ADC_REFSEL_VREF + * @return None + * \hideinitializer + */ +#define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk) | u32Ref) + +/** + * @brief Set power down mode. + * @param[in] adc Base address of ADC module + * @param[in] u32Mode The power down mode. 0: power down mode, 2: standby mode + * @param[in] u32CalEn Do calibration when power up. + * @return None + * \hideinitializer + */ +#define ADC_SET_POWERDOWN_MODE(adc, u32Mode, u32CalEn) \ + ADC->PWRCTL = (ADC->PWRCTL & ~(ADC_PWRCTL_PWDMOD_Msk | ADC_PWRCTL_PWDCALEN_Msk)) \ + | (u32Mode << ADC_PWRCTL_PWDMOD_Pos) | (u32CalEn << ADC_PWRCTL_PWDCALEN_Pos) + +/** + * @brief Enable PDMA transfer. + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_ENABLE_PDMA(adc) (ADC->CR |= ADC_CR_PTEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_DISABLE_PDMA(adc) (ADC->CR &= ~ADC_CR_PTEN_Msk) + +/** + * @brief Get PDMA current transfer data + * @param[in] adc Base address of ADC module + * @return PDMA current transfer data + * \hideinitializer + */ +#define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMADATA_AD_PDMA_Msk) + +void ADC_Open(ADC_T *adc, + uint32_t u32InputMode, + uint32_t u32OpMode, + uint32_t u32ChMask); +void ADC_Close(ADC_T *adc); +void ADC_EnableHWTrigger(ADC_T *adc, + uint32_t u32Source, + uint32_t u32Param); +void ADC_DisableHWTrigger(ADC_T *adc); +void ADC_EnableTimerTrigger(ADC_T *adc, + uint32_t u32Source, + uint32_t u32PDMACnt); +void ADC_DisableTimerTrigger(ADC_T *adc); +void ADC_SetExtraSampleTime(ADC_T *adc, + uint32_t u32ChNum, + uint32_t u32SampleTime); +void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask); +void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask); + + + +/*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_ADC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__ADC_H__ + +/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/clk.h b/program/Library/StdDriver/inc/clk.h new file mode 100644 index 0000000..466d24e --- /dev/null +++ b/program/Library/StdDriver/inc/clk.h @@ -0,0 +1,368 @@ +/**************************************************************************//** + * @file clk.h + * @version V1.00 + * $Revision: 20 $ + * $Date: 15/07/08 10:00a $ + * @brief Nano100 series CLK driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup NANO100_CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_128MHZ 128000000 +#define FREQ_120MHZ 120000000 +#define FREQ_48MHZ 48000000 +#define FREQ_42MHZ 42000000 +#define FREQ_32MHZ 32000000 +#define FREQ_24MHZ 24000000 +#define FREQ_12MHZ 12000000 + +/********************* Bit definition of PWRCTL register **********************/ +#define CLK_PWRCTL_HXT_EN (0x1UL<>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */ +#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */ +#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */ +#define NA MODULE_NoMsk /*!< Not Available */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2*/ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) /*!< CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */ +/*-------------------------------------------------------------------------------------------------------------------------------*/ +/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5) */ +/*-------------------------------------------------------------------------------------------------------------------------------*/ +#define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) /*!< TICK Module */ +#define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) /*!< SRAM Module */ +#define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) /*!< EBI Module */ +#define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) /*!< ISP Module */ +#define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) /*!< DMA Module */ +#define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) /*!< GPIO Module */ + +#define SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) /*!< SmartCard2 Module */ +#define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) /*!< SmartCard1 Module */ +#define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) /*!< SmartCard0 Module */ +#define I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) /*!< I2S Module */ +#define ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) /*!< ADC Module */ +#define USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) /*!< USBD Module */ +#define PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) /*!< PWM1 Channel2 and Channel3 Module */ +#define PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) /*!< PWM1 Channel0 and Channel1 Module */ +#define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) /*!< PWM0 Channel2 and Channel3 Module */ +#define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) /*!< PWM0 Channel0 and Channel1 Module */ +#define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) /*!< UART1 Module */ +#define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) /*!< UART0 Module */ +#define SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) /*!< SPI0 Module */ +#define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) /*!< SPI1 Module */ +#define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) /*!< SPI0 Module */ +#define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) /*!< I2C1 Module */ +#define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) /*!< I2C0 Module */ +#define FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) /*!< Frequency Divider0 Output Module */ +#define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) /*!< Timer3 Module */ +#define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) /*!< Timer2 Module */ +#define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) /*!< Timer1 Module */ +#define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) /*!< Timer0 Module */ +#define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) /*!< Real-Time-Clock Module */ +#define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) /*!< Watchdog Timer Module */ +#define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) /*!< LCD Module */ +#define DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) /*!< DAC Module */ +/*@}*/ /* end of group NANO100_CLK_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +int32_t CLK_SysTickDelay(uint32_t us); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); + +/*@}*/ /* end of group NANO100_CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_CLK_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__CLK_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/crc.h b/program/Library/StdDriver/inc/crc.h new file mode 100644 index 0000000..104e7a6 --- /dev/null +++ b/program/Library/StdDriver/inc/crc.h @@ -0,0 +1,159 @@ +/**************************************************************************//** + * @file crc.h + * @version V1.00 + * $Revision: 2 $ + * $Date: 15/06/10 4:50p $ + * @brief Nano100 series CRC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup NANO100_CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT 0x00000000UL /*!DMAIER |= (u32Mask)) + +/** + * @brief Disable CRC Interrupt + * + * @param[in] u32Mask Interrupt mask + * + * @return None + * + * @details This macro disable the interrupts. + */ +#define CRC_DISABLE_INT(u32Mask) (PDMACRC->DMAIER &= ~(u32Mask)) + +/** + * @brief Get CRC Interrupt Flag + * + * @param[in] None + * + * @return Interrupt Flag + * + * @details This macro gets the interrupt flag. + */ +#define CRC_GET_INT_FLAG() ((uint32_t)(PDMACRC->DMAISR)) + +/** + * @brief Clear CRC Interrupt Flag + * + * @param[in] u32Mask Interrupt mask + * + * @return None + * + * @details This macro clear the interrupt flag. + */ +#define CRC_CLR_INT_FLAG(u32Mask) (PDMACRC->DMAISR |= (u32Mask)) + +/** + * @brief Set CRC seed value + * + * @param[in] u32Seed Seed value + * + * @return None + * + * @details This macro set seed value. + */ +#define CRC_SET_SEED(u32Seed) { PDMACRC->SEED = (u32Seed); PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk; } + +/** + * @brief Get CRC Seed value + * + * @param[in] None + * + * @return Seed Value + * + * @details This macro gets the seed value. + */ +#define CRC_GET_SEED() ((uint32_t)(PDMACRC->SEED)) + +/** + * @brief CRC write data + * + * @param[in] u32Data write data + * + * @return None + * + * @details This macro write CRC data. + */ +#define CRC_WRITE_DATA(u32Data) (PDMACRC->WDATA = (u32Data)) + + +/*********************************************************************/ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount); +uint32_t CRC_GetChecksum(void); + + +/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_CRC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__CRC_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/dac.h b/program/Library/StdDriver/inc/dac.h new file mode 100644 index 0000000..ae546fa --- /dev/null +++ b/program/Library/StdDriver/inc/dac.h @@ -0,0 +1,180 @@ +/**************************************************************************//** + * @file dac.h + * @version V1.00 + * $Revision: 4 $ + * $Date: 14/09/08 12:31p $ + * @brief NANO100 series DAC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup NANO100_DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ +#define DAC_WRITE_DAT_TRIGGER (0UL << DAC_CTL_DACLSEL_Pos) ///< Write DACx_DAT trigger \hideinitializer +#define DAC_PDMA_TRIGGER (1UL << DAC_CTL_DACLSEL_Pos) ///< PDMA trigger \hideinitializer +#define DAC_TIMER0_TRIGGER (2UL << DAC_CTL_DACLSEL_Pos) ///< Timer 0 trigger \hideinitializer +#define DAC_TIMER1_TRIGGER (3UL << DAC_CTL_DACLSEL_Pos) ///< Timer 1 trigger \hideinitializer +#define DAC_TIMER2_TRIGGER (4UL << DAC_CTL_DACLSEL_Pos) ///< Timer 2 trigger \hideinitializer +#define DAC_TIMER3_TRIGGER (5UL << DAC_CTL_DACLSEL_Pos) ///< Timer 3 trigger \hideinitializer + +#define DAC_REFSEL_POWER (0UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to power \hideinitializer +#define DAC_REFSEL_INT_VREF (1UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to Int_VREF \hideinitializer +#define DAC_REFSEL_VREF (2UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to VREF \hideinitializer + +/*@}*/ /* end of group NANO100_DAC_EXPORTED_CONSTANTS */ + + + +/** @addtogroup NANO100_DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief Write data for conversion. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * \hideinitializer + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) do {\ + if(u32Ch) {\ + DAC->DATA1 = u32Data;\ + } else {\ + DAC->DATA0 = u32Data;\ + }\ + }while(0) + + +/** + * @brief Enable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) (DAC->COMCTL |= DAC_COMCTL_DAC01GRP_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) (DAC->COMCTL &= ~DAC_COMCTL_DAC01GRP_Msk) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @return If DAC is able to convert or not. + * @retval 0 DAC is in idle state. + * @retval 1 DAC is in busy state, or DAC is not in ready state. + * @details If this macro returns 1, DAC is \b not in ready state. Ether DAC is busy or not in ready state. + * \hideinitializer + */ +#define DAC_IS_BUSY(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_BUSY_Msk ? 1 : 0) + + +/** + * @brief Get the interrupt flag of specified channel. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @return Returns the interrupt flag of selected channel. + * @retval 0 DAC interrupt flag is not set. + * @retval 1 DAC interrupt flag is set. + * \hideinitializer + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_DACIFG_Msk ? 1 : 0) + +/** + * @brief This macro clear the interrupt status bit of specified channel. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @return None + * \hideinitializer + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) do {\ + if(u32Ch)\ + DAC->STS1 = DAC_STS_DACIFG_Msk;\ + else\ + DAC->STS0 = DAC_STS_DACIFG_Msk;\ + }while(0) + + +/** + * @brief Set the DAC reference voltage. This setting affects both DAC channel + * @param[in] dac Base address of DAC module + * @param[in] u32Ref The reference voltage selection. Valid values are: + * - \ref DAC_REFSEL_POWER + * - \ref DAC_REFSEL_INT_VREF + * - \ref DAC_REFSEL_VREF + * @return None + * \hideinitializer + */ +#define DAC_SET_REF_VOLTAGE(dac, u32Ref) (DAC->COMCTL = ((DAC->COMCTL) & ~DAC_COMCTL_REFSEL_Msk) | u32Ref) + +/** + * @brief This macro enable the interrupt of specified channel. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @return None + * \hideinitializer + */ +#define DAC_ENABLE_INT(dac, u32Ch) do {\ + if(u32Ch)\ + DAC->CTL1 |= DAC_CTL_DACIE_Msk;\ + else\ + DAC->CTL0 |= DAC_CTL_DACIE_Msk;\ + }while(0) + +/** + * @brief This macro disable the interrupt of specified channel. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @return None + * \hideinitializer + */ +#define DAC_DISABLE_INT(dac, u32Ch) do {\ + if(u32Ch)\ + DAC->CTL1 &= ~DAC_CTL_DACIE_Msk;\ + else\ + DAC->CTL0 &= ~DAC_CTL_DACIE_Msk;\ + }while(0) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group NANO100_DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_DAC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__DAC_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/ebi.h b/program/Library/StdDriver/inc/ebi.h new file mode 100644 index 0000000..cf6af56 --- /dev/null +++ b/program/Library/StdDriver/inc/ebi.h @@ -0,0 +1,151 @@ +/**************************************************************************//** + * @file ebi.h + * @version V1.00 + * $Revision: 4 $ + * $Date: 14/09/30 4:21p $ + * @brief Nano100 Series Flash Memory Controller Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_EBI_Driver EBI Driver + @{ +*/ + + +/** @addtogroup NANO100_EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BASE_ADDR 0x60000000 /*!< EBI base address */ +#define EBI_MAX_SIZE 0x20000 /*!< Maximum size of EBI bank */ +#define EBI_TIMEOUT_COUNT 0x10000 /*!< Time-out value */ + +/* Constants for EBI data bus width */ +#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */ +#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EBI MCLK divider */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0 /*!< MCLK divided by 1 */ +#define EBI_MCLKDIV_2 1 /*!< MCLK divided by 2 */ +#define EBI_MCLKDIV_4 2 /*!< MCLK divided by 4 */ +#define EBI_MCLKDIV_8 3 /*!< MCLK divided by 8 */ +#define EBI_MCLKDIV_16 4 /*!< MCLK divided by 16 */ +#define EBI_MCLKDIV_32 5 /*!< MCLK divided by 32 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EBI timing setting */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_TIMING_FASTEST 0x0 /*!< EBI timing is the fastest */ +#define EBI_TIMING_VERYFAST 0x1 /*!< EBI timing is the very fast */ +#define EBI_TIMING_FAST 0x2 /*!< EBI timing is the fast */ +#define EBI_TIMING_NORMAL 0x3 /*!< EBI timing is the normal */ +#define EBI_TIMING_SLOW 0x4 /*!< EBI timing is the slow */ +#define EBI_TIMING_VERYSLOW 0x5 /*!< EBI timing is the very slow */ +#define EBI_TIMING_SLOWEST 0x6 /*!< EBI timing is the slowest */ + + +/*@}*/ /* end of group NANO100_EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EBI access macros */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @brief Read one byte data from EBI. + * @param[in] Addr EBI offset address. + * @return Byte data read from EBI. + * \hideinitializer + */ +#define EBI_READ_DATA8(Addr) *((volatile unsigned char *)(EBI_BASE_ADDR+Addr)) + +/** + * @brief Write one byte data to EBI. + * @param[in] Addr EBI offset address. + * @param[in] Data Byte data to be written. + * @return None + * \hideinitializer + */ +#define EBI_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI_BASE_ADDR+Addr))=Data + +/** + * @brief Read a half-word data from EBI. + * @param[in] Addr EBI offset address. + * @return Half-word data read from EBI. + * \hideinitializer + */ +#define EBI_READ_DATA16(Addr) *((volatile unsigned short *)(EBI_BASE_ADDR+Addr)) + +/** + * @brief Write a half-word data to EBI. + * @param[in] Addr EBI offset address. + * @param[in] Data Half-word data to be written. + * @return None + * \hideinitializer + */ +#define EBI_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI_BASE_ADDR+Addr))=Data + +/** + * @brief Read a word data from EBI. + * @param[in] Addr EBI offset address. + * @return Word data read from EBI. + * \hideinitializer + */ +#define EBI_READ_DATA32(Addr) *((volatile unsigned int *)(EBI_BASE_ADDR+Addr)) + +/** + * @brief Write a word data to EBI. + * @param[in] Addr EBI offset address. + * @param[in] Data Word data to be written. + * @return None + * \hideinitializer + */ +#define EBI_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI_BASE_ADDR+Addr))=Data + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint8_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + + +/*@}*/ /* end of group NANO100_EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_EBI_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif // __EBI_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/fmc.h b/program/Library/StdDriver/inc/fmc.h new file mode 100644 index 0000000..24d1eed --- /dev/null +++ b/program/Library/StdDriver/inc/fmc.h @@ -0,0 +1,207 @@ +/**************************************************************************//** + * @file fmc.h + * @version V1.00 + * $Revision: 5 $ + * $Date: 15/06/12 2:11p $ + * @brief Nano100B Series Flash Memory Controller Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup NANO100_FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ +#define FMC_APROM_END 0x0001EC00UL /*!< APROM End Address */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ +#define FMC_LDROM_END 0x00101000UL /*!< LDROM End Address */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration Address */ + +#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 bytes) */ +#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 Kbytes) */ + +#define FMC_TIMEOUT_READ ((SystemCoreClock/10)*2) /*!< Read command time-out 100 ms \hideinitializer */ +#define FMC_TIMEOUT_WRITE ((SystemCoreClock/10)*2) /*!< Write command time-out 100 ms \hideinitializer */ +#define FMC_TIMEOUT_ERASE ((SystemCoreClock/10)*4) /*!< Erase command time-out 200 ms \hideinitializer */ +#define FMC_TIMEOUT_CHKSUM (SystemCoreClock*2) /*!< Get checksum command time-out 2 s \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read flash word */ +#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Write flash word */ +#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */ +#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */ +#define FMC_ISPCMD_READ_PID 0x0C /*!< ISP Command: Read Product ID */ +#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */ +#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Vector Page Remap */ + +#define IS_BOOT_FROM_APROM 0 /*!< Is booting from APROM */ +#define IS_BOOT_FROM_LDROM 1 /*!< Is booting from LDROM */ + + +/*@}*/ /* end of group NANO100_FMC_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macros */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro selects booting from APROM. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_SET_APROM_BOOT() (FMC->ISPCON &= ~FMC_ISPCON_BS_Msk) + +/** + * @brief This macro selects booting from LDROM. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCON |= FMC_ISPCON_BS_Msk) + +/** + * @brief This macro enables APROM update function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCON |= FMC_ISPCON_APUEN_Msk) + +/** + * @brief This macro disables APROM update function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk) + +/** + * @brief This macro enables User Configuration update function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk) + +/** + * @brief This macro disables User Configuration update function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk) + +/** + * @brief This macro enables LDROM update function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk) + +/** + * @brief This macro disables LDROM update function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk) + +/** + * @brief This macro enables ISP function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_ENABLE_ISP() (FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk) + +/** + * @brief This macro disables ISP function. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_DISABLE_ISP() (FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk) + +/** + * @brief This macro gets ISP fail flag value. + * @param None + * @return ISP fail flag value. + * \hideinitializer + */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) ? 1 : 0) + +/** + * @brief This macro clears ISP fail flag. + * @param None + * @return None + * \hideinitializer + */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCON |= FMC_ISPCON_ISPFF_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern void FMC_Close(void); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_GetBootSource(void); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern uint32_t FMC_ReadCID(void); +extern uint32_t FMC_ReadPID(void); +extern uint32_t FMC_ReadUCID(uint32_t u32Index); +extern uint32_t FMC_ReadUID(uint32_t u32Index); +extern uint32_t FMC_ReadDataFlashBaseAddr(void); +extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +extern uint32_t FMC_GetVectorPageAddr(void); +extern int32_t FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count); +extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count); + + +/*@}*/ /* end of group NANO100_FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_FMC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif // __FMC_H__ + +/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/gpio.h b/program/Library/StdDriver/inc/gpio.h new file mode 100644 index 0000000..b73d724 --- /dev/null +++ b/program/Library/StdDriver/inc/gpio.h @@ -0,0 +1,444 @@ +/**************************************************************************//** + * @file gpio.h + * @version V1.00 + * $Revision: 7 $ + * $Date: 14/12/01 10:30a $ + * @brief Nano100 series GPIO driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup NANO100_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ +#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PMD Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PMD_INPUT 0x0UL /*!< Input Mode */ +#define GPIO_PMD_OUTPUT 0x1UL /*!< Output Mode */ +#define GPIO_PMD_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* IMD Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */ +#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DBNCECON Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_ICLK_ON 0x00000020UL /*!< DBNCECON setting for all IO pins edge detection circuit is always active after reset */ +#define GPIO_ICLK_OFF 0x00000000UL /*!< DBNCECON setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */ + +#define GPIO_DBCLKSRC_IRC10K 0x00000010UL /*!< DBNCECON setting for de-bounce counter clock source is the internal 10 kHz */ +#define GPIO_DBCLKSRC_HCLK 0x00000000UL /*!< DBNCECON setting for de-bounce counter clock source is the internal HCLK */ + +#define GPIO_DBCLKSEL_1 0x00000000UL /*!< DBNCECON setting for sampling cycle = 1 clocks */ +#define GPIO_DBCLKSEL_2 0x00000001UL /*!< DBNCECON setting for sampling cycle = 2 clocks */ +#define GPIO_DBCLKSEL_4 0x00000002UL /*!< DBNCECON setting for sampling cycle = 4 clocks */ +#define GPIO_DBCLKSEL_8 0x00000003UL /*!< DBNCECON setting for sampling cycle = 8 clocks */ +#define GPIO_DBCLKSEL_16 0x00000004UL /*!< DBNCECON setting for sampling cycle = 16 clocks */ +#define GPIO_DBCLKSEL_32 0x00000005UL /*!< DBNCECON setting for sampling cycle = 32 clocks */ +#define GPIO_DBCLKSEL_64 0x00000006UL /*!< DBNCECON setting for sampling cycle = 64 clocks */ +#define GPIO_DBCLKSEL_128 0x00000007UL /*!< DBNCECON setting for sampling cycle = 128 clocks */ +#define GPIO_DBCLKSEL_256 0x00000008UL /*!< DBNCECON setting for sampling cycle = 256 clocks */ +#define GPIO_DBCLKSEL_512 0x00000009UL /*!< DBNCECON setting for sampling cycle = 512 clocks */ +#define GPIO_DBCLKSEL_1024 0x0000000AUL /*!< DBNCECON setting for sampling cycle = 1024 clocks */ +#define GPIO_DBCLKSEL_2048 0x0000000BUL /*!< DBNCECON setting for sampling cycle = 2048 clocks */ +#define GPIO_DBCLKSEL_4096 0x0000000CUL /*!< DBNCECON setting for sampling cycle = 4096 clocks */ +#define GPIO_DBCLKSEL_8192 0x0000000DUL /*!< DBNCECON setting for sampling cycle = 8192 clocks */ +#define GPIO_DBCLKSEL_16384 0x0000000EUL /*!< DBNCECON setting for sampling cycle = 16384 clocks */ +#define GPIO_DBCLKSEL_32768 0x0000000FUL /*!< DBNCECON setting for sampling cycle = 32768 clocks */ + +/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + * Example 1: + * + * PA0 = 1; + * + * It is used to set PA0 to high; + * + * Example 2: + * + * if (PA0) + * PA0 = 0; + * + * If PA0 pin status is high, then set PA0 data output to low. + */ +#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#define PA0 GPIO_PIN_ADDR(0, 0) /*!< Specify PA0 Pin Data Input/Output */ +#define PA1 GPIO_PIN_ADDR(0, 1) /*!< Specify PA1 Pin Data Input/Output */ +#define PA2 GPIO_PIN_ADDR(0, 2) /*!< Specify PA2 Pin Data Input/Output */ +#define PA3 GPIO_PIN_ADDR(0, 3) /*!< Specify PA3 Pin Data Input/Output */ +#define PA4 GPIO_PIN_ADDR(0, 4) /*!< Specify PA4 Pin Data Input/Output */ +#define PA5 GPIO_PIN_ADDR(0, 5) /*!< Specify PA5 Pin Data Input/Output */ +#define PA6 GPIO_PIN_ADDR(0, 6) /*!< Specify PA6 Pin Data Input/Output */ +#define PA7 GPIO_PIN_ADDR(0, 7) /*!< Specify PA7 Pin Data Input/Output */ +#define PA8 GPIO_PIN_ADDR(0, 8) /*!< Specify PA8 Pin Data Input/Output */ +#define PA9 GPIO_PIN_ADDR(0, 9) /*!< Specify PA9 Pin Data Input/Output */ +#define PA10 GPIO_PIN_ADDR(0, 10) /*!< Specify PA10 Pin Data Input/Output */ +#define PA11 GPIO_PIN_ADDR(0, 11) /*!< Specify PA11 Pin Data Input/Output */ +#define PA12 GPIO_PIN_ADDR(0, 12) /*!< Specify PA12 Pin Data Input/Output */ +#define PA13 GPIO_PIN_ADDR(0, 13) /*!< Specify PA13 Pin Data Input/Output */ +#define PA14 GPIO_PIN_ADDR(0, 14) /*!< Specify PA14 Pin Data Input/Output */ +#define PA15 GPIO_PIN_ADDR(0, 15) /*!< Specify PA15 Pin Data Input/Output */ + +#define PB0 GPIO_PIN_ADDR(1, 0) /*!< Specify PB0 Pin Data Input/Output */ +#define PB1 GPIO_PIN_ADDR(1, 1) /*!< Specify PB1 Pin Data Input/Output */ +#define PB2 GPIO_PIN_ADDR(1, 2) /*!< Specify PB2 Pin Data Input/Output */ +#define PB3 GPIO_PIN_ADDR(1, 3) /*!< Specify PB3 Pin Data Input/Output */ +#define PB4 GPIO_PIN_ADDR(1, 4) /*!< Specify PB4 Pin Data Input/Output */ +#define PB5 GPIO_PIN_ADDR(1, 5) /*!< Specify PB5 Pin Data Input/Output */ +#define PB6 GPIO_PIN_ADDR(1, 6) /*!< Specify PB6 Pin Data Input/Output */ +#define PB7 GPIO_PIN_ADDR(1, 7) /*!< Specify PB7 Pin Data Input/Output */ +#define PB8 GPIO_PIN_ADDR(1, 8) /*!< Specify PB8 Pin Data Input/Output */ +#define PB9 GPIO_PIN_ADDR(1, 9) /*!< Specify PB9 Pin Data Input/Output */ +#define PB10 GPIO_PIN_ADDR(1, 10) /*!< Specify PB10 Pin Data Input/Output */ +#define PB11 GPIO_PIN_ADDR(1, 11) /*!< Specify PB11 Pin Data Input/Output */ +#define PB12 GPIO_PIN_ADDR(1, 12) /*!< Specify PB12 Pin Data Input/Output */ +#define PB13 GPIO_PIN_ADDR(1, 13) /*!< Specify PB13 Pin Data Input/Output */ +#define PB14 GPIO_PIN_ADDR(1, 14) /*!< Specify PB14 Pin Data Input/Output */ +#define PB15 GPIO_PIN_ADDR(1, 15) /*!< Specify PB15 Pin Data Input/Output */ + +#define PC0 GPIO_PIN_ADDR(2, 0) /*!< Specify PC0 Pin Data Input/Output */ +#define PC1 GPIO_PIN_ADDR(2, 1) /*!< Specify PC1 Pin Data Input/Output */ +#define PC2 GPIO_PIN_ADDR(2, 2) /*!< Specify PC2 Pin Data Input/Output */ +#define PC3 GPIO_PIN_ADDR(2, 3) /*!< Specify PC3 Pin Data Input/Output */ +#define PC4 GPIO_PIN_ADDR(2, 4) /*!< Specify PC4 Pin Data Input/Output */ +#define PC5 GPIO_PIN_ADDR(2, 5) /*!< Specify PC5 Pin Data Input/Output */ +#define PC6 GPIO_PIN_ADDR(2, 6) /*!< Specify PC6 Pin Data Input/Output */ +#define PC7 GPIO_PIN_ADDR(2, 7) /*!< Specify PC7 Pin Data Input/Output */ +#define PC8 GPIO_PIN_ADDR(2, 8) /*!< Specify PC8 Pin Data Input/Output */ +#define PC9 GPIO_PIN_ADDR(2, 9) /*!< Specify PC9 Pin Data Input/Output */ +#define PC10 GPIO_PIN_ADDR(2, 10) /*!< Specify PC10 Pin Data Input/Output */ +#define PC11 GPIO_PIN_ADDR(2, 11) /*!< Specify PC11 Pin Data Input/Output */ +#define PC12 GPIO_PIN_ADDR(2, 12) /*!< Specify PC12 Pin Data Input/Output */ +#define PC13 GPIO_PIN_ADDR(2, 13) /*!< Specify PC13 Pin Data Input/Output */ +#define PC14 GPIO_PIN_ADDR(2, 14) /*!< Specify PC14 Pin Data Input/Output */ +#define PC15 GPIO_PIN_ADDR(2, 15) /*!< Specify PC15 Pin Data Input/Output */ + +#define PD0 GPIO_PIN_ADDR(3, 0) /*!< Specify PD0 Pin Data Input/Output */ +#define PD1 GPIO_PIN_ADDR(3, 1) /*!< Specify PD1 Pin Data Input/Output */ +#define PD2 GPIO_PIN_ADDR(3, 2) /*!< Specify PD2 Pin Data Input/Output */ +#define PD3 GPIO_PIN_ADDR(3, 3) /*!< Specify PD3 Pin Data Input/Output */ +#define PD4 GPIO_PIN_ADDR(3, 4) /*!< Specify PD4 Pin Data Input/Output */ +#define PD5 GPIO_PIN_ADDR(3, 5) /*!< Specify PD5 Pin Data Input/Output */ +#define PD6 GPIO_PIN_ADDR(3, 6) /*!< Specify PD6 Pin Data Input/Output */ +#define PD7 GPIO_PIN_ADDR(3, 7) /*!< Specify PD7 Pin Data Input/Output */ +#define PD8 GPIO_PIN_ADDR(3, 8) /*!< Specify PD8 Pin Data Input/Output */ +#define PD9 GPIO_PIN_ADDR(3, 9) /*!< Specify PD9 Pin Data Input/Output */ +#define PD10 GPIO_PIN_ADDR(3, 10) /*!< Specify PD10 Pin Data Input/Output */ +#define PD11 GPIO_PIN_ADDR(3, 11) /*!< Specify PD11 Pin Data Input/Output */ +#define PD12 GPIO_PIN_ADDR(3, 12) /*!< Specify PD12 Pin Data Input/Output */ +#define PD13 GPIO_PIN_ADDR(3, 13) /*!< Specify PD13 Pin Data Input/Output */ +#define PD14 GPIO_PIN_ADDR(3, 14) /*!< Specify PD14 Pin Data Input/Output */ +#define PD15 GPIO_PIN_ADDR(3, 15) /*!< Specify PD15 Pin Data Input/Output */ + +#define PE0 GPIO_PIN_ADDR(4, 0) /*!< Specify PE0 Pin Data Input/Output */ +#define PE1 GPIO_PIN_ADDR(4, 1) /*!< Specify PE1 Pin Data Input/Output */ +#define PE2 GPIO_PIN_ADDR(4, 2) /*!< Specify PE2 Pin Data Input/Output */ +#define PE3 GPIO_PIN_ADDR(4, 3) /*!< Specify PE3 Pin Data Input/Output */ +#define PE4 GPIO_PIN_ADDR(4, 4) /*!< Specify PE4 Pin Data Input/Output */ +#define PE5 GPIO_PIN_ADDR(4, 5) /*!< Specify PE5 Pin Data Input/Output */ +#define PE6 GPIO_PIN_ADDR(4, 6) /*!< Specify PE6 Pin Data Input/Output */ +#define PE7 GPIO_PIN_ADDR(4, 7) /*!< Specify PE7 Pin Data Input/Output */ +#define PE8 GPIO_PIN_ADDR(4, 8) /*!< Specify PE8 Pin Data Input/Output */ +#define PE9 GPIO_PIN_ADDR(4, 9) /*!< Specify PE9 Pin Data Input/Output */ +#define PE10 GPIO_PIN_ADDR(4, 10) /*!< Specify PE10 Pin Data Input/Output */ +#define PE11 GPIO_PIN_ADDR(4, 11) /*!< Specify PE11 Pin Data Input/Output */ +#define PE12 GPIO_PIN_ADDR(4, 12) /*!< Specify PE12 Pin Data Input/Output */ +#define PE13 GPIO_PIN_ADDR(4, 13) /*!< Specify PE13 Pin Data Input/Output */ +#define PE14 GPIO_PIN_ADDR(4, 14) /*!< Specify PE14 Pin Data Input/Output */ +#define PE15 GPIO_PIN_ADDR(4, 15) /*!< Specify PE15 Pin Data Input/Output */ + +#define PF0 GPIO_PIN_ADDR(5, 0) /*!< Specify PF0 Pin Data Input/Output */ +#define PF1 GPIO_PIN_ADDR(5, 1) /*!< Specify PF1 Pin Data Input/Output */ +#define PF2 GPIO_PIN_ADDR(5, 2) /*!< Specify PF2 Pin Data Input/Output */ +#define PF3 GPIO_PIN_ADDR(5, 3) /*!< Specify PF3 Pin Data Input/Output */ +#define PF4 GPIO_PIN_ADDR(5, 4) /*!< Specify PF4 Pin Data Input/Output */ +#define PF5 GPIO_PIN_ADDR(5, 5) /*!< Specify PF5 Pin Data Input/Output */ + +/*@}*/ /* end of group NANO100_GPIO_EXPORTED_CONSTANTS */ + +/** @addtogroup NANO100_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + */ +#define GPIO_CLR_INT_FLAG(gpio, u32PinMask) ((gpio)->ISRC = u32PinMask) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_DISABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN &= ~u32PinMask) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_ENABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN |= u32PinMask) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + */ +#define GPIO_DISABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->OFFD |= (u32PinMask << 16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + */ +#define GPIO_ENABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->OFFD &= ~(u32PinMask << 16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_DISABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DMASK &= ~u32PinMask) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_ENABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DMASK |= u32PinMask) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + */ +#define GPIO_GET_INT_FLAG(gpio, u32PinMask) ((gpio)->ISRC & u32PinMask) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be \ref GPIO_DBCLKSRC_HCLK or \ref GPIO_DBCLKSRC_IRC10K + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be \n + * \ref GPIO_DBCLKSEL_1, \ref GPIO_DBCLKSEL_2, \ref GPIO_DBCLKSEL_4, \ref GPIO_DBCLKSEL_8, \n + * \ref GPIO_DBCLKSEL_16, \ref GPIO_DBCLKSEL_32, \ref GPIO_DBCLKSEL_64, \ref GPIO_DBCLKSEL_128, \n + * \ref GPIO_DBCLKSEL_256, \ref GPIO_DBCLKSEL_512, \ref GPIO_DBCLKSEL_1024, \ref GPIO_DBCLKSEL_2048, \n + * \ref GPIO_DBCLKSEL_4096, \ref GPIO_DBCLKSEL_8192, \ref GPIO_DBCLKSEL_16384, \ref GPIO_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: \ref GPIO_SET_DEBOUNCE_TIME(\ref GPIO_DBCLKSRC_IRC10K, \ref GPIO_DBCLKSEL_4) \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us, + * and system will sampling interrupt input once per 1600 us. + */ +#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBNCECON = (GP_DBNCECON_DBCLK_ON_Msk | u32ClkSrc | u32ClkSel)) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * + * @retval The specified port data + * + * @details Get the PIN register of specified GPIO port. + */ +#define GPIO_GET_IN_DATA(gpio) ((gpio)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Data GPIO port data + * + * @retval None + * + * @details Set the Data into specified GPIO port. + */ +#define GPIO_SET_OUT_DATA(gpio, u32Data) ((gpio)->DOUT = (u32Data)) + +/** + * @brief Disable Pin Pull-up resistor Function + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Disable the Pull-up resistor function of specified GPIO pin. + */ +#define GPIO_DISABLE_PULL_UP(gpio, u32PinMask) ((gpio)->PUEN &= ~u32PinMask) + +/** + * @brief Enable Pin Pull-up resistor Function + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port + * + * @return None + * + * @details Enable the Pull-up resistor function of specified GPIO pin. + */ +#define GPIO_ENABLE_PULL_UP(gpio, u32PinMask) ((gpio)->PUEN |= u32PinMask) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @retval None + * + * @details Toggle the specified GPIO pint. + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + +/** + * @brief Enable External GPIO interrupt 0 + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Pin The pin of specified GPIO port + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT0 GPIO_EnableInt + + +/** + * @brief Disable External GPIO interrupt 0 + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15 + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT0 GPIO_DisableInt + + +/** + * @brief Enable External GPIO interrupt 1 + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Pin The pin of specified GPIO port + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT1 GPIO_EnableInt + + +/** + * @brief Disable External GPIO interrupt 1 + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15 + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT1 GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin); + + + +/*@}*/ /* end of group NANO100_GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_GPIO_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__GPIO_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/i2c.h b/program/Library/StdDriver/inc/i2c.h new file mode 100644 index 0000000..593f161 --- /dev/null +++ b/program/Library/StdDriver/inc/i2c.h @@ -0,0 +1,194 @@ +/****************************************************************************//** + * @file i2c.h + * @version V1.00 + * $Revision: 5 $ + * $Date: 15/06/05 5:06p $ + * @brief Nano100 series I2C driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup NANO100_I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +#define I2C_STA 0x08 /*!< I2C START bit value */ +#define I2C_STO 0x04 /*!< I2C STOP bit value*/ +#define I2C_SI 0x10 /*!< I2C SI bit value */ +#define I2C_AA 0x02 /*!< I2C ACK bit value */ + +#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */ +#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */ + +/*@}*/ /* end of group NANO100_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the I2C control register at one time. + * @param[in] i2c is the base address of I2C module. + * @param[in] u8Ctrl is the register value of I2C control register. + * @return none + * \hideinitializer + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ( (i2c)->CON = ((i2c)->CON & ~0x1e) | u8Ctrl ) + +/** + * @brief This macro only set START bit to the control register of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + * \hideinitializer + */ +#define I2C_START(i2c) ( (i2c)->CON = ((i2c)->CON & ~I2C_CON_I2C_STS_Msk) | I2C_CON_START_Msk ) + +/** + * @brief This macro only set STOP bit to the control register of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return 0 success + * @return -1 time out + * \hideinitializer + */ +static __INLINE int32_t I2C_STOP(I2C_T *i2c) +{ + int32_t tout = (SystemCoreClock / 10); + + i2c->CON |= (I2C_CON_I2C_STS_Msk | I2C_CON_STOP_Msk); + while((i2c->CON & I2C_CON_STOP_Msk) && (tout-- > 0)); + if (i2c->CON & I2C_CON_STOP_Msk) + return -1; + return 0; +} + +/** + * @brief This macro will return when I2C module is ready. + * @param[in] i2c is the base address of I2C module. + * @return 0 success + * @return -1 time out + * \hideinitializer + */ +static __INLINE int32_t I2C_WAIT_READY(I2C_T *i2c) +{ + int32_t tout = (SystemCoreClock / 10); + + while(!(i2c->INTSTS & I2C_INTSTS_INTSTS_Msk) && (tout-- > 0)); + if (!(i2c->INTSTS & I2C_INTSTS_INTSTS_Msk)) + return -1; + i2c->INTSTS |= I2C_INTSTS_INTSTS_Msk; + return 0; +} + +/** + * @brief This macro returns the data stored in data register of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return Data. + * \hideinitializer + */ +#define I2C_GET_DATA(i2c) ( (i2c)->DATA ) + +/** + * @brief This macro writes the data to data register of I2C module. + * @param[in] i2c is the base address of I2C module. + * @param[in] u8Data is the data which will be write to data register of I2C module. + * @return none + * \hideinitializer + */ +#define I2C_SET_DATA(i2c, u8Data) ( (i2c)->DATA = u8Data ) + +/** + * @brief This macro returns the status of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return Status. + * \hideinitializer + */ +#define I2C_GET_STATUS(i2c) ( (i2c)->STATUS ) + +/** + * @brief This macro returns timeout flag. + * @param[in] i2c is the base address of I2C module. + * @return Status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->INTSTS & I2C_INTSTS_TIF_Msk) == I2C_INTSTS_TIF_Msk ? 1:0 ) + +/** + * @brief This macro clears timeout flag. + * @param[in] i2c is the base address of I2C module. + * @return none + * \hideinitializer + */ +#define I2C_CLEAR_TIMEOUT_FLAG(i2c) ( (i2c)->INTSTS |= I2C_INTSTS_TIF_Msk ) + +/** + * @brief This macro returns wakeup flag. + * @param[in] i2c is the base address of I2C module. + * @return Status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKUPSTS & I2C_WKUPSTS_WKUPIF_Msk) == I2C_WKUPSTS_WKUPIF_Msk ? 1:0 ) + +/** + * @brief This macro clears wakeup flag. + * @param[in] i2c is the base address of I2C module. + * @return none + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->WKUPSTS |= I2C_WKUPSTS_WKUPIF_Msk ) + +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +void I2C_Close(I2C_T *i2c); +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +void I2C_ClearIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_GetData(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); + +/*@}*/ /* end of group NANO100_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_I2C_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__I2C_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/i2s.h b/program/Library/StdDriver/inc/i2s.h new file mode 100644 index 0000000..5669d76 --- /dev/null +++ b/program/Library/StdDriver/inc/i2s.h @@ -0,0 +1,297 @@ +/**************************************************************************//** + * @file i2s.h + * @version V1.00 + * $Revision: 5 $ + * $Date: 15/06/08 4:59p $ + * @brief Nano100 series I2S driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup NANO100_I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 8-bit */ +#define I2S_DATABIT_16 (1 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 16-bit */ +#define I2S_DATABIT_24 (2 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 24-bit */ +#define I2S_DATABIT_32 (3 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 32-bit */ + +/* Audio Format */ +#define I2S_MONO I2S_CTRL_MONO_Msk /*!< Mono channel */ +#define I2S_STEREO 0 /*!< Stereo channel */ + +/* I2S Data Format */ +#define I2S_FORMAT_MSB I2S_CTRL_FORMAT_Msk /*!< MSB data format */ +#define I2S_FORMAT_I2S 0 /*!< I2S data format */ + +/* I2S Interface */ +#define I2S_I2S 0 /*!< I2S interface is selected */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTRL_SLAVE_Msk /*!< As slave mode */ +#define I2S_MODE_MASTER 0 /*!< As master mode */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 1 word */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 2 words */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 3 words */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 4 words */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 5 words */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 6 words */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 7 words */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 2 words */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 3 words */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 4 words */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 5 words */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 6 words */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 7 words */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 8 words */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT 0 /*!< Record mono right channel */ +#define I2S_MONO_LEFT I2S_CTRL_RXLCH_Msk /*!< Record mono left channel */ + +/* I2S Channel */ +#define I2S_RIGHT 0 /*!< Select right channel */ +#define I2S_LEFT 1 /*!< Select left channel */ + +/*@}*/ /* end of group NANO100_I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup NANO100_I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for left or right channel. Valid values are: + * - \ref I2S_RIGHT + * - \ref I2S_LEFT + * @return none + * \hideinitializer + */ +static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == I2S_RIGHT) + i2s->CTRL |= I2S_CTRL_RCHZCEN_Msk; + else + i2s->CTRL |= I2S_CTRL_LCHZCEN_Msk; +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for left or right channel. Valid values are: + * - \ref I2S_RIGHT + * - \ref I2S_LEFT + * @return none + * \hideinitializer + */ +static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == I2S_RIGHT) + i2s->CTRL &= ~I2S_CTRL_RCHZCEN_Msk; + else + i2s->CTRL &= ~I2S_CTRL_LCHZCEN_Msk; +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTRL |= I2S_CTRL_TXDMA_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_TXDMA_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTRL |= I2S_CTRL_RXDMA_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_RXDMA_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTRL |= I2S_CTRL_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTRL |= I2S_CTRL_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTRL |= I2S_CTRL_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTRL |= I2S_CTRL_CLR_TXFIFO_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTRL |= I2S_CTRL_CLR_RXFIFO_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +#define I2S_SET_MONO_RX_CHANNEL(i2s, u32Ch) ( u32Ch == I2S_MONO_LEFT ? ((i2s)->CTRL |= I2S_CTRL_RXLCH_Msk) : ((i2s)->CTRL &= ~I2S_CTRL_RXLCH_Msk) ) + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = u32Data ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ((i2s)->STATUS & (u32Mask)) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ((((i2s)->STATUS & I2S_STATUS_TX_LEVEL_Msk) >> I2S_STATUS_TX_LEVEL_Pos) & 0xF) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ((((i2s)->STATUS & I2S_STATUS_RX_LEVEL_Msk) >> I2S_STATUS_RX_LEVEL_Pos) & 0xF) + +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface); +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + +/*@}*/ /* end of group NANO100_I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group NANO100_I2S_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__I2S_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + diff --git a/program/Library/StdDriver/inc/lcd.h b/program/Library/StdDriver/inc/lcd.h new file mode 100644 index 0000000..371a499 --- /dev/null +++ b/program/Library/StdDriver/inc/lcd.h @@ -0,0 +1,227 @@ +/****************************************************************************//** + * @file lcd.h + * @version V1.00 + * $Revision: 5 $ + * $Date: 15/06/26 1:30p $ + * @brief Nano100 series I2C driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __LCD_H__ +#define __LCD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +//#include + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_LCD_Driver LCD Driver + @{ +*/ + + +/** @addtogroup NANO100_LCD_EXPORTED_CONSTANTS LCD Exported Constants + @{ +*/ + +/// @cond +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/// @endcond + +#define LCD_FREQ_DIV32 ((uint32_t) 0x00000000) /*!< Clock source (32 or 10KHz) divide by 32 */ +#define LCD_FREQ_DIV64 ((uint32_t) 0x00000010) /*!< Clock source (32 or 10KHz) divide by 64 */ +#define LCD_FREQ_DIV96 ((uint32_t) 0x00000020) /*!< Clock source (32 or 10KHz) divide by 96 */ +#define LCD_FREQ_DIV128 ((uint32_t) 0x00000030) /*!< Clock source (32 or 10KHz) divide by 128 */ +#define LCD_FREQ_DIV192 ((uint32_t) 0x00000040) /*!< Clock source (32 or 10KHz) divide by 192 */ +#define LCD_FREQ_DIV256 ((uint32_t) 0x00000050) /*!< Clock source (32 or 10KHz) divide by 256 */ +#define LCD_FREQ_DIV384 ((uint32_t) 0x00000060) /*!< Clock source (32 or 10KHz) divide by 384 */ +#define LCD_FREQ_DIV512 ((uint32_t) 0x00000070) /*!< Clock source (32 or 10KHz) divide by 512 */ + +#define LCD_MUX_STATIC ((uint32_t) 0x00000000) /*!< Static multiplexing */ +#define LCD_MUX_ONE_SECOND ((uint32_t) 0x00000002) /*!< Duplex multiplexing */ +#define LCD_MUX_ONE_THIRD ((uint32_t) 0x00000004) /*!< Triplex multiplexing */ +#define LCD_MUX_ONE_FOURTH ((uint32_t) 0x00000006) /*!< Quadruplex multiplexing */ +#define LCD_MUX_ONE_FIFTH ((uint32_t) 0x00000008) /*!< 1/5 duty */ +#define LCD_MUX_ONE_SIXTH ((uint32_t) 0x0000000A) /*!< 1/6 duty */ + +#define LCD_BIAS_STATIC ((uint32_t) 0x00000000) /*!< Static bias */ +#define LCD_BIAS_HALF ((uint32_t) 0x00000002) /*!< 1/2 bias */ +#define LCD_BIAS_THIRD ((uint32_t) 0x00000004) /*!< 1/3 bias */ + +#define LCD_CPUMP_DIV1 ((uint32_t) 0x00000000) /*!< Clock source (32 or 10KHz) divide by 1 and is used by analog component */ +#define LCD_CPUMP_DIV2 ((uint32_t) 0x00000800) /*!< Clock source (32 or 10KHz) divide by 2 */ +#define LCD_CPUMP_DIV4 ((uint32_t) 0x00001000) /*!< Clock source (32 or 10KHz) divide by 4 */ +#define LCD_CPUMP_DIV8 ((uint32_t) 0x00001800) /*!< Clock source (32 or 10KHz) divide by 8 */ +#define LCD_CPUMP_DIV16 ((uint32_t) 0x00002000) /*!< Clock source (32 or 10KHz) divide by 16 */ +#define LCD_CPUMP_DIV32 ((uint32_t) 0x00002800) /*!< Clock source (32 or 10KHz) divide by 32 */ +#define LCD_CPUMP_DIV64 ((uint32_t) 0x00003000) /*!< Clock source (32 or 10KHz) divide by 64 */ +#define LCD_CPUMP_DIV128 ((uint32_t) 0x00003800) /*!< Clock source (32 or 10KHz) divide by 128 */ + +#define LCD_CPVOl_2_7V ((uint32_t) 0x00000000) /*!< Set charge pump voltage to 2.7 V */ +#define LCD_CPVOl_2_8V ((uint32_t) 0x00000100) /*!< Set charge pump voltage to 2.8 V */ +#define LCD_CPVOl_2_9V ((uint32_t) 0x00000200) /*!< Set charge pump voltage to 2.9 V */ +#define LCD_CPVOl_3V ((uint32_t) 0x00000300) /*!< Set charge pump voltage to 3 V */ +#define LCD_CPVOl_3_1V ((uint32_t) 0x00000400) /*!< Set charge pump voltage to 3.1 V */ +#define LCD_CPVOl_3_2V ((uint32_t) 0x00000500) /*!< Set charge pump voltage to 3.2 V */ +#define LCD_CPVOl_3_3V ((uint32_t) 0x00000600) /*!< Set charge pump voltage to 3.3 V */ +#define LCD_CPVOl_3_4V ((uint32_t) 0x00000700) /*!< Set charge pump voltage to 3.4 V */ + +#define LCD_FCPRESC_DIV1 ((uint32_t) 0x00000000) /*!< Set pre-scale divider value to 1 */ +#define LCD_FCPRESC_DIV2 ((uint32_t) 0x00000004) /*!< Set pre-scale divider value to 2 */ +#define LCD_FCPRESC_DIV4 ((uint32_t) 0x00000008) /*!< Set pre-scale divider value to 4 */ +#define LCD_FCPRESC_DIV8 ((uint32_t) 0x0000000C) /*!< Set pre-scale divider value to 8 */ + +#define LCD_FRAMECOUNT_INT ((uint32_t) 0x00000001) /*!< Indicate frame count interrupt */ +#define LCD_POWERDOWN_INT ((uint32_t) 0x00000002) /*!< Indicate power down interrupt */ +#define LCD_ALL_INT ((uint32_t) 0x00000003) /*!< Indicate frame count & power down interrupt */ + +#define ERR_LCD_CAL_BLINK_FAIL 0xFFFF0000 /*!< Specifies that overflow to calculate the blinking frequency */ + +/*@}*/ /* end of group NANO100_LCD_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_LCD_EXPORTED_STRUCTS LCD Exported Structs + @{ +*/ +typedef enum +{ + LCD_C_TYPE = 0, /*!< Select LCD C-Type */ + LCD_EXTERNAL_R_TYPE = 1, /*!< Select LCD External R-Type */ + LCD_INTERNAL_R_TYPE = 2, /*!< Select LCD Internal R-Type */ + LCD_EXTERNAL_C_TYPE = 3 /*!< Select LCD External C-Type */ +} LCD_PanelType; + +/*@}*/ /* end of group NANO100_LCD_EXPORTED_STRUCTS */ + + +/** @addtogroup NANO100_LCD_EXPORTED_FUNCTIONS LCD Exported Functions + @{ +*/ + +/** + * @brief Get LCD Power Down interrupt flag. + * + * @param None + * + * @return LCD Power Down interrupt Flag. + */ +#define LCD_GET_PD_INT_FLAG() ((LCD->FCSTS & LCD_FCSTS_PDSTS_Msk) >> LCD_FCSTS_PDSTS_Pos) + +/** + * @brief Clear LCD Power Down interrupt flag. + * + * @param None + * + * @return None. + */ +#define LCD_CLR_PD_INT_FLAG() (LCD->FCSTS = LCD_FCSTS_PDSTS_Msk) + +/** + * @brief Get LCD Frame Count interrupt flag. + * + * @param None + * + * @return LCD Frame Count interrupt Flag. + */ +#define LCD_GET_FRAME_CNT_INT_FLAG() ((LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) >> LCD_FCSTS_FCSTS_Pos) + +/** + * @brief Clear LCD Frame Count interrupt flag. + * + * @param None + * + * @return None. + */ +#define LCD_CLR_FRAME_CNT_INT_FLAG() (LCD->FCSTS = LCD_FCSTS_FCSTS_Msk) + +/** + * @brief Enable LCD Power Down Display function. + * + * @param None + * + * @return None. + */ +#define LCD_ENABLE_PD_DISPLAY() (LCD->CTL |= LCD_CTL_PDDISP_EN_Msk) + +/** + * @brief Disable LCD Power Down Display function. + * + * @param None + * + * @return None. + */ +#define LCD_DISABLE_PD_DISPLAY() (LCD->CTL &= ~LCD_CTL_PDDISP_EN_Msk) + +uint32_t LCD_EnableFrameCounter(uint32_t u32Count); +void LCD_DisableFrameCounter(void); +uint32_t LCD_EnableBlink(uint32_t u32ms); +void LCD_DisableBlink(void); +void LCD_EnableInt(uint32_t IntSrc); +void LCD_DisableInt(uint32_t IntSrc); +uint32_t LCD_Open(uint32_t u32DrivingType, uint32_t u32ComNum, uint32_t u32BiasLevel, uint32_t u32FramerateDiv, uint32_t u32DrivingVol); +void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag); +void LCD_SetAllPixels(uint32_t u32OnOff); +void LCD_Close(void); + +/** + * @brief Enable LCD controller + * + * @param None + * + * @return None + * + */ +static __INLINE void LCD_EnableDisplay(void) +{ + /* Enable LCD */ + LCD->CTL |= LCD_CTL_EN_Msk; +} + +/** + * @brief Disable LCD controller + * + * @param None + * + * @return None + * + */ +static __INLINE void LCD_DisableDisplay(void) +{ + /* Enable LCD */ + LCD->CTL &= ~LCD_CTL_EN_Msk; +} + + + +/*@}*/ /* end of group NANO100_LCD_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group NANO100_LCD_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __LCD_H__ */ + + + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + + diff --git a/program/Library/StdDriver/inc/pdma.h b/program/Library/StdDriver/inc/pdma.h new file mode 100644 index 0000000..a7559cb --- /dev/null +++ b/program/Library/StdDriver/inc/pdma.h @@ -0,0 +1,220 @@ +/**************************************************************************//** + * @file pdma.h + * @version V1.00 + * $Revision: 9 $ + * $Date: 15/06/10 4:52p $ + * @brief Nano100 series PDMA driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup NANO100_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Data Width Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_WIDTH_8 0x00080000UL /*!GCRISR)) + +/** + * @brief Get PDMA Channel Interrupt Status + * + * @param[in] u32Ch Selected DMA channel + * + * @return Interrupt Status + * + * @details This macro gets the channel interrupt status. + * \hideinitializer + */ +#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100)))) + +/** + * @brief Clear PDMA Channel Interrupt Flag + * + * @param[in] u32Ch Selected DMA channel + * @param[in] u32Mask Interrupt Mask + * + * @return None + * + * @details This macro clear the channel interrupt flag. + * \hideinitializer + */ +#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask)) + +/** + * @brief Check Channel Status + * + * @param[in] u32Ch The selected channel + * + * @return 0 = idle + * @return 1 = busy + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CSR +(uint32_t)((u32Ch-1)*0x100)))&PDMA_CSR_TRIG_EN_Msk)? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr)) + +/** + * @brief Set Destination Address + * + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr)) + +/** + * @brief Set Transfer Count + * + * @param[in] u32Ch The selected channel + * @param[in] u32Count Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) \ +do{\ + if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \ + *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 2); \ + else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \ + *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = (u32Count); \ + else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \ + *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 1); \ +}while(0) + +/** + * @brief Stop the channel + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk) + +void PDMA_Open(uint32_t u32Mask); +void PDMA_Close(void); +void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(uint32_t u32Ch); +void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask); + +/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_PDMA_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__PDMA_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/pwm.h b/program/Library/StdDriver/inc/pwm.h new file mode 100644 index 0000000..202dd30 --- /dev/null +++ b/program/Library/StdDriver/inc/pwm.h @@ -0,0 +1,205 @@ +/**************************************************************************//** + * @file pwm.h + * @version V1.00 + * $Revision: 12 $ + * $Date: 15/06/30 2:52p $ + * @brief NANO100 series PWM driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_PWM_Driver PWM Driver + @{ +*/ + +/** @addtogroup NANO100_PWM_EXPORTED_CONSTANTS PWM Exported Constants + @{ +*/ +#define PWM_CHANNEL_NUM (4) /*!< PWM channel number \hideinitializer */ +#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */ +#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */ +#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */ +#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */ +#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */ +#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */ +#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */ +#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */ +#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */ +#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */ +#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */ +#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */ +#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */ +#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */ +#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */ +#define PWM_RISING_LATCH_INT_ENABLE (1UL) /*!< PWM rising latch interrupt enable \hideinitializer */ +#define PWM_FALLING_LATCH_INT_ENABLE (2UL) /*!< PWM falling latch interrupt enable \hideinitializer */ +#define PWM_RISING_FALLING_LATCH_INT_ENABLE (3UL) /*!< PWM rising latch interrupt enable \hideinitializer */ +#define PWM_RISING_LATCH_INT_FLAG (2UL) /*!< PWM rising latch condition happened \hideinitializer */ +#define PWM_FALLING_LATCH_INT_FLAG (4UL) /*!< PWM falling latch condition happened \hideinitializer */ +#define PWM_RISING_FALLING_LATCH_INT_FLAG (6UL) /*!< PWM rising latch condition happened \hideinitializer */ +#define PWM_RISING_LATCH_PDMA_ENABLE (0x10UL) /*!< PWM rising latch PDMA enable \hideinitializer */ +#define PWM_FALLING_LATCH_PDMA_ENABLE (0x20UL) /*!< PWM falling latch PDMA enable \hideinitializer */ +#define PWM_RISING_FALLING_LATCH_PDMA_ENABLE (0x30UL) /*!< PWM rising and falling latch PDMA enable \hideinitializer */ +#define PWM_CAP_PDMA_RFORDER_R (0x1000UL) /*!< PWM captured data transferred by PDMA is rising latch first \hideinitializer */ +#define PWM_CAP_PDMA_RFORDER_F (0UL) /*!< PWM captured data transferred by PDMA is falling latch first \hideinitializer */ + +/*@}*/ /* end of group NANO100_PWM_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions + @{ +*/ + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask)\ +do { \ + uint8_t i; \ + (pwm)->CTL &= ~(PWM_CTL_CH0INV_Msk | PWM_CTL_CH1INV_Msk | PWM_CTL_CH2INV_Msk | PWM_CTL_CH3INV_Msk);\ + for (i = 0; i < PWM_CHANNEL_NUM; i++) { \ + if ( (u32ChannelMask) & (1 << i)) { \ + (pwm)->CTL |= (PWM_CTL_CH0INV_Msk << (i * 8)); \ + } \ + } \ + }while(0) + + +/** + * @brief This macro get captured rising data + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CRL0 + 2 * u32ChannelNum)) + +/** + * @brief This macro get captured falling data + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CFL0 + 2 * u32ChannelNum)) + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF + * @return None + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, + * channel 1 will also be affected. + * \hideinitializer + */ +#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \ + (pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8))) + +/** + * @brief This macro set the divider of the selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Divider Clock divider of specified channel. Valid values are + * - \ref PWM_CLK_DIV_1 + * - \ref PWM_CLK_DIV_2 + * - \ref PWM_CLK_DIV_4 + * - \ref PWM_CLK_DIV_8 + * - \ref PWM_CLK_DIV_16 + * @return None + * \hideinitializer + */ +#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \ + (pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u32Divider << (4 * u32ChannelNum))) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next PWM period + * \hideinitializer + */ +#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) \ +do { \ + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; \ + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= (u32CMR << PWM_DUTY_CM_Pos); \ +}while(0) + +/** + * @brief This macro set the period of the selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next PWM period + * @note PWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) \ +do { \ + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; \ + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u32CNR; \ +} while(0) + +uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32DutyCycle); +uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32UnitTimeNsec, + uint32_t u32CaptureEdge); +void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_PWM_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__PWM_H__ + +/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/rtc.h b/program/Library/StdDriver/inc/rtc.h new file mode 100644 index 0000000..0d0f59b --- /dev/null +++ b/program/Library/StdDriver/inc/rtc.h @@ -0,0 +1,254 @@ +/**************************************************************************//** + * @file rtc.h + * @version V1.00 + * $Revision: 7 $ + * $Date: 15/06/26 1:34p $ + * @brief Nano100 series RTC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_RTC_Driver RTC Driver + @{ +*/ + + +/** @addtogroup NANO100_RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ + + +#define RTC_INIT_KEY 0xA5EB1357 /*!< RTC Access Key */ +#define RTC_WRITE_KEY 0xA965 /*!< RTC Access Key */ + +#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time Out Value */ + +#define RTC_YEAR2000 2000 /*!< RTC Reference */ +#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference */ + +#define RTC_CLOCK_12 0 /*!< RTC 12 Hour */ +#define RTC_CLOCK_24 1 /*!< RTC 24 Hour */ + +#define RTC_AM 1 /*!< RTC AM */ +#define RTC_PM 2 /*!< RTC PM */ + +#define RTC_TICK_1_SEC ((uint32_t) 0x00000000) /*!< Time tick is 1 second */ +#define RTC_TICK_1_2_SEC ((uint32_t) 0x00000001) /*!< Time tick is 1/2 second */ +#define RTC_TICK_1_4_SEC ((uint32_t) 0x00000002) /*!< Time tick is 1/4 second */ +#define RTC_TICK_1_8_SEC ((uint32_t) 0x00000003) /*!< Time tick is 1/8 second */ +#define RTC_TICK_1_16_SEC ((uint32_t) 0x00000004) /*!< Time tick is 1/16 second */ +#define RTC_TICK_1_32_SEC ((uint32_t) 0x00000005) /*!< Time tick is 1/32 second */ +#define RTC_TICK_1_64_SEC ((uint32_t) 0x00000006) /*!< Time tick is 1/64 second */ +#define RTC_TICK_1_128_SEC ((uint32_t) 0x00000007) /*!< Time tick is 1/128 second */ + +#define RTC_SUNDAY ((uint32_t) 0x00000000) /*!< Day of week is sunday */ +#define RTC_MONDAY ((uint32_t) 0x00000001) /*!< Day of week is monday */ +#define RTC_TUESDAY ((uint32_t) 0x00000002) /*!< Day of week is tuesday */ +#define RTC_WEDNESDAY ((uint32_t) 0x00000003) /*!< Day of week is wednesday */ +#define RTC_THURSDAY ((uint32_t) 0x00000004) /*!< Day of week is thursday */ +#define RTC_FRIDAY ((uint32_t) 0x00000005) /*!< Day of week is friday */ +#define RTC_SATURDAY ((uint32_t) 0x00000006) /*!< Day of week is saturday */ + + +#define RTC_SNOOPER_RISING 0 /*!< Snooper Active Rising Edge */ +#define RTC_SNOOPER_FALLING 1 /*!< Snooper Active Falling Edge */ + + +/*@}*/ /* end of group NANO100_RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ + +/** + * @brief RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group NANO100_RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup NANO100_RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + + +/** + * @brief Read spare register + * + * @param[in] u32RegNum The spare register number(0~23) + * + * @return Spare register content. + * + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[u32RegNum]) + +/** + * @brief Write spare register + * + * @param[in] u32RegNum The spare register number(0~23) + * @param[in] u32RegValue The spare register value + * + * @return None + * + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[u32RegNum] = u32RegValue) + +/** + * @brief According to current time, return this year is leap year or not + * + * @param None + * + * @return 0 = This year is not a leap year. \n + * 1 = This year is a leap year. + * + */ +#define RTC_IS_LEAP_YEAR() ((RTC->LIR & (RTC_LIR_LIR_Msk))?1:0) + +/** + * @brief Clear alarm interrupt status. + * + * @param None + * + * @return None + * + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->RIIR = RTC_RIIR_AIF_Msk) + +/** + * @brief Clear tick interrupt status. + * + * @param None + * + * @return None + * + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->RIIR = RTC_RIIR_TIF_Msk) + +/** + * @brief Clear tamper detect pin status. + * + * @param[in] u32PinNum tamper detect pin number. + * + * @return None + * + */ +#define RTC_CLEAR_TAMPER_FLAG(u32PinNum) (RTC->RIIR = RTC_RIIR_SNOOPIF_Msk) + +/** + * @brief Get alarm interrupt status. + * + * @param None + * + * @return Alarm interrupt status + * + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->RIIR & RTC_RIIR_AIF_Msk) >> RTC_RIIR_AIF_Pos) + +/** + * @brief Get alarm interrupt status. + * + * @param None + * + * @return Alarm interrupt status + * + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->RIIR & RTC_RIIR_TIF_Msk) >> RTC_RIIR_TIF_Pos) + +/** + * @brief Get tamper detect pin status. + * + * @param None + * + * @return 1: Snooper Pin Event Detected \n + * 0: Snooper Pin Event Never Detected + * + */ +#define RTC_GET_TAMPER_FLAG() ( (RTC->RIIR & RTC_RIIR_SNOOPIF_Msk) >> RTC_RIIR_SNOOPIF_Pos) + +/** + * @brief Enable Timer tick wakeup function. + * + * @param None + * + * @return None + * + */ +#define RTC_ENABLE_TICK_WAKEUP() (RTC->TTR |= RTC_TTR_TWKE_Msk); + +/** + * @brief Disable Timer tick wakeup function. + * + * @param None + * + * @return None + * + */ +#define RTC_DISABLE_TICK_WAKEUP() (RTC->TTR &= ~RTC_TTR_TWKE_Msk); + + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX100); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +uint32_t RTC_GetDayOfWeek(void); +void RTC_DisableTamperDetection(void); +void RTC_EnableTamperDetection(uint32_t u32PinCondition); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); + + + +/*@}*/ /* end of group NANO100_RTC_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group NANO100_RTC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + + + diff --git a/program/Library/StdDriver/inc/sc.h b/program/Library/StdDriver/inc/sc.h new file mode 100644 index 0000000..fb24473 --- /dev/null +++ b/program/Library/StdDriver/inc/sc.h @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file sc.h + * @version V1.00 + * $Revision: 7 $ + * $Date: 15/07/31 7:26p $ + * @brief Nano100 series Smartcard (SC) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013~2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SC_Driver SC Driver + @{ +*/ + +/** @addtogroup NANO100_SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers */ +#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high */ +#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low */ +#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status */ +#define SC_CLK_ON 1 /*!< Smartcard clock on */ +#define SC_CLK_OFF 0 /*!< Smartcard clock off */ + +#define SC_TMR_MODE_0 (0ul << SC_TMR0_MODE_Pos) /*!IER |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * @param[in] sc Base address of smartcard module + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_IER_ACON_ERR_IE_Msk + * - \ref SC_IER_RTMR_IE_Msk + * - \ref SC_IER_INIT_IE_Msk + * - \ref SC_IER_CD_IE_Msk + * - \ref SC_IER_BGT_IE_Msk + * - \ref SC_IER_TMR2_IE_Msk + * - \ref SC_IER_TMR1_IE_Msk + * - \ref SC_IER_TMR0_IE_Msk + * - \ref SC_IER_TERR_IE_Msk + * - \ref SC_IER_TBE_IE_Msk + * - \ref SC_IER_RDA_IE_Msk + * @return None + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + uint32_t reg = (sc)->PINCSR;\ + if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\ + ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\ + reg &= ~SC_PINCSR_POW_EN_Msk;\ + else\ + reg |= SC_PINCSR_POW_EN_Msk;\ + if(u32State)\ + (sc)->PINCSR = reg | SC_PINCSR_POW_EN_Msk;\ + else\ + (sc)->PINCSR = reg & ~SC_PINCSR_POW_EN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * @param[in] sc Base address of smartcard module + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF + * @return None + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + uint32_t reg = (sc)->PINCSR;\ + if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\ + ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\ + reg &= ~SC_PINCSR_POW_EN_Msk;\ + else\ + reg |= SC_PINCSR_POW_EN_Msk;\ + if(u32OnOff)\ + (sc)->PINCSR = reg | SC_PINCSR_CLK_KEEP_Msk;\ + else\ + (sc)->PINCSR = reg & ~SC_PINCSR_CLK_KEEP_Msk;\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + uint32_t reg = (sc)->PINCSR;\ + if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\ + ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\ + reg &= ~SC_PINCSR_POW_EN_Msk;\ + else\ + reg |= SC_PINCSR_POW_EN_Msk;\ + if(u32State)\ + (sc)->PINCSR = reg | SC_PINCSR_SC_DATA_O_Msk;\ + else\ + (sc)->PINCSR = reg & ~SC_PINCSR_SC_DATA_O_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + uint32_t reg = (sc)->PINCSR;\ + if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\ + ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\ + reg &= ~SC_PINCSR_POW_EN_Msk;\ + else\ + reg |= SC_PINCSR_POW_EN_Msk;\ + if(u32State)\ + (sc)->PINCSR = reg | SC_PINCSR_SC_RST_Msk;\ + else\ + (sc)->PINCSR = reg & ~SC_PINCSR_SC_RST_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * @param[in] sc Base address of smartcard module + * @return[in] One byte read from receive FIFO + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->RBR)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * @param[in] sc Base address of smartcard module + * @param[in] u8Data Data to write to transmit FIFO + * @return None + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->THR = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * @param[in] sc Base address of smartcard module + * @param[in] u32Len Stop bit length, ether 1 or 2. + * @return None + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_SLEN_Msk) | (u32Len == 1 ? SC_CTL_SLEN_Msk : 0)) + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry + * @return None + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + // Retry count must set while enable bit disabled, so disable it first + sc->CTL &= ~(SC_CTL_TX_ERETRY_Msk | SC_CTL_TX_ERETRY_EN_Msk); + + if(u32Count != 0) + { + sc->CTL |= ((u32Count - 1) << SC_CTL_TX_ERETRY_Pos) | SC_CTL_TX_ERETRY_EN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry + * @return None + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + // Retry count must set while enable bit disabled, so disable it first + sc->CTL &= ~(SC_CTL_RX_ERETRY_Msk | SC_CTL_RX_ERETRY_EN_Msk); + + if(u32Count != 0) + { + sc->CTL |= ((u32Count - 1) << SC_CTL_RX_ERETRY_Pos) | SC_CTL_RX_ERETRY_EN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); + + +/*@}*/ /* end of group NANO100_SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__SC_H__ + +/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/scuart.h b/program/Library/StdDriver/inc/scuart.h new file mode 100644 index 0000000..72f0ad9 --- /dev/null +++ b/program/Library/StdDriver/inc/scuart.h @@ -0,0 +1,261 @@ +/**************************************************************************//** + * @file sc.h + * @version V1.00 + * $Revision: 3 $ + * $Date: 14/05/20 7:57p $ + * @brief Nano100 series Smartcard UART mode (SCUART) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup NANO100_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 5 bits */ +#define SCUART_CHAR_LEN_6 (0x2ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 6 bits */ +#define SCUART_CHAR_LEN_7 (0x1ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 7 bits */ +#define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits */ + +#define SCUART_PARITY_NONE (SC_UACTL_PBDIS_Msk) /*!< Set SCUART transfer with no parity */ +#define SCUART_PARITY_ODD (SC_UACTL_OPE_Msk) /*!< Set SCUART transfer with odd parity */ +#define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity */ + +#define SCUART_STOP_BIT_1 (SC_CTL_SLEN_Msk) /*!< Set SCUART transfer with one stop bit */ +#define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits */ + + +/*@}*/ /* end of group NANO100_SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * @param[in] sc The base address of smartcard module. + * @param[in] u8Data Data byte to transmit + * @return None + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->THR = (u8Data)) + +/** + * @brief Get TX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_TRSR_TX_EMPTY_F_Msk Transmit FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_TX_EMPTY_F_Msk) + +/** + * @brief Get TX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_TRSR_TX_FULL_F_Msk Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->TRSR & SC_TRSR_TX_FULL_F_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * @param[in] sc The base address of smartcard module + * @return None + * @note This Macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->TRSR & SC_TRSR_TX_ATV_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) ((sc)->TRSR & SC_TRSR_TX_FULL_F_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * @param[in] sc The base address of smartcard module + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_TX_ATV_Msk ? 0 : 1) + + +/* RX Macros */ + +/** + * @brief Read Rx data register + * @param[in] sc The base address of smartcard module + * @return The oldest data byte in RX FIFO + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->RBR) + +/** + * @brief Get RX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_TRSR_RX_EMPTY_F_Msk Receive FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_RX_EMPTY_F_Msk) + + +/** + * @brief Get RX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_TRSR_TX_FULL_F_Msk Receive FIFO is full + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->TRSR & SC_TRSR_RX_FULL_F_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) ((sc)->ISR & SC_ISR_RDA_IS_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) ((sc)->TRSR & SC_TRSR_RX_FULL_F_Msk ? 1 : 0) + +/* Interrupt Macros */ + +/** + * @brief Enable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits + * - \ref SC_IER_RTMR_IE_Msk + * - \ref SC_IER_TERR_IE_Msk + * - \ref SC_IER_TBE_IE_Msk + * - \ref SC_IER_RDA_IE_Msk + * @return None + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->IER |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits + * - \ref SC_IER_RTMR_IE_Msk + * - \ref SC_IER_TERR_IE_Msk + * - \ref SC_IER_TBE_IE_Msk + * - \ref SC_IER_RDA_IE_Msk + * @return None + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_ISR_RTMR_IS_Msk + * - \ref SC_ISR_TERR_IS_Msk + * - \ref SC_ISR_TBE_IS_Msk + * - \ref SC_ISR_RDA_IS_Msk + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->ISR & u32Type ? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values + * - \ref SC_ISR_RTMR_IS_Msk + * - \ref SC_ISR_TERR_IS_Msk + * - \ref SC_ISR_TBE_IS_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->ISR = u32Type) + +/** + * @brief Get receive error flag/status + * @param[in] sc The base address of smartcard module + * @return Current receive error status, could one of following errors: + * @retval SC_TRSR_RX_EPA_F_Msk Parity error + * @retval SC_TRSR_RX_EFR_F_Msk Frame error + * @retval SC_TRSR_RX_EBR_F_Msk Break error + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->TRSR & (SC_TRSR_RX_EPA_F_Msk | SC_TRSR_RX_EFR_F_Msk | SC_TRSR_RX_EBR_F_Msk)) + +/** + * @brief Clear specified receive error flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_TRSR_RX_EPA_F_Msk + * - \ref SC_TRSR_RX_EFR_F_Msk + * - \ref SC_TRSR_RX_EBR_F_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->TRSR = u32Mask) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes); + +/*@}*/ /* end of group NANO100_SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SCUART_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__SCUART_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/spi.h b/program/Library/StdDriver/inc/spi.h new file mode 100644 index 0000000..c85fc94 --- /dev/null +++ b/program/Library/StdDriver/inc/spi.h @@ -0,0 +1,387 @@ +/****************************************************************************//** + * @file spi.h + * @version V1.00 + * $Revision: 8 $ + * $Date: 15/06/08 5:03p $ + * @brief NANO100 series SPI driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup NANO100_SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */ +#define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */ +#define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */ +#define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define SPI_MASTER (0x0) /*!< Set as master */ + +#define SPI_SS0 (0x1) /*!< Set SS0 */ +#define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS0 active high */ +#define SPI_SS0_ACTIVE_LOW (0x0) /*!< SS0 active low */ + +#define SPI_SS1 (0x2) /*!< Set SS1 */ +#define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS1 active high */ +#define SPI_SS1_ACTIVE_LOW (0x0) /*!< SS1 active low */ + +#define SPI_IE_MASK (0x01) /*!< Interrupt enable mask */ +#define SPI_SSTA_INTEN_MASK (0x04) /*!< Slave 3-Wire mode start interrupt enable mask */ +#define SPI_FIFO_TX_INTEN_MASK (0x08) /*!< FIFO TX interrupt mask */ +#define SPI_FIFO_RX_INTEN_MASK (0x10) /*!< FIFO RX interrupt mask */ +#define SPI_FIFO_RXOVR_INTEN_MASK (0x20) /*!< FIFO RX overrun interrupt mask */ +#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) /*!< FIFO timeout interrupt mask */ + + +/*@}*/ /* end of group NANO100_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +/** + * @brief Abort the current transfer in slave 3-wire mode. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSR |= SPI_SSR_SLV_ABORT_Msk ) + +/** + * @brief Clear the slave 3-wire mode start interrupt flag. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk ) + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_INTSTS_Msk ) + +/** + * @brief Disable slave 3-wire mode. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSR &= ~SPI_SSR_NOSLVSEL_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSR |= SPI_SSR_NOSLVSEL_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi is the base address of SPI module. + * @return The count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_CNT_Msk) >> SPI_STATUS_RX_FIFO_CNT_Pos) & 0xf ) + +/** + * @brief Get the Rx FIFO empty flag. + * @param[in] spi is the base address of SPI module. + * @return Rx FIFO flag + * @retval 0 Rx FIFO is not empty + * @retval 1 Rx FIFO is empty + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0) + +/** + * @brief Get the Tx FIFO empty flag. + * @param[in] spi is the base address of SPI module. + * @return Tx FIFO flag + * @retval 0 Tx FIFO is not empty + * @retval 1 Tx FIFO is empty + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0) + +/** + * @brief Get the Tx FIFO full flag. + * @param[in] spi is the base address of SPI module. + * @return Tx FIFO flag + * @retval 0 Tx FIFO is not full + * @retval 1 Tx FIFO is full + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0) + +/** + * @brief Get the datum read from RX0 FIFO. + * @param[in] spi is the base address of SPI module. + * @return Data in Rx0 register. + * \hideinitializer + */ +#define SPI_READ_RX0(spi) ( (spi)->RX0 ) + +/** + * @brief Get the datum read from RX1 FIFO. + * @param[in] spi is the base address of SPI module. + * @return Data in Rx1 register. + */ +#define SPI_READ_RX1(spi) ( (spi)->RX1 ) + +/** + * @brief Write datum to TX0 register. + * @param[in] spi is the base address of SPI module. + * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus. + * @return none + * \hideinitializer + */ +#define SPI_WRITE_TX0(spi, u32TxData) ( (spi)->TX0 = u32TxData ) + +/** + * @brief Write datum to TX1 register. + * @param[in] spi is the base address of SPI module. + * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus. + * @return none + * \hideinitializer + */ +#define SPI_WRITE_TX1(spi, u32TxData) ( (spi)->TX1 = u32TxData ) + +/** + * @brief Set SPIn_SS0 pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define SPI_SET_SS0_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0))) + +/** + * @brief Set SPIn_SS0 pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define SPI_SET_SS0_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)) | SPI_SS0) + +/** + * @brief Set SPIn_SS1 pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define SPI_SET_SS1_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1))) + +/** + * @brief Set SPIn_SS1 pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define SPI_SET_SS1_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)) | SPI_SS1) + +/** + * @brief Set SPIn_SS0, SPIn_SS1 pin to high or low state. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] ss0 0 = Set SPIn_SS0 to low. 1 = Set SPIn_SS0 to high. + * @param[in] ss1 0 = Set SPIn_SS1 to low. 1 = Set SPIn_SS1 to high. + * @return None. + * @details Disable automatic slave selection function and set SPIn_SS0/SPIn_SS1 pin to specified high/low state. + * Only available in Master mode. + */ +#define SPI_SET_SS_LEVEL(spi, ss0, ss1) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SSR_SSR_Msk)) | (((ss1)^1) << 1) | ((ss0)^1)) + +/** + * @brief Enable byte reorder function. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk ) + +/** + * @brief Disable byte reorder function. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi is the base address of SPI module. + * @param[in] u32SuspCycle decides the length of suspend interval. + * @return none + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CTL_SP_CYCLE_Pos) ) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk ) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi is the base address of SPI module. + * @param[in] u32Width is the data width (from 8-32 bits). + * @return none + * \hideinitializer + */ +static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width) +{ + if(u32Width == 32) + u32Width = 0; + + spi->CTL = (spi->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (u32Width << SPI_CTL_TX_BIT_LEN_Pos); +} + +/** + * @brief Get the SPI busy state. + * @param[in] spi is the base address of SPI module. + * @return SPI busy status + * @retval 0 SPI module is not busy + * @retval 1 SPI module is busy + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_GO_BUSY_Msk) == SPI_CTL_GO_BUSY_Msk ? 1:0) + +/** + * @brief Set the GO_BUSY bit to trigger SPI transfer. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_GO_BUSY_Msk ) + +/** + * @brief Disable SPI Dual IO function. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUAL_IO_EN_Msk ) + +/** + * @brief Enable Dual IO function and set SPI Dual IO direction to input. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DUAL_IO_DIR_Msk) | SPI_CTL_DUAL_IO_EN_Msk ) + +/** + * @brief Enable Dual IO function and set SPI Dual IO direction to output. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= (SPI_CTL_DUAL_IO_DIR_Msk | SPI_CTL_DUAL_IO_EN_Msk) ) + +/** + * @brief Trigger RX PDMA transfer. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_RX_DMA_EN_Msk ) + +/** + * @brief Trigger TX PDMA transfer. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_TX_DMA_EN_Msk ) + +/** + * @brief Enable 2-bit transfer mode. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOB_Msk ) + +/** + * @brief Disable 2-bit transfer mode. + * @param[in] spi is the base address of SPI module. + * @return none + * \hideinitializer + */ +#define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOB_Msk ) + +/** + * @brief Get the status register value. + * @param[in] spi is the base address of SPI module. + * @return status value. + * \hideinitializer + */ +#define SPI_GET_STATUS(spi) ( (spi)->STATUS ) + +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void SPI_DisableFIFO(SPI_T *spi); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_EnableWakeup(SPI_T *spi); +void SPI_DisableWakeup(SPI_T *spi); +/*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SPI_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__SPI_H__ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/sys.h b/program/Library/StdDriver/inc/sys.h new file mode 100644 index 0000000..c3368c9 --- /dev/null +++ b/program/Library/StdDriver/inc/sys.h @@ -0,0 +1,874 @@ +/**************************************************************************//** +* @file sys.h +* @version V1.00 +* $Revision: 17 $ +* $Date: 15/06/24 1:11p $ +* @brief Nano100 Series system control header file. +* +* @note + * SPDX-License-Identifier: Apache-2.0 +* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SYS_H__ +#define __SYS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup NANO100_SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CHIP_RST ((0x0<<24) | SYS_IPRST_CTL1_CHIP_RST_Pos ) /*!< CHIP reset is one of the SYS_ResetModule parameter */ +#define CPU_RST ((0x0<<24) | SYS_IPRST_CTL1_CPU_RST_Pos ) /*!< CPU reset is one of the SYS_ResetModule parameter */ +#define DMA_RST ((0x0<<24) | SYS_IPRST_CTL1_DMA_RST_Pos ) /*!< DMA reset is one of the SYS_ResetModule parameter */ +#define EBI_RST ((0x0<<24) | SYS_IPRST_CTL1_EBI_RST_Pos ) /*!< EBI reset is one of the SYS_ResetModule parameter */ +#define SC1_RST ((0x4<<24) | SYS_IPRST_CTL2_SC1_RST_Pos ) /*!< SmartCard1 reset is one of the SYS_ResetModule parameter */ +#define SC0_RST ((0x4<<24) | SYS_IPRST_CTL2_SC0_RST_Pos ) /*!< SmartCard0 reset is one of the SYS_ResetModule parameter */ +#define I2S_RST ((0x4<<24) | SYS_IPRST_CTL2_I2S_RST_Pos ) /*!< I2S reset is one of the SYS_ResetModule parameter */ +#define ADC_RST ((0x4<<24) | SYS_IPRST_CTL2_ADC_RST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */ +#define USBD_RST ((0x4<<24) | SYS_IPRST_CTL2_USBD_RST_Pos ) /*!< USBD reset is one of the SYS_ResetModule parameter */ +#define DAC_RST ((0x4<<24) | SYS_IPRST_CTL2_DAC_RST_Pos ) /*!< DAC reset is one of the SYS_ResetModule parameter */ +#define PWM1_RST ((0x4<<24) | SYS_IPRST_CTL2_PWM1_RST_Pos ) /*!< PWM1 reset is one of the SYS_ResetModule parameter */ +#define PWM0_RST ((0x4<<24) | SYS_IPRST_CTL2_PWM0_RST_Pos ) /*!< PWM0 reset is one of the SYS_ResetModule parameter */ +#define UART1_RST ((0x4<<24) | SYS_IPRST_CTL2_UART1_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define UART0_RST ((0x4<<24) | SYS_IPRST_CTL2_UART0_RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */ +#define SPI2_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI2_RST_Pos ) /*!< SPI2 reset is one of the SYS_ResetModule parameter */ +#define SPI1_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI1_RST_Pos ) /*!< SPI1 reset is one of the SYS_ResetModule parameter */ +#define SPI0_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI0_RST_Pos ) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ +#define I2C1_RST ((0x4<<24) | SYS_IPRST_CTL2_I2C1_RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ +#define I2C0_RST ((0x4<<24) | SYS_IPRST_CTL2_I2C0_RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ +#define TMR3_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR3_RST_Pos ) /*!< Timer3 reset is one of the SYS_ResetModule parameter */ +#define TMR2_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR2_RST_Pos ) /*!< Timer2 reset is one of the SYS_ResetModule parameter */ +#define TMR1_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR1_RST_Pos ) /*!< Timer1 reset is one of the SYS_ResetModule parameter */ +#define TMR0_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR0_RST_Pos ) /*!< Timer0 reset is one of the SYS_ResetModule parameter */ +#define GPIO_RST ((0x4<<24) | SYS_IPRST_CTL2_GPIO_RST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Multi-Function constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ + +/********************* Bit definition of VREFCTL register **********************/ +#define SYS_VREFCTL_BGP_EN SYS_VREFCTL_BGP_EN_Msk /*!BODSTS |= SYS_BODSTS_BOD_INT_Msk) + +/** + * @brief Disable Brown-out 2.5V detector function + * @param None + * @return None + * @details This macro disable Brown-out 2.5V detector function. + */ +#define SYS_DISABLE_BOD25() (SYS->BODCTL &= ~SYS_BODCTL_BOD25_EN_Msk) + +/** + * @brief Enable Brown-out 2.5V detector function + * @param None + * @return None + * @details This macro enable Brown-out 2.5V detector function. + */ +#define SYS_ENABLE_BOD25() (SYS->BODCTL |= SYS_BODCTL_BOD25_EN_Msk) + +/** + * @brief Disable Brown-out 2.0V detector function + * @param None + * @return None + * @details This macro disable Brown-out 2.0V detector function. + */ +#define SYS_DISABLE_BOD20() (SYS->BODCTL &= ~SYS_BODCTL_BOD20_EN_Msk) + +/** + * @brief Enable Brown-out 2.0V detector function + * @param None + * @return None + * @details This macro enable Brown-out 2.0V detector function. + */ +#define SYS_ENABLE_BOD20() (SYS->BODCTL |= SYS_BODCTL_BOD20_EN_Msk) + +/** + * @brief Disable Brown-out 1.7V detector function + * @param None + * @return None + * @details This macro disable Brown-out 1.7V detector function. + */ +#define SYS_DISABLE_BOD17() (SYS->BODCTL &= ~SYS_BODCTL_BOD17_EN_Msk) + +/** + * @brief Enable Brown-out 1.7V detector function + * @param None + * @return None + * @details This macro enable Brown-out 1.7V detector function. + */ +#define SYS_ENABLE_BOD17() (SYS->BODCTL |= SYS_BODCTL_BOD17_EN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODSTS & SYS_BODSTS_BOD_INT_Msk) + +/** + * @brief Get Brown-out 2.5V detector status + * @param None + * @retval 0 System voltage is higher than 2.5V setting or BOD_EN is 0. + * @retval >=1 System voltage is lower than 2.5V setting. + * @details This macro get Brown-out detector output status. + * If the BOD_EN is 0, this function always return 0. + */ +#define SYS_GET_BOD25_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD25_drop_Msk) + +/** + * @brief Get Brown-out 2.0V detector status + * @param None + * @retval 0 System voltage is higher than 2.0V setting or BOD_EN is 0. + * @retval >=1 System voltage is lower than 2.0V setting. + * @details This macro get Brown-out detector output status. + * If the BOD_EN is 0, this function always return 0. + */ +#define SYS_GET_BOD20_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD20_drop_Msk) + +/** + * @brief Get Brown-out 1.7V detector status + * @param None + * @retval 0 System voltage is higher than 1.7V setting or BOD_EN is 0. + * @retval >=1 System voltage is lower than 1.7V setting. + * @details This macro get Brown-out detector output status. + * If the BOD_EN is 0, this function always return 0. + */ +#define SYS_GET_BOD17_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD17_drop_Msk) + +/** + * @brief Disable Brown-out 2.5V detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + */ +#define SYS_DISABLE_BOD25_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD25_RST_EN_Msk) + +/** + * @brief Enable Brown-out 2.5V detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + */ +#define SYS_ENABLE_BOD25_RST() (SYS->BODCTL |= SYS_BODCTL_BOD25_RST_EN_Msk) + +/** + * @brief Disable Brown-out 2.0V detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + */ +#define SYS_DISABLE_BOD20_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD20_RST_EN_Msk) + +/** + * @brief Enable Brown-out 2.0V detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + */ +#define SYS_ENABLE_BOD20_RST() (SYS->BODCTL |= SYS_BODCTL_BOD20_RST_EN_Msk) + +/** + * @brief Disable Brown-out 1.7V detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + */ +#define SYS_DISABLE_BOD17_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD17_RST_EN_Msk) + +/** + * @brief Enable Brown-out 1.7V detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + */ +#define SYS_ENABLE_BOD17_RST() (SYS->BODCTL |= SYS_BODCTL_BOD17_RST_EN_Msk) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + */ +#define SYS_IS_BOD_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_BOD_Msk) + + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + */ +#define SYS_IS_CPU_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_CPU_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + */ +#define SYS_IS_POR_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_POR_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + */ +#define SYS_IS_RSTPIN_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_PAD_Msk) + + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + */ +#define SYS_IS_SYSTEM_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_SYS_Msk) + + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + */ +#define SYS_IS_WDT_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_WDT_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + */ +#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + */ +#define SYS_ENABLE_POR() (SYS->PORCTL = 0) + + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including: + * - \ref SYS_RST_SRC_RSTS_POR_Msk + * - \ref SYS_RST_SRC_RSTS_PAD_Msk + * - \ref SYS_RST_SRC_RSTS_WDT_Msk + * - \ref SYS_RST_SRC_RSTS_BOD_Msk + * - \ref SYS_RST_SRC_RSTS_SYS_Msk + * - \ref SYS_RST_SRC_RSTS_CPU_Msk + * @return None + * @details This macro clear reset source flag. + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RST_SRC = u32RstSrc ) + +/** + * @brief Get HIRC trim status + * @param None + * @retval BIT0 HIRC Frequency Lock + * @retval BIT1 Trim Failure Interrupt + * @retval BIT2 LXT Clock error + * @details This macro get HIRC trim interrupt status register. + */ +#define SYS_GET_IRCTRIM_INT_FLAG() (SYS->IRCTRIMINT) + +/** + * @brief Clear HIRC trim flag + * @param[in] u32IRCTrimFlg is HIRC trim flags. Including: + * - \ref SYS_IRCTRIMINT_FAIL_INT + * - \ref SYS_IRCTRIMINT_32KERR_INT + * @return None + * @details This macro clear HIRC trim flag. + */ +#define SYS_CLEAR_IRCTRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRCTRIMINT = u32IRCTrimFlg ) + + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + while(SYS->RegLockAddr != SYS_RegLockAddr_RegUnLock_Msk) + { + SYS->RegLockAddr = 0x59; + SYS->RegLockAddr = 0x16; + SYS->RegLockAddr = 0x88; + } +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->RegLockAddr = 0; +} + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_EnableIRCTrim(uint32_t u32TrimSel,uint32_t u32TrimEnInt); +void SYS_DisableIRCTrim(void); +/*@}*/ /* end of group NANO100_SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SYS_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__SYS_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + + diff --git a/program/Library/StdDriver/inc/timer.h b/program/Library/StdDriver/inc/timer.h new file mode 100644 index 0000000..615c958 --- /dev/null +++ b/program/Library/StdDriver/inc/timer.h @@ -0,0 +1,326 @@ +/**************************************************************************//** + * @file timer.h + * @version V1.00 + * $Revision: 6 $ + * $Date: 14/08/29 7:56p $ + * @brief Nano100 series TIMER driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup NANO100_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ + +#define TIMER_ONESHOT_MODE (0UL) /*!< Timer working in one shot mode */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in periodic mode */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in toggle mode */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in continuous mode */ + +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL) /*!< Free counting mode */ +#define TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_CTL_TCAP_CNT_MODE_Msk) /*!< Trigger counting mode */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_CTL_TCAP_MODE_Msk) /*!< Counter reset mode */ + +#define TIMER_CAPTURE_FALLING_EDGE (0UL) /*!< Falling edge trigger timer capture */ +#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Rising edge trigger timer capture */ +#define TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Falling edge then rising edge trigger timer capture */ +#define TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Rising edge then falling edge trigger timer capture */ + +#define TIMER_COUNTER_RISING_EDGE (TIMER_CTL_EVENT_EDGE_Msk) /*!< Counter increase on rising edge */ +#define TIMER_COUNTER_FALLING_EDGE (0UL) /*!< Counter increase on falling edge */ + +#define TIMER_TIMEOUT_TRIGGER (0UL) /*!< Timer timeout trigger other modules */ +#define TIMER_CAPTURE_TRIGGER (TIMER_CTL_CAP_TRG_EN_Msk) /*!< Timer capture trigger other modules */ + +/*@}*/ /* end of group NANO100_TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief This macro is used to set new Timer compared value + * @param[in] timer The base address of Timer module + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF + * @return None + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMPR = (u32Value)) + +/** + * @brief This macro is used to set new Timer prescale value + * @param[in] timer The base address of Timer module + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF + * @return None + * @note Clock input is divided by (prescale + 1) before it is fed into timer + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->PRECNT = (u32Value)) + +/** + * @brief This macro is used to check if specify Timer is inactive or active + * @return timer is activate or inactivate + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_TMR_ACT_Msk ? 1 : 0) + + +/** + * @brief This function is used to start Timer counting + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_TMR_EN_Msk; +} + +/** + * @brief This function is used to stop Timer counting + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_TMR_EN_Msk; +} + +/** + * @brief This function is used to enable the Timer wake-up function + * @param[in] timer The base address of Timer module + * @return None + * @note To wake the system from power down mode, timer clock source must be ether LXT or LIRC + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WAKE_EN_Msk; +} + +/** + * @brief This function is used to disable the Timer wake-up function + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WAKE_EN_Msk; +} + + +/** + * @brief This function is used to enable the capture pin detection de-bounce function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_TCAP_DEB_EN_Msk; +} + +/** + * @brief This function is used to disable the capture pin detection de-bounce function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_TCAP_DEB_EN_Msk; +} + + +/** + * @brief This function is used to enable the counter pin detection de-bounce function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_EVNT_DEB_EN_Msk; +} + +/** + * @brief This function is used to disable the counter pin detection de-bounce function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EVNT_DEB_EN_Msk; +} + +/** + * @brief This function is used to enable the Timer time-out interrupt function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->IER |= TIMER_IER_TMR_IE_Msk; +} + +/** + * @brief This function is used to disable the Timer time-out interrupt function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->IER &= ~TIMER_IER_TMR_IE_Msk; +} + +/** + * @brief This function is used to enable the Timer capture trigger interrupt function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->IER |= TIMER_IER_TCAP_IE_Msk; +} + +/** + * @brief This function is used to disable the Timer capture trigger interrupt function. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->IER &= ~TIMER_IER_TCAP_IE_Msk; +} + +/** + * @brief This function indicates Timer time-out interrupt occurred or not. + * @param[in] timer The base address of Timer module + * @return Timer time-out interrupt occurred or not + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return(timer->ISR & TIMER_ISR_TMR_IS_Msk ? 1 : 0); +} + +/** + * @brief This function clears the Timer time-out interrupt flag. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->ISR = TIMER_ISR_TMR_IS_Msk; +} + +/** + * @brief This function indicates Timer capture interrupt occurred or not. + * @param[in] timer The base address of Timer module + * @return Timer capture interrupt occurred or not + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return(timer->ISR & TIMER_ISR_TCAP_IS_Msk ? 1 : 0); +} + +/** + * @brief This function clears the Timer capture interrupt flag. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->ISR = TIMER_ISR_TCAP_IS_Msk; +} + +/** + * @brief This function indicates Timer has waked up system or not. + * @param[in] timer The base address of Timer module + * @return Timer has waked up system or not + * @retval 0 Timer did not wake up system + * @retval 1 Timer wake up system + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->ISR & TIMER_ISR_TMR_WAKE_STS_Msk ? 1 : 0); +} + +/** + * @brief This function clears the Timer wakeup interrupt flag. + * @param[in] timer The base address of Timer module + * @return None + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->ISR = TIMER_ISR_TMR_WAKE_STS_Msk; +} + +/** + * @brief This function gets the Timer capture data. + * @param[in] timer The base address of Timer module + * @return Timer capture data value + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->TCAP; +} + +/** + * @brief This function reports the current timer counter value. + * @param[in] timer The base address of Timer module + * @return Timer counter value + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->DR; +} + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/*@}*/ /* end of group NANO100_TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_TIMER_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__TIMER_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/uart.h b/program/Library/StdDriver/inc/uart.h new file mode 100644 index 0000000..1569ef7 --- /dev/null +++ b/program/Library/StdDriver/inc/uart.h @@ -0,0 +1,380 @@ +/**************************************************************************//** + * @file uart.h + * @version V1.00 + * $Revision: 9 $ + * $Date: 15/06/26 1:36p $ + * @brief Nano100 Series uart control header file. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_UART_Driver UART Driver + @{ +*/ + +/** @addtogroup NANO100_UART_EXPORTED_CONSTANTS UART Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_LCR constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_WORD_LEN_5 (0) /*!< UART_TLCTL setting to set UART word length to 5 bits */ +#define UART_WORD_LEN_6 (1) /*!< UART_TLCTL setting to set UART word length to 6 bits */ +#define UART_WORD_LEN_7 (2) /*!< UART_TLCTL setting to set UART word length to 7 bits */ +#define UART_WORD_LEN_8 (3) /*!< UART_TLCTL setting to set UART word length to 8 bits */ + +#define UART_PARITY_NONE (0x0 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as no parity */ +#define UART_PARITY_ODD (0x1 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as odd parity */ +#define UART_PARITY_EVEN (0x3 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as even parity */ +#define UART_PARITY_MARK (0x5 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to keep parity bit as '1' */ +#define UART_PARITY_SPACE (0x7 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to keep parity bit as '0' */ + +#define UART_STOP_BIT_1 (0x0 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for one stop bit */ +#define UART_STOP_BIT_1_5 (0x1 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for 1.5 stop bit when 5-bit word length */ +#define UART_STOP_BIT_2 (0x1 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for two stop bit when 6, 7, 8-bit word length */ + +#define UART_TLCTL_RFITL_1BYTE (0x0 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 1 bit */ +#define UART_TLCTL_RFITL_4BYTES (0x1 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 4 bits */ +#define UART_TLCTL_RFITL_8BYTES (0x2 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 8 bits */ +#define UART_TLCTL_RFITL_14BYTES (0x3 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 14 bits */ + +#define UART_TLCTL_RTS_TRI_LEV_1BYTE (0x0 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 1 bit */ +#define UART_TLCTL_RTS_TRI_LEV_4BYTES (0x1 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 4 bits */ +#define UART_TLCTL_RTS_TRI_LEV_8BYTES (0x2 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 8 bits */ +#define UART_TLCTL_RTS_TRI_LEV_14BYTES (0x3 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 14 bits */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART RTS LEVEL TRIGGER constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MCSR_LEV_RTS_Pos) /*!< Set RTS is High Level Trigger */ +#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MCSR_LEV_RTS_Pos) /*!< Set RTS is Low Level Trigger */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UA_FUNC_SEL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_FUNC_SEL_UART (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set UART Function (Default) */ +#define UART_FUNC_SEL_LIN (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set LIN Function */ +#define UART_FUNC_SEL_IrDA (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set IrDA Function */ +#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set RS485 Function */ + + +/*@}*/ /* end of group NANO100_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Calculate UART baudrate mode0 divider + * + * @param None + * + * @return UART baudrate mode0 register setting value + * + */ +#define UART_BAUD_MODE0 (0) + +/** + * @brief Calculate UART baudrate mode0 divider + * + * @param None + * + * @return UART baudrate mode1 register setting value + * + */ +#define UART_BAUD_MODE1 (UART_BAUD_DIV_16_EN_Msk) + + +/** + * @brief Calculate UART baudrate mode0 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode1 divider + * + */ +#define UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-1) + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode0 divider + */ +#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-1) + + +/** + * @brief Write Data to Tx data register + * + * @param[in] uart The base address of UART module. + * @param[in] u8Data Data byte to transmit + * + * @return None + */ +#define UART_WRITE(uart, u8Data) (uart->THR = (u8Data)) + +/** + * @brief Read Rx data register + * + * @param[in] uart The base address of UART module. + * + * @return The oldest data byte in RX FIFO + */ +#define UART_READ(uart) (uart->RBR) + + +/** + * @brief Get Tx empty register value. + * + * @param[in] uart The base address of UART module + * + * @return Tx empty register value. + */ +#define UART_GET_TX_EMPTY(uart) (uart->FSR & UART_FSR_TX_EMPTY_F_Msk) + + +/** + * @brief Get Rx empty register value. + * + * @param[in] uart The base address of UART module + * + * @return Rx empty register value. + */ +#define UART_GET_RX_EMPTY(uart) (uart->FSR & UART_FSR_RX_EMPTY_F_Msk) + +/** + * @brief Check specified uart port transmission is over. + * + * @param[in] uart The base address of UART module + * + * @return TE_Flag. + */ +#define UART_IS_TX_EMPTY(uart) ((uart->FSR & UART_FSR_TE_F_Msk) >> UART_FSR_TE_F_Pos) + + +/** + * @brief Wait specified uart port transmission is over + * + * @param[in] uart The base address of UART module + * + * @return None + */ +#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FSR) & UART_FSR_TX_EMPTY_F_Msk) >> UART_FSR_TX_EMPTY_F_Pos)) + +/** + * @brief Check RDA_IF is set or not + * + * @param[in] uart The base address of UART module + * + * @return + * 0 : The number of bytes in the RX FIFO is less than the RFITL + * 1 : The number of bytes in the RX FIFO equals or larger than RFITL + */ +#define UART_IS_RX_READY(uart) ((uart->ISR & UART_ISR_RDA_IS_Msk)>>UART_ISR_RDA_IS_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The base address of UART module + * + * @return + * 1 = TX FIFO is full + * 0 = TX FIFO is not full + */ +#define UART_IS_TX_FULL(uart) ((uart->FSR & UART_FSR_TX_FULL_F_Msk)>>UART_FSR_TX_FULL_F_Pos) + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The base address of UART module + * + * @return + * 1 = RX FIFO is full + * 0 = RX FIFO is not full + * + */ +#define UART_IS_RX_FULL(uart) ((uart->FSR & UART_FSR_RX_FULL_F_Msk)>>UART_FSR_RX_FULL_F_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The base address of UART module + * + * @return Tx full register value + */ +#define UART_GET_TX_FULL(uart) (uart->FSR & UART_FSR_TX_FULL_F_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The base address of UART module + * + * @return Rx full register value + */ +#define UART_GET_RX_FULL(uart) (uart->FSR & UART_FSR_RX_FULL_F_Msk) + + +/** + * @brief Enable specified interrupt + * + * @param[in] uart The base address of UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_IER_LIN_IE_Msk : LIN interrupt + * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt + * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt + * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt + * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt + * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt + * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt + * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt + * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt + * + * @return None + */ +#define UART_ENABLE_INT(uart, u32eIntSel) (uart->IER |= (u32eIntSel)) + + +/** + * @brief Disable specified interrupt + * + * @param[in] uart The base address of UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_IER_LIN_IE_Msk : LIN interrupt + * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt + * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt + * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt + * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt + * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt + * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt + * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt + * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt + * @return None + */ +#define UART_DISABLE_INT(uart, u32eIntSel) (uart->IER &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The base address of UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag,should be + * - \ref UART_ISR_LIN_IS_Msk : LIN interrupt flag + * - \ref UART_ISR_ABAUD_IS_Msk : Auto baudrate interrupt flag + * - \ref UART_ISR_WAKE_IS_Msk : Wakeup interrupt flag + * - \ref UART_ISR_BUF_ERR_IS_Msk : Buffer Error interrupt flag + * - \ref UART_ISR_RTO_IS_Msk : Rx time-out interrupt flag + * - \ref UART_ISR_MODEM_IS_Msk : Modem interrupt flag + * - \ref UART_ISR_RLS_IS_Msk : Rx Line status interrupt flag + * - \ref UART_ISR_THRE_IS_Msk : Tx empty interrupt flag + * - \ref UART_ISR_RDA_IS_Msk : Rx ready interrupt flag + * + * @return + * 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->ISR & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Set RTS pin is low + * + * @param[in] uart The base address of UART module + * @return None + */ +static __INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MCSR |= UART_MCSR_LEV_RTS_Msk; +} + +/** + * @brief Set RTS pin is high + * + * @param[in] uart The base address of UART module + * @return None + */ +static __INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MCSR &= ~UART_MCSR_LEV_RTS_Msk; +} + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The base address of UART module + * @return None + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->TRSR |= UART_TRSR_RS485_ADDET_F_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The base address of UART module + * @return RS-485 Address Byte Detection Flag + */ +#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->TRSR & UART_TRSR_RS485_ADDET_F_Msk) >> UART_TRSR_RS485_ADDET_F_Pos) + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart ); +void UART_DisableFlowCtrl(UART_T* uart ); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag ); +void UART_EnableFlowCtrl(UART_T* uart ); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag ); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes); +void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes); + + +/*@}*/ /* end of group NANO100_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_UART_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__UART_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + + + + + + + + diff --git a/program/Library/StdDriver/inc/usbd.h b/program/Library/StdDriver/inc/usbd.h new file mode 100644 index 0000000..83eab95 --- /dev/null +++ b/program/Library/StdDriver/inc/usbd.h @@ -0,0 +1,516 @@ +/**************************************************************************//** + * @file usbd.h + * @brief NANO100 series USB driver header file + * @version 2.0.0 + * @date 20, September, 2014 + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup NANO100_USBD_EXPORTED_STRUCTS USBD Exported Structs + @{ +*/ +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Device descriptor */ + uint8_t *gu8ConfigDesc; /*!< Config descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for HID Report descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ +} S_USBD_INFO_T; + +/// @cond HIDDEN_SYMBOLS +extern S_USBD_INFO_T gsInfo; +/// @endcond /* HIDDEN_SYMBOLS */ + +/*@}*/ /* end of group NANO100_USBD_EXPORTED_STRUCTS */ + +/** @addtogroup NANO100_USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ +#define USBD_BUF_BASE (USBD_BASE+0x100) + +#define USBD_MAX_EP 8 + +#define EP0 0 /*!< Endpoint 0 */ +#define EP1 1 /*!< Endpoint 1 */ +#define EP2 2 /*!< Endpoint 2 */ +#define EP3 3 /*!< Endpoint 3 */ +#define EP4 4 /*!< Endpoint 4 */ +#define EP5 5 /*!< Endpoint 5 */ +#define EP6 6 /*!< Endpoint 6 */ +#define EP7 7 /*!< Endpoint 7 */ + +/// @cond HIDDEN_SYMBOLS +extern volatile uint32_t g_usbd_UsbConfig; + +/*! b, then return a. Otherwise, return b. + */ +#define Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + */ +#define Minimum(a,b) ((a)<(b) ? (a) : (b)) + +/** + * @brief Enable USBD engine + * @param None + * @retval None + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->CTL |= 0xF)) + +/** + * @brief Disable USBD engine + * @param None + * @retval None + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->CTL &= ~USBD_USB_EN)) + +/** + * @brief Enable USBD PHY + * @param None + * @retval None + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->CTL |= USBD_PHY_EN)) + +/** + * @brief Disable USBD PHY + * @param None + * @retval None + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->CTL &= ~USBD_PHY_EN)) + +/** + * @brief Force USB PHY Transceiver to Drive SE0 + * @param None + * @retval None + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->CTL |= USBD_DRVSE0)) + +/** + * @brief Release SE0 + * @param None + * @retval None + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->CTL &= ~USBD_DRVSE0)) + +/** + * @brief Set USBD address + * @param[in] addr host assign address number + * @retval None + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USBD address + * @param None + * @retval USBD address + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USBD interrupt + * @param[in] intr interrupt mask + * @retval None + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get USBD interrupt flag + * @param None + * @retval interrupt status + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USBD interrupt + * @param[in] flag interrupt flag + * @retval None + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = flag) + +/** + * @brief Get USBD Endpoint status + * @param None + * @retval endpoint status + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USBD bus state + * @param None + * @retval bus status + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->BUSSTS & 0xf)) + +/** + * @brief check cable connect state + * @param None + * @retval connect / disconnect + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->BUSSTS & USBD_BUSSTS_FLDET_Msk)) + +/** + * @brief Stop USB endpoint transaction + * @param[in] ep endpoint + * @retval None + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_CLRRDY_Msk) + +/** + * @brief Set USB data1 token + * @param[in] ep endpoint + * @retval None + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQ_SYNC_Msk) + +/** + * @brief Set USB data0 token + * @param[in] ep endpoint + * @retval None + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQ_SYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * @param[in] ep endpoint + * @param[in] size IN transfer length + * @retval None + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * @param[in] ep endpoint + * @retval received data length + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief config endpoint + * @param[in] ep endpoint + * @param[in] config config value + * @retval None + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set buffer for USB endpoint + * @param[in] ep endpoint + * @param[in] offset buffer offset + * @retval None + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get buffer for USB endpoint + * @param[in] ep endpoint + * @retval buffer offset + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= ~USBD_CFG_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_SSTALL_Msk) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size) +{ + while (size--) *dest++ = *src++; +} + + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * @return None + * + * @details Set USB endpoint stall state, endpoint will return STALL token. + */ +static __INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + int i; + + for (i=0; iEP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *) (u32CfgAddr)); + + if((u32Cfg & 0xf) == epnum) + { + *((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg | USBD_CFG_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * @return None + * + * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token. + */ +static __INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + int i; + + for (i=0; iEP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *) (u32CfgAddr)); + + if((u32Cfg & 0xf) == epnum) + { + *((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg & ~USBD_CFG_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * @retval 0 USB endpoint is not stalled. + * @retval non-0 USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + */ +static __INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + int i; + + for (i=0; iEP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *) (u32CfgAddr)); + + if((u32Cfg & 0xf) == epnum) + break; + } + return (u32Cfg & USBD_CFG_SSTALL); +} + + +/*--------------------------------------------------------------------*/ +extern volatile uint8_t g_usbd_RemoteWakeupEn; + +typedef void (*VENDOR_REQ)(void); /*!ISR = WDT_ISR_RST_IS_Msk) + +/** + * @brief This macro clear WDT time-out interrupt flag. + * @param None + * @return None + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->ISR = WDT_ISR_IS_Msk) + +/** + * @brief This macro clear WDT time-out wake-up system flag. + * @param None + * @return None + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->ISR = WDT_ISR_WAKE_IS_Msk) + +/** + * @brief This macro indicate WDT time-out to reset system or not. + * @return WDT reset system or not + * @retval 0 WDT did not cause system reset + * @retval 1 WDT caused system reset + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() (WDT->ISR & WDT_ISR_RST_IS_Msk ? 1 : 0) + +/** + * @brief This macro indicate WDT time-out interrupt occurred or not. + * @return WDT time-out interrupt occurred or not + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->ISR & WDT_ISR_IS_Msk ? 1 : 0) + +/** + * @brief This macro indicate WDT time-out waked system up or not + * @return WDT time-out waked system up or not + * @retval 0 WDT did not wake up system + * @retval 1 WDT waked up system + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->ISR & WDT_ISR_WAKE_IS_Msk ? 1 : 0) + +/** + * @brief This macro is used to reset 18-bit WDT counter. + * @details If WDT is activated and enabled to reset system, software must reset WDT counter + * before WDT time-out plus reset delay reached. Or WDT generate a reset signal. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->CTL |= WDT_CTL_WTR_Msk) + +/** + * @brief This function stops WDT counting and disable WDT module + * @param None + * @return None + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0; + return; +} + +/** + * @brief This function enables the WDT time-out interrupt + * @param None + * @return None + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->IER = WDT_IER_IE_Msk; + return; +} + +/** + * @brief This function disables the WDT time-out interrupt + * @param None + * @return None + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + WDT->IER = 0; + return; +} + +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup); + +/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_WDT_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__WDT_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/inc/wwdt.h b/program/Library/StdDriver/inc/wwdt.h new file mode 100644 index 0000000..dbe56f7 --- /dev/null +++ b/program/Library/StdDriver/inc/wwdt.h @@ -0,0 +1,126 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V1.00 + * $Revision: 2 $ + * $Date: 14/01/14 5:38p $ + * @brief Nano100 series WWDT driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup NANO100_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +#define WWDT_PRESCALER_1 (0UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1 */ +#define WWDT_PRESCALER_2 (1UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 2 */ +#define WWDT_PRESCALER_4 (2UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 4 */ +#define WWDT_PRESCALER_8 (3UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 8 */ +#define WWDT_PRESCALER_16 (4UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 16 */ +#define WWDT_PRESCALER_32 (5UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 32 */ +#define WWDT_PRESCALER_64 (6UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 64 */ +#define WWDT_PRESCALER_128 (7UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 128 */ +#define WWDT_PRESCALER_192 (8UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 192 */ +#define WWDT_PRESCALER_256 (9UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 256 */ +#define WWDT_PRESCALER_384 (0xAUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 384 */ +#define WWDT_PRESCALER_512 (0xBUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 512 */ +#define WWDT_PRESCALER_768 (0xCUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 768 */ +#define WWDT_PRESCALER_1024 (0xDUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1024 */ +#define WWDT_PRESCALER_1536 (0xEUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1536 */ +#define WWDT_PRESCALER_2048 (0xFUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 2048 */ + +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to RLD register to reload WWDT counter */ +/*@}*/ /* end of group NANO100_WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup NANO100_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief This macro clear WWDT time-out reset system flag. + * @param None + * @return None + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STS = WWDT_STS_RF_Msk) + +/** + * @brief This macro clears WWDT compare match interrupt flag. + * @param None + * @return None + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STS = WWDT_STS_IF_Msk) + +/** + * @brief This macro is use to get WWDT time-out reset system flag. + * @return WWDT reset system or not + * @retval 0 WWDT did not cause system reset + * @retval 1 WWDT caused system reset + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() (WWDT->STS & WWDT_STS_RF_Msk ? 1 : 0) + +/** + * @brief This macro is used to indicate WWDT compare match interrupt flag. + * @return WWDT compare match interrupt occurred or not + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() (WWDT->STS & WWDT_STS_IF_Msk ? 1 : 0) + +/** + * @brief This macro to reflects current WWDT counter value + * @param None + * @return Return current WWDT counter value + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->VAL) + +/** + * @brief This macro is used to reload the WWDT counter value to 0x3F. + * @param None + * @return None + * @details After WWDT enabled, application must reload WWDT counter while + * current counter is less than compare value and larger than 0, + * otherwise WWDT will cause system reset. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLD = WWDT_RELOAD_WORD) + + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + + +/*@}*/ /* end of group NANO100_WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_WWDT_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__WWDT_H__ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/EEPROM_Emulate.c b/program/Library/StdDriver/src/EEPROM_Emulate.c new file mode 100644 index 0000000..10c066e --- /dev/null +++ b/program/Library/StdDriver/src/EEPROM_Emulate.c @@ -0,0 +1,223 @@ +/**************************************************************************//** + * @file EEPROM_Emulate.c + * @brief Flash-based EEPROM emulation for Nuvoton Nano100B series. + * + * Storage layout (per page, EEP_FLASH_PAGE_SIZE bytes each): + * + * offset 0..3 : EEP_PAGE_MAGIC (0x55AA0001) -> page is valid + * offset 4.. : sequence of 32-bit entry words; an empty slot reads + * 0xFFFFFFFF (erased flash). Scanning stops at first + * empty slot. A valid entry is encoded as: + * + * byte 3 byte 2 byte 1 byte 0 + * +--------+---------+---------+--------+ + * | TAG | index | ~index | value | + * +--------+---------+---------+--------+ + * 0xE5 + * + * TAG (0xE5) lets us distinguish a written entry from + * the all-ones erased state, and the (~index) byte is a + * cheap consistency check. + * + * When the active page fills up, compact() copies the current state into + * the other page (one entry per non-default index), then erases the old + * page. Only one of the two pages is "live" at any time. + * + ******************************************************************************/ + +#include "Nano100Series.h" +#include "fmc.h" +#include "sys.h" +#include "EEPROM_Emulate.h" + +/*--------------------------------------------------------------------------*/ +/* Internal constants */ +/*--------------------------------------------------------------------------*/ + +#define EEP_PAGE_MAGIC 0x55AA0001u /* Marks a page as valid */ +#define EEP_ENTRY_TAG 0xE5u /* High byte of every valid entry */ +#define EEP_ERASED_WORD 0xFFFFFFFFu /* Erased flash reads as all 1s */ + +/*--------------------------------------------------------------------------*/ +/* Module state */ +/*--------------------------------------------------------------------------*/ + +/* RAM mirror - Read_Data() returns from here for speed. + * Initialised to 0xFF so an unwritten index reads as erased flash would. */ +static uint8_t s_data[EEP_DATA_SIZE]; + +/* Address of the currently active flash page. */ +static uint32_t s_active_page; + +/* Offset of the next free entry slot inside the active page. */ +static uint32_t s_next_offset; + +/* Logical sizes (latched from Init_EEPROM arguments). */ +static uint32_t s_data_size_used; +static uint32_t s_page_count; + +/* Public compatibility constants - the application calls + * Init_EEPROM(eep_data_size, eep_page_amount); */ +const uint32_t eep_data_size = EEP_DATA_SIZE; +const uint32_t eep_page_amount = EEP_PAGE_COUNT; + +/*--------------------------------------------------------------------------*/ +/* Helpers */ +/*--------------------------------------------------------------------------*/ + +static uint32_t page_addr(uint32_t page_idx) +{ + return EEP_FLASH_BASE + page_idx * EEP_FLASH_PAGE_SIZE; +} + +static uint32_t make_entry(uint8_t idx, uint8_t val) +{ + return ((uint32_t)EEP_ENTRY_TAG << 24) + | ((uint32_t)idx << 16) + | ((uint32_t)((uint8_t)~idx) << 8) + | (uint32_t)val; +} + +/* Returns 1 if word is a valid entry, 0 otherwise. Outputs idx & val. */ +static int parse_entry(uint32_t word, uint8_t *idx, uint8_t *val) +{ + uint8_t tag = (uint8_t)(word >> 24); + uint8_t i = (uint8_t)(word >> 16); + uint8_t ni = (uint8_t)(word >> 8); + uint8_t v = (uint8_t)(word ); + + if (tag != EEP_ENTRY_TAG) return 0; + if ((uint8_t)~i != ni) return 0; /* index check failed */ + if (i >= EEP_DATA_SIZE) return 0; + + *idx = i; + *val = v; + return 1; +} + +/* Erase a page and write its magic header. */ +static void format_page(uint32_t addr) +{ + FMC_Erase(addr); + FMC_Write(addr, EEP_PAGE_MAGIC); +} + +/* Scan a page; if valid, replay every entry into the RAM mirror. + * Returns the offset of the first empty slot (>= 4 if magic was OK, + * 0 if the page is invalid). */ +static uint32_t load_page(uint32_t addr) +{ + if (FMC_Read(addr) != EEP_PAGE_MAGIC) return 0; + + uint32_t off = 4; + while (off + 4 <= EEP_FLASH_PAGE_SIZE) { + uint32_t w = FMC_Read(addr + off); + if (w == EEP_ERASED_WORD) break; /* end of log */ + + uint8_t idx, val; + if (parse_entry(w, &idx, &val)) { + if (idx < s_data_size_used) s_data[idx] = val; + } + /* Corrupt entries are silently skipped, scan continues. */ + off += 4; + } + return off; +} + +/* Move the live image from the current page to the other page, + * then erase the old page. Updates s_active_page and s_next_offset. */ +static void compact(void) +{ + uint32_t old_addr = s_active_page; + uint32_t new_addr = (s_active_page == page_addr(0)) ? page_addr(1) + : page_addr(0); + + format_page(new_addr); + + uint32_t off = 4; + for (uint32_t i = 0; i < s_data_size_used; i++) { + if (s_data[i] != 0xFF) { /* skip "erased" */ + FMC_Write(new_addr + off, make_entry((uint8_t)i, s_data[i])); + off += 4; + if (off + 4 > EEP_FLASH_PAGE_SIZE) break; /* safety cap */ + } + } + + FMC_Erase(old_addr); + s_active_page = new_addr; + s_next_offset = off; +} + +/*==========================================================================*/ +/* Public API */ +/*==========================================================================*/ + +void Init_EEPROM(uint32_t data_size, uint32_t page_amount) +{ + s_data_size_used = (data_size > EEP_DATA_SIZE) ? EEP_DATA_SIZE : data_size; + s_page_count = (page_amount < 2u) ? 2u : page_amount; + (void)s_page_count; /* currently fixed at 2 internally */ + + /* Default RAM mirror to "blank flash" so an unwritten cell reads 0xFF. */ + for (uint32_t i = 0; i < EEP_DATA_SIZE; i++) s_data[i] = 0xFF; + + /* Enable FMC ISP and APROM update. SYS_UnlockReg is required because + * ISPCON is a protected register on Nano100 series. */ + SYS_UnlockReg(); + FMC_Open(); + FMC_ENABLE_AP_UPDATE(); +} + +void Search_Valid_Page(void) +{ + /* Strategy: try page 0 first; if invalid, try page 1; if neither has + * the magic word, format page 0 and start with empty data. */ + + uint32_t off = load_page(page_addr(0)); + if (off != 0) { + s_active_page = page_addr(0); + s_next_offset = off; + return; + } + + off = load_page(page_addr(1)); + if (off != 0) { + s_active_page = page_addr(1); + s_next_offset = off; + return; + } + + format_page(page_addr(0)); + s_active_page = page_addr(0); + s_next_offset = 4; +} + +uint32_t Read_Data(uint8_t index, uint8_t *data) +{ + if (data == 0) return 1; + if (index >= EEP_DATA_SIZE) return 2; + + *data = s_data[index]; + return 0; +} + +uint32_t Write_Data(uint8_t index, uint8_t data) +{ + if (index >= EEP_DATA_SIZE) return 1; + + /* Skip if value would not actually change - avoids needless flash wear. */ + if (s_data[index] == data) return 0; + + /* Update RAM mirror first; flash is just a backing store. */ + s_data[index] = data; + + /* Compact if the active page can no longer hold one more entry. */ + if (s_next_offset + 4u > EEP_FLASH_PAGE_SIZE) { + compact(); + } + + FMC_Write(s_active_page + s_next_offset, make_entry(index, data)); + s_next_offset += 4u; + + return 0; +} diff --git a/program/Library/StdDriver/src/adc.c b/program/Library/StdDriver/src/adc.c new file mode 100644 index 0000000..dc1a39c --- /dev/null +++ b/program/Library/StdDriver/src/adc.c @@ -0,0 +1,203 @@ +/**************************************************************************//** + * @file adc.c + * @version V1.00 + * $Revision: 7 $ + * $Date: 14/10/06 6:00p $ + * @brief NANO100 series ADC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_ADC_Driver ADC Driver + @{ +*/ + + +/** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions + @{ +*/ + +/** + * @brief This API configures ADC module to be ready for convert the input from selected channel + * @param[in] adc Base address of ADC module + * @param[in] u32InputMode Input mode (single-end/differential). Valid values are: + * - \ref ADC_INPUT_MODE_SINGLE_END + * - \ref ADC_INPUT_MODE_DIFFERENTIAL + * @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are: + * - \ref ADC_OPERATION_MODE_SINGLE + * - \ref ADC_OPERATION_MODE_SINGLE_CYCLE + * - \ref ADC_OPERATION_MODE_CONTINUOUS + * @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @note This API does not turn on ADC power nor does trigger ADC conversion + */ +void ADC_Open(ADC_T *adc, + uint32_t u32InputMode, + uint32_t u32OpMode, + uint32_t u32ChMask) +{ + + ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode; + ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode; + ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk); + ADC->CHEN = u32ChMask; + return; +} + +/** + * @brief Disable ADC module + * @param[in] adc Base address of ADC module + * @return None + */ +void ADC_Close(ADC_T *adc) +{ + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk; + return; + +} + +/** + * @brief Configure the hardware trigger condition and enable hardware trigger + * @param[in] adc Base address of ADC module + * @param[in] u32Source Decides the hardware trigger source. Valid values are: + * - \ref ADC_TRIGGER_BY_EXT_PIN + * @param[in] u32Param While ADC trigger by external pin, this parameter + * is used to set trigger condition. Valid values are: + * - \ref ADC_LOW_LEVEL_TRIGGER + * - \ref ADC_HIGH_LEVEL_TRIGGER + * - \ref ADC_FALLING_EDGE_TRIGGER + * - \ref ADC_RISING_EDGE_TRIGGER + * @return None + */ +void ADC_EnableHWTrigger(ADC_T *adc, + uint32_t u32Source, + uint32_t u32Param) +{ + ADC->CR &= ~(ADC_CR_TRGE_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGS_Msk); + ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk; + return; +} + +/** + * @brief Disable hardware trigger ADC function. + * @param[in] adc Base address of ADC module + * @return None + */ +void ADC_DisableHWTrigger(ADC_T *adc) +{ + ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk); + return; +} + +/** + * @brief Config and enable timer trigger + * @param[in] adc Base address of ADC module + * @param[in] u32Source Decides which timer trigger ADC. Valid values are: 0 ~ 3 + * @param[in] u32PDMACnt When timer event occurred, PDMA will transfer u32PDMACnt+1 ADC result + * @return None + */ +void ADC_EnableTimerTrigger(ADC_T *adc, + uint32_t u32Source, + uint32_t u32PDMACnt) +{ + ADC->CR &= ~(ADC_CR_TMPDMACNT_Msk | ADC_CR_TMSEL_Msk); + ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk; + + return; +} + +/** + * @brief Disable timer trigger ADC function. + * @param[in] adc Base address of ADC module + * @return None + */ +void ADC_DisableTimerTrigger(ADC_T *adc) +{ + ADC->CR &= ~ADC_CR_TMTRGMOD_Msk; + + return; +} + +/** + * @brief Configure the extended sampling time + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum The channel number + * @param[in] u32SampleTime Decides the extend sampling counter. Valid values are 0 ~ 15 + * @return None + */ +void ADC_SetExtraSampleTime(ADC_T *adc, + uint32_t u32ChNum, + uint32_t u32SampleTime) +{ + + if (u32ChNum < 8) + ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4)); + else if (u32ChNum < 12) + ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~(ADC_SMPLCNT1_CH8SAMPCNT_Msk << ((u32ChNum - 8) * 4))) | (u32SampleTime << ((u32ChNum - 8 ) * 4)); + else + ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos); +} + +/** + * @brief Enable the interrupt(s) selected by u32Mask parameter. + * @param[in] adc Base address of ADC module + * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit + * corresponds to a interrupt status. This parameter decides which + * interrupts will be enabled. + * - \ref ADC_ADF_INT + * - \ref ADC_CMP0_INT + * - \ref ADC_CMP1_INT + * @return None + */ +void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask) +{ + if(u32Mask & ADC_ADF_INT) + ADC->CR |= ADC_CR_ADIE_Msk; + if(u32Mask & ADC_CMP0_INT) + ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk; + if(u32Mask & ADC_CMP1_INT) + ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk; + + return; +} + +/** + * @brief Disable the interrupt(s) selected by u32Mask parameter. + * @param[in] adc Base address of ADC module + * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit + * corresponds to a interrupt status. This parameter decides which + * interrupts will be disabled. + * - \ref ADC_ADF_INT + * - \ref ADC_CMP0_INT + * - \ref ADC_CMP1_INT + * @return None + */ +void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask) +{ + if(u32Mask & ADC_ADF_INT) + ADC->CR &= ~ADC_CR_ADIE_Msk; + if(u32Mask & ADC_CMP0_INT) + ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk; + if(u32Mask & ADC_CMP1_INT) + ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk; + + return; +} + + + +/*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_ADC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/clk.c b/program/Library/StdDriver/src/clk.c new file mode 100644 index 0000000..a12ef10 --- /dev/null +++ b/program/Library/StdDriver/src/clk.c @@ -0,0 +1,647 @@ +/**************************************************************************//** + * @file clk.c + * @version V1.00 + * $Revision: 29 $ + * $Date: 15/06/30 3:10p $ + * @brief NANO100 series CLK driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "Nano100Series.h" +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_CLK_Driver CLK Driver + @{ +*/ + + +/** @addtogroup NANO100_CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief This function disable frequency output function. + * @param None + * @return None + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO0 clock source */ + CLK->APBCLK &= (~CLK_APBCLK_FDIV_EN_Msk); +} + +/** + * @brief This function enable frequency divider module clock, + * enable frequency divider clock function and configure frequency divider. + * @param[in] u32ClkSrc is frequency divider function clock source + * - \ref CLK_CLKSEL2_FRQDIV_S_HXT + * - \ref CLK_CLKSEL2_FRQDIV_S_LXT + * - \ref CLK_CLKSEL2_FRQDIV_S_HCLK + * - \ref CLK_CLKSEL2_FRQDIV_S_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. + * @return None + * + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. + * The formula is: + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->FRQDIV = CLK_FRQDIV_FDIV_EN_Msk | u32ClkDiv ; + + /* Enable CKO clock source */ + CLK->APBCLK |= CLK_APBCLK_FDIV_EN_Msk; + + /* Select CKO clock source */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV_S_Msk)) | u32ClkSrc; +} + +/** + * @brief This function let system enter to Power-down mode. + * @param None + * @return None + */ +void CLK_PowerDown(void) +{ + SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; + CLK->PWRCTL |= (CLK_PWRCTL_PD_EN_Msk | CLK_PWRCTL_WK_DLY_Msk ); + __WFI(); +} + +/** + * @brief This function let system enter to Idle mode + * @return None + */ +void CLK_Idle(void) +{ + CLK->PWRCTL &= ~(CLK_PWRCTL_PD_EN_Msk ); + __WFI(); +} + +/** + * @brief This function get external high frequency crystal frequency. The frequency unit is Hz. + * @param None + * @return None + */ +uint32_t CLK_GetHXTFreq(void) +{ + if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN ) + return __HXT; + else + return 0; +} + +/** + * @brief This function get external low frequency crystal frequency. The frequency unit is Hz. + * @return LXT frequency + */ +uint32_t CLK_GetLXTFreq(void) +{ + if(CLK->PWRCTL & CLK_PWRCTL_LXT_EN ) + return __LXT; + else + return 0; +} + +/** + * @brief This function get HCLK frequency. The frequency unit is Hz. + * @param None + * @return HCLK frequency + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief This function get CPU frequency. The frequency unit is Hz. + * @param None + * @return CPU frequency + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief This function get PLL frequency. The frequency unit is Hz. + * @param None + * @return PLL frequency + */ +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32Freq =0, u32PLLSrc; + uint32_t u32NO, u32NR, u32IN_DV, u32PllReg; + + u32PllReg = CLK->PLLCTL; + + if (u32PllReg & CLK_PLLCTL_PD) + return 0; /* PLL is in power down mode */ + + if (u32PllReg & CLK_PLLCTL_PLL_SRC_Msk) + u32PLLSrc = __HIRC12M; + else + u32PLLSrc = __HXT; + + u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1; + + u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DV_Msk) >> 8; + if (u32IN_DV == 0) + u32NR = 2; + else if (u32IN_DV == 1) + u32NR = 4; + else if (u32IN_DV == 2) + u32NR = 8; + else + u32NR = 16; + u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DV_Msk) +32) / u32NR / u32NO; + return u32Freq; +} + +/** + * @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 ~ 42 MHz + * @param[in] u32Hclk is HCLK frequency + * @return None + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_HIRC_STB_Msk; + + if(u32Hclk==__HIRC12M) + { + CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk); + CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_HCLK_CLK_DIVIDER(1)); + return SystemCoreClock; + } + + if(u32HclkFREQ_42MHZ) u32Hclk=FREQ_42MHZ; + + if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN) + CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT,u32Hclk*2); + else + { + CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk*2); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_HIRC_STB_Msk; + } + CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(2)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0) + CLK->PWRCTL &= ~CLK_PWRCTL_HIRC_EN_Msk; + + return SystemCoreClock; +} + +/** + * @brief This function set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLK_S_HXT + * - \ref CLK_CLKSEL0_HCLK_S_LXT + * - \ref CLK_CLKSEL0_HCLK_S_PLL + * - \ref CLK_CLKSEL0_HCLK_S_LIRC + * - \ref CLK_CLKSEL0_HCLK_S_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_HCLK_CLK_DIVIDER(x) + * @return None + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_HIRC_STB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRC_EN_Msk; + CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC; + + CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_N_Msk) | u32ClkDiv; + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc; + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0) + CLK->PWRCTL &= ~CLK_CLKSTATUS_HIRC_STB_Msk; +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :------------------- | :------------------------------- | :------------------------- | + * |\ref GPIO_MODULE | x | x | + * |\ref DMA_MODULE | x | x | + * |\ref ISP_MODULE | x | x | + * |\ref EBI_MODULE | x | x | + * |\ref SRAM_MODULE | x | x | + * |\ref TICK_MODULE | x | x | + * |\ref SC2_MODULE |\ref CLK_CLKSEL2_SC_S_HXT |\ref CLK_SC2_CLK_DIVIDER(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL2_SC_S_PLL |\ref CLK_SC2_CLK_DIVIDER(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL2_SC_S_HIRC |\ref CLK_SC2_CLK_DIVIDER(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL2_SC_S_HXT |\ref CLK_SC1_CLK_DIVIDER(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL2_SC_S_PLL |\ref CLK_SC1_CLK_DIVIDER(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL2_SC_S_HIRC |\ref CLK_SC1_CLK_DIVIDER(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL2_SC_S_HXT |\ref CLK_SC0_CLK_DIVIDER(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL2_SC_S_PLL |\ref CLK_SC0_CLK_DIVIDER(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL2_SC_S_HIRC |\ref CLK_SC0_CLK_DIVIDER(x) | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HXT |\ref CLK_I2S_CLK_DIVIDER(x) | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_PLL |\ref CLK_I2S_CLK_DIVIDER(x) | + * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HIRC |\ref CLK_I2S_CLK_DIVIDER(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HXT |\ref CLK_ADC_CLK_DIVIDER(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_LXT |\ref CLK_ADC_CLK_DIVIDER(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_PLL |\ref CLK_ADC_CLK_DIVIDER(x) | + * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HIRC |\ref CLK_ADC_CLK_DIVIDER(x) | + * |\ref USBD_MODULE | x |\ref CLK_USB_CLK_DIVIDER(x) | + * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_HXT | x | + * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_LXT | x | + * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_HCLK | x | + * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_HIRC | x | + * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_HXT | x | + * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_LXT | x | + * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_HCLK | x | + * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_HIRC | x | + * |\ref LCD_MODULE |\ref CLK_CLKSEL1_LCD_S_LXT | x | + * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_HXT | x | + * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_LXT | x | + * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_HCLK | x | + * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_HIRC | x | + * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_HXT | x | + * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_LXT | x | + * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_HCLK | x | + * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_HIRC | x | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_LXT |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_LXT |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_UART_CLK_DIVIDER(x) | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2_S_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2_S_HCLK | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1_S_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1_S_HCLK | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0_S_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0_S_HCLK | x | + * |\ref I2C1_MODULE | x | x | + * |\ref I2C0_MODULE | x | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HXT | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_LXT | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HCLK | x | + * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_EXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_EXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_EXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_EXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x | + * |\ref RTC_MODULE | x | x | + * |\ref WDT_MODULE | x | x | + * | + */ + +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32tmp=0,u32sel=0,u32div=0; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) + { + u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4); + u32tmp = *(volatile uint32_t *)(u32div); + u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4); + u32tmp = *(volatile uint32_t *)(u32sel); + u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<PWRCTL |= u32ClkMask; + if(u32ClkMask & CLK_PWRCTL_HXT_EN_Msk) + CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk); + + if(u32ClkMask & CLK_PWRCTL_LXT_EN_Msk) + CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk); + + if(u32ClkMask & CLK_PWRCTL_HIRC_EN_Msk) + CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk); + + if(u32ClkMask & CLK_PWRCTL_LIRC_EN_Msk) + CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk); +} + +/** + * @brief This function disable clock source + * @param[in] u32ClkMask is clock source mask. Including: + * - \ref CLK_PWRCTL_HXT_EN_Msk + * - \ref CLK_PWRCTL_LXT_EN_Msk + * - \ref CLK_PWRCTL_HIRC_EN_Msk + * - \ref CLK_PWRCTL_LIRC_EN_Msk + * @return None + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief This function enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref GPIO_MODULE + * - \ref DMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref SRAM_MODULE + * - \ref TICK_MODULE + * - \ref SC2_MODULE + * - \ref SC1_MODULE + * - \ref SC0_MODULE + * - \ref USBD_MODULE + * - \ref I2S_MODULE + * - \ref ADC_MODULE + * - \ref PWM1_CH23_MODULE + * - \ref PWM1_CH01_MODULE + * - \ref PWM0_CH23_MODULE + * - \ref PWM0_CH01_MODULE + * - \ref UART1_MODULE + * - \ref UART0_MODULE + * - \ref SPI2_MODULE + * - \ref SPI1_MODULE + * - \ref SPI0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C0_MODULE + * - \ref FDIV_MODULE + * - \ref TMR3_MODULE + * - \ref TMR2_MODULE + * - \ref TMR1_MODULE + * - \ref TMR0_MODULE + * - \ref RTC_MODULE + * - \ref WDT_MODULE + * - \ref LCD_MODULE + * - \ref DAC_MODULE + * @return None + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1< FREQ_120MHZ) + u32PllFreq=FREQ_120MHZ; + + if(u32PllClkSrc!=CLK_PLLCTL_PLL_SRC_HIRC) + { + /* PLL source clock from HXT */ + u32Register = (0x0UL<16 || u32NF>(0x3F+32) ) + { + u32NR = u32NR>>1; + u32NF = u32NF>>1; + } + + for(i32NRVal=3; i32NRVal>=0; i32NRVal--) + if(u32NR==u32NRTable[i32NRVal]) break; + + CLK->PLLCTL = u32Register | (i32NRVal<<8) | (u32NF - 32) ; + + CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk; + + CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk); + + return CLK_GetPLLClockFreq(); + +} + +/** + * @brief This function disable PLL + * @param None + * @return None + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + +/** + * @brief This function execute delay function. + * @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ... + * @return 0 success + * -1 clock time out + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + */ +int32_t CLK_SysTickDelay(uint32_t us) +{ + int32_t tout = SystemCoreClock * ((us / 1000000) + 1) + (SystemCoreClock / 2); + + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = (0x00); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) && + (tout-- > 0)); + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) + return -1; /* time out */ + SysTick->CTRL = 0; + return 0; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It should be 0x1~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + SysTick->CTRL=0; + if( u32ClkSrc== CLK_CLKSEL0_STCLKSEL_HCLK ) /* Set System Tick clock source */ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + else + { + SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; + } + SysTick->LOAD = u32Count; /* Set System Tick reload value */ + SysTick->VAL = 0; /* Clear System Tick current value and counter flag */ + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Set System Tick counter enabled */ +} + +/** + * @brief Disable System Tick counter + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + SysTick->CTRL = 0; /* Set System Tick counter disabled */ +} + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including + * - \ref CLK_CLKSTATUS_CLK_SW_FAIL_Msk + * - \ref CLK_CLKSTATUS_HIRC_STB_Msk + * - \ref CLK_CLKSTATUS_LIRC_STB_Msk + * - \ref CLK_CLKSTATUS_PLL_STB_Msk + * - \ref CLK_CLKSTATUS_LXT_STB_Msk + * - \ref CLK_CLKSTATUS_HXT_STB_Msk + * @return 0 clock is not stable + * 1 clock is stable + * + * @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt; + + i32TimeOutCnt = __HSI / 20; + + while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + return 0; + } + return 1; +} + + +/*@}*/ /* end of group NANO100_CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_CLK_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + diff --git a/program/Library/StdDriver/src/crc.c b/program/Library/StdDriver/src/crc.c new file mode 100644 index 0000000..6dd4761 --- /dev/null +++ b/program/Library/StdDriver/src/crc.c @@ -0,0 +1,102 @@ +/**************************************************************************//** + * @file crc.c + * @version V1.00 + * $Revision: 3 $ + * $Date: 14/09/29 3:50p $ + * @brief Nano100 series CRC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_CRC_Driver CRC Driver + @{ +*/ + + +/** @addtogroup NANO100_CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC Polynomial Mode \ref CRC_CCITT, \ref CRC_8, \ref CRC_16, \ref CRC_32 + * @param[in] u32Attribute Parameter attribute \ref CRC_CHECKSUM_COM, \ref CRC_CHECKSUM_RVS, \ref CRC_WDATA_COM, \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value + * @param[in] u32DataLen CPU Write Data Length \ref CRC_CPU_WDATA_8, \ref CRC_CPU_WDATA_16, \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function enable the CRC channel. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + PDMAGCR->GCRCSR |= DMA_GCR_GCRCSR_CRC_CLK_EN_Msk; + PDMACRC->SEED = u32Seed; + PDMACRC->CTL = u32Mode | u32Attribute | u32DataLen | DMA_CRC_CTL_CRCCEN_Msk; + /* When operated in CPU PIO mode, setting RST bit will reload the initial seed value (CRC_SEED register) */ + PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk; +} + +/** + * @brief CRC Start DMA transfer + * + * @param[in] u32SrcAddr Source address + * @param[in] u32ByteCount Calculate byte count + * + * @return None + * + * @details This function start DMA transfer. + */ +void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount) +{ + PDMACRC->DMASAR = u32SrcAddr; + PDMACRC->DMABCR = u32ByteCount; + PDMACRC->CTL |= DMA_CRC_CTL_TRIG_EN_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum + * + * @details This macro get the CRC checksum + */ +uint32_t CRC_GetChecksum(void) +{ + switch (PDMACRC->CTL & DMA_CRC_CTL_CRC_MODE_Msk) + { + case CRC_CCITT: + case CRC_16: + return (PDMACRC->CHECKSUM & 0xffff); + + case CRC_32: + return (PDMACRC->CHECKSUM); + + case CRC_8: + return (PDMACRC->CHECKSUM & 0xff); + + default: + return 0; + } +} + + +/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_CRC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/dac.c b/program/Library/StdDriver/src/dac.c new file mode 100644 index 0000000..ee792fe --- /dev/null +++ b/program/Library/StdDriver/src/dac.c @@ -0,0 +1,118 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * $Revision: 4 $ + * $Date: 14/09/08 12:31p $ + * @brief NANO100 series DAC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup NANO100_DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make a DAC channel ready to convert. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @param[in] u32TrgSrc Decides the trigger source of specified DAC channel. Valid options are: + * - \ref DAC_WRITE_DAT_TRIGGER + * - \ref DAC_PDMA_TRIGGER + * - \ref DAC_TIMER0_TRIGGER + * - \ref DAC_TIMER1_TRIGGER + * - \ref DAC_TIMER2_TRIGGER + * - \ref DAC_TIMER3_TRIGGER + * @return None + * @note This API also set DAC stable time to 2uc according to current PCLK + */ +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc) +{ + uint32_t u32Delay; + + // DAC needs 6 us to stable after power on + u32Delay = CLK_GetHCLKFreq() * 6 / 1000000; + if(u32Delay == 0) + u32Delay++; + if(u32Ch == 0) + DAC->CTL0 = (u32Delay << DAC_CTL_DACPWONSTBCNT_Pos) | u32TrgSrc | DAC_CTL_DACEN_Msk; + else + DAC->CTL1 = (u32Delay << DAC_CTL_DACPWONSTBCNT_Pos) | u32TrgSrc | DAC_CTL_DACEN_Msk; + + // DAC needs 2 us to stable after convert. + u32Delay = CLK_GetHCLKFreq() * 2 / 1000000; + if(u32Delay == 0) + u32Delay++; + DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_Msk) | u32Delay; +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch DAC channel number, could be 0 or 1 + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + if(u32Ch == 0) + { + DAC->CTL0 &= ~DAC_CTL_DACEN_Msk; + } + else + { + DAC->CTL1 &= ~DAC_CTL_DACEN_Msk; + } + +} + + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac Base address of DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, Valid values are between 1~0xFF. + * @return Success or failed + * @retval 0 Success + * @retval -1 Failed, the new setting will cause stable time less than 2us. So new setting is not applied. + * @details For example, DAC controller clock speed is 12MHz and DAC conversion settling time is 3 us, + * u32Delay should be given the value 3 * 12 = 36. + * @note User needs to write appropriate value to meet DAC conversion settling time base on + * PCLK (APB clock) speed. Minimum delay is 2 us. + * @note This setting is shared by both DAC channels. + */ +int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + uint32_t u32Dly; + + // DAC needs 2 us to stable after DAC convert, calculate minimal setting + u32Dly = CLK_GetHCLKFreq() * 2 / 1000000; + if(u32Dly == 0) + u32Dly++; + + if(u32Delay < u32Dly) // return error id stable time is shorter than 2us + return -1; + DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_Msk) | u32Delay; + return 0; +} + + + + +/*@}*/ /* end of group NANO100_DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_DAC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/ebi.c b/program/Library/StdDriver/src/ebi.c new file mode 100644 index 0000000..579ab09 --- /dev/null +++ b/program/Library/StdDriver/src/ebi.c @@ -0,0 +1,154 @@ +/****************************************************************************//** + * @file ebi.c + * @version V0.10 + * $Revision: 3 $ + * $Date: 14/02/05 10:36a $ + * @brief NANO100 series EBI driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" +#include "ebi.h" + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_EBI_Driver EBI Driver + @{ +*/ + + +/** @addtogroup NANO100_EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize and enable EBI + * @param[in] u32Bank argument is reserved in NANO100 series. + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode argument is reserved in NANO100 series. + * @param[in] u32CSActiveLevel argument is reserved in NANO100 series. + * @return none + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + EBI->EBICON = 0; + + if (u32DataWidth == EBI_BUSWIDTH_8BIT) + EBI->EBICON &= ~EBI_EBICON_ExtBW16_Msk; + else + EBI->EBICON |= EBI_EBICON_ExtBW16_Msk; + + EBI->EBICON &= ~(EBI_EBICON_ExttALE_Msk | EBI_EBICON_MCLKDIV_Msk); + switch (u32TimingClass) + { + case EBI_TIMING_FASTEST: + EBI->EBICON |= (0 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = 0; + break; + + case EBI_TIMING_VERYFAST: + EBI->EBICON |= (1 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = (4 << EBI_EXTIME_ExttACC_Pos) | (1 << EBI_EXTIME_ExttAHD_Pos) | + (2 << EBI_EXTIME_ExtIW2X_Pos) | (2 << EBI_EXTIME_ExtIR2W_Pos) | + (2 << EBI_EXTIME_ExtIR2R_Pos); + break; + + case EBI_TIMING_FAST: + EBI->EBICON |= (2 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_4 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = (8 << EBI_EXTIME_ExttACC_Pos) | (2 << EBI_EXTIME_ExttAHD_Pos) | + (4 << EBI_EXTIME_ExtIW2X_Pos) | (4 << EBI_EXTIME_ExtIR2W_Pos) | + (4 << EBI_EXTIME_ExtIR2R_Pos); + break; + + case EBI_TIMING_NORMAL: + EBI->EBICON |= (3 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_8 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = (16 << EBI_EXTIME_ExttACC_Pos) | (3 << EBI_EXTIME_ExttAHD_Pos) | + (8 << EBI_EXTIME_ExtIW2X_Pos) | (8 << EBI_EXTIME_ExtIR2W_Pos) | + (8 << EBI_EXTIME_ExtIR2R_Pos); + break; + + case EBI_TIMING_SLOW: + EBI->EBICON |= (4 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_16 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = (20 << EBI_EXTIME_ExttACC_Pos) | (4 << EBI_EXTIME_ExttAHD_Pos) | + (12 << EBI_EXTIME_ExtIW2X_Pos) | (12 << EBI_EXTIME_ExtIR2W_Pos) | + (12 << EBI_EXTIME_ExtIR2R_Pos); + break; + + case EBI_TIMING_VERYSLOW: + EBI->EBICON |= (5 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_32 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = (26 << EBI_EXTIME_ExttACC_Pos) | (5 << EBI_EXTIME_ExttAHD_Pos) | + (14 << EBI_EXTIME_ExtIW2X_Pos) | (14 << EBI_EXTIME_ExtIR2W_Pos) | + (14 << EBI_EXTIME_ExtIR2R_Pos); + break; + + case EBI_TIMING_SLOWEST: + EBI->EBICON |= (6 << EBI_EBICON_ExttALE_Pos); + EBI->EBICON |= (EBI_MCLKDIV_32 << EBI_EBICON_MCLKDIV_Pos); + EBI->EXTIME = (31 << EBI_EXTIME_ExttACC_Pos) | (7 << EBI_EXTIME_ExttAHD_Pos) | + (15 << EBI_EXTIME_ExtIW2X_Pos) | (15 << EBI_EXTIME_ExtIR2W_Pos) | + (15 << EBI_EXTIME_ExtIR2R_Pos); + break; + } + + EBI->EBICON |= EBI_EBICON_MCLKEN_Msk | EBI_EBICON_ExtEN_Msk; +} + +/** + * @brief Disable EBI + * @param[in] u32Bank argument is reserved in NANO100 series. + * @return none + */ +void EBI_Close(uint8_t u32Bank) +{ + EBI->EBICON = 0; + EBI->EXTIME = 0; +} + +/** + * @brief Set EBI bus timings + * @param[in] u32Bank argument is reserved in NANO100 series. + * @param[in] u32TimingConfig The new EBI timing settings. This value will be written to EXTIME register. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * @return none + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + EBI->EXTIME = u32TimingConfig; + EBI->EBICON = (EBI->EBICON & ~EBI_EBICON_MCLKDIV_Msk) | (u32MclkDiv << EBI_EBICON_MCLKDIV_Pos); +} + + +/*@}*/ /* end of group NANO100_EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_EBI_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/fmc.c b/program/Library/StdDriver/src/fmc.c new file mode 100644 index 0000000..46ee5a1 --- /dev/null +++ b/program/Library/StdDriver/src/fmc.c @@ -0,0 +1,334 @@ +/**************************************************************************//** + * @file fmc.c + * @version V1.00 + * $Revision: 8 $ + * $Date: 15/06/12 3:17p $ + * @brief NANO100 series FMC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +//* Includes ------------------------------------------------------------------*/ +#include + +#include "Nano100Series.h" + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup NANO100_FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +int32_t g_FMC_i32ErrCode; + +/** + * @brief Disable FMC ISP function. + * @return None + */ +void FMC_Close(void) +{ + FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk; +} + + +/** + * @brief Execute ISP command to erase a flash page. The page size is 512 bytes. + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 512-byte aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed or time-out + * @note Global error code g_FMC_i32ErrCode + * -1 time-out error + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t tout = FMC_TIMEOUT_ERASE; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if ((tout <= 0) || (FMC->ISPCON & FMC_ISPCON_ISPFF_Msk)) + { + g_FMC_i32ErrCode = -1; + FMC->ISPCON |= FMC_ISPCON_ISPFF_Msk; + return -1; + } + return 0; +} + + +/** + * @brief Get the current boot source. + * @return The current boot source. + * @retval 0 Is boot from APROM. + * @retval 1 Is boot from LDROM. + */ +int32_t FMC_GetBootSource (void) +{ + if (FMC->ISPCON & FMC_ISPCON_BS_Msk) + return 1; + else + return 0; +} + + +/** + * @brief Enable FMC ISP function + * @return None + */ +void FMC_Open(void) +{ + FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk; +} + + +/** + * @brief Execute ISP command to read a word from flash. + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * @return The word data read from specified flash address. + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + int32_t tout = FMC_TIMEOUT_ERASE; + + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADR = u32Addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if (tout <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + return FMC->ISPDAT; +} + + +/** + * @brief Read company ID. + * @return The company ID. + * Return 0xFFFFFFFF if read failed. + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +uint32_t FMC_ReadCID(void) +{ + int32_t tout = FMC_TIMEOUT_READ; + + FMC->ISPCMD = FMC_ISPCMD_READ_CID; + FMC->ISPADR = 0x0; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if (tout <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + return FMC->ISPDAT; +} + + +/** + * @brief Read product ID. + * @return The product ID. + * Return 0xFFFFFFFF if read failed. + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +uint32_t FMC_ReadPID(void) +{ + int32_t tout = FMC_TIMEOUT_READ; + + FMC->ISPCMD = FMC_ISPCMD_READ_PID; + FMC->ISPADR = 0x04; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if (tout <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + return FMC->ISPDAT; +} + + +/** + * @brief This function reads one of the four UCID. + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * @return The UCID. + * Return 0xFFFFFFFF if read failed. + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + int32_t tout = FMC_TIMEOUT_READ; + + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADR = (0x04 * u32Index) + 0x10; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if (tout <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + return FMC->ISPDAT; +} + + +/** + * @brief This function reads one of the three UID. + * @param[in] u32Index Index of the UID to read. u32Index must be 0, 1, or 2. + * @return The UID. + * Return 0xFFFFFFFF if read failed. + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +uint32_t FMC_ReadUID(uint32_t u32Index) +{ + int32_t tout = FMC_TIMEOUT_READ; + + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADR = 0x04 * u32Index; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if (tout <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + return FMC->ISPDAT; +} + + +/** + * @brief Get the base address of Data Flash if enabled. + * @return Base address of Data Flash + */ +uint32_t FMC_ReadDataFlashBaseAddr(void) +{ + return FMC->DFBADR; +} + + +/** + * @brief This function will force re-map assigned flash page to CPU address 0x0. + * @param[in] u32PageAddr Address of the page to be mapped to CPU address 0x0. + * @return None + * @note Global error code g_FMC_i32ErrCode + * -1 time-out + */ +void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + int32_t tout = FMC_TIMEOUT_WRITE; + + FMC->ISPCMD = FMC_ISPCMD_VECMAP; + FMC->ISPADR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if (tout <= 0) + g_FMC_i32ErrCode = -1; +} + + +/** + * @brief Obtain the current vector page address setting. + * @return The vector page address. + */ +uint32_t FMC_GetVectorPageAddr(void) +{ + return (FMC->ISPSTA & 0x0FFFFF00ul); +} + + +/** + * @brief Execute ISP command to program a word to flash. + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * @return None + */ +int32_t FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t tout = FMC_TIMEOUT_WRITE; + + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while ((tout-- > 0) && (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk)) {} + if ((tout <= 0) || (FMC->ISPSTA & FMC_ISPSTA_ISPFF_Msk)) + { + g_FMC_i32ErrCode = -1; + return -1; + } + return 0; +} + + +/** + * @brief Execute ISP command to read User Configuration. + * @param[out] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Avaliable word count in u32Config. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count) +{ + u32Config[0] = FMC_Read(FMC_CONFIG_BASE); + if (u32Count < 2) + return -1; + u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4); + return 0; +} + + +/** + * @brief Execute ISP command to write User Configuration. + * @param[in] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Available word count in u32Config. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count) +{ + FMC_ENABLE_CFG_UPDATE(); + FMC_Erase(FMC_CONFIG_BASE); + FMC_Write(FMC_CONFIG_BASE, u32Config[0]); + FMC_Write(FMC_CONFIG_BASE+4, u32Config[1]); + FMC_DISABLE_CFG_UPDATE(); + return 0; +} + + +/*@}*/ /* end of group NANO100_FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_FMC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ + + diff --git a/program/Library/StdDriver/src/gpio.c b/program/Library/StdDriver/src/gpio.c new file mode 100644 index 0000000..9fc5eb9 --- /dev/null +++ b/program/Library/StdDriver/src/gpio.c @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file gpio.c + * @version V1.00 + * $Revision: 3 $ + * $Date: 14/09/29 3:50p $ + * @brief Nano100 series GPIO driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_GPIO_Driver GPIO Driver + @{ +*/ + + +/** @addtogroup NANO100_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * @param[in] u32Mode Operation mode. \ref GPIO_PMD_INPUT, \ref GPIO_PMD_OUTPUT, \ref GPIO_PMD_OPEN_DRAIN + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i=0; iPMD = (gpio->PMD & ~(0x3 << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15 + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + gpio->IMD |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); + gpio->IER |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15 + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin) +{ + gpio->IMD &= ~(1UL << u32Pin); + gpio->IER &= ~((0x00010001UL) << u32Pin); +} + + + +/*@}*/ /* end of group NANO100_GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_GPIO_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/i2c.c b/program/Library/StdDriver/src/i2c.c new file mode 100644 index 0000000..01f1b1a --- /dev/null +++ b/program/Library/StdDriver/src/i2c.c @@ -0,0 +1,302 @@ +/****************************************************************************//** + * @file i2c.c + * @version V0.10 + * $Revision: 7 $ + * $Date: 15/06/05 5:04p $ + * @brief NANO100 series I2C driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup NANO100_I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief This function make I2C module be ready and set the wanted bus clock. + * @param[in] i2c is the base address of I2C module. + * @param[in] u32BusClock is the target bus speed of I2C module. + * @return Actual I2C bus clock frequency. + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + + u32Div = (uint32_t) (((SystemCoreClock * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */ + i2c->DIV = u32Div; + + /* Enable I2C */ + i2c->CON |= I2C_CON_IPEN_Msk; + + return ( SystemCoreClock / ((u32Div+1)<<2) ); +} + +/** + * @brief This function closes the I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C */ + if((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_I2C0_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_I2C0_RST_Msk; + } + else + { + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_I2C1_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_I2C1_RST_Msk; + } + + /* Disable I2C */ + i2c->CON &= ~I2C_CON_IPEN_Msk; +} + +/** + * @brief This function clears the timeout flag. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->INTSTS |= I2C_INTSTS_TIF_Msk; +} + +/** + * @brief This function sets the control bit of the I2C module. + * @param[in] i2c is the base address of I2C module. + * @param[in] u8Start sets START bit to I2C module. + * @param[in] u8Stop sets STOP bit to I2C module. + * @param[in] u8Si sets SI bit to I2C module. + * @param[in] u8Ack sets ACK bit to I2C module. + * @return none + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0; + uint32_t u32Val = i2c->CON & ~(I2C_STA | I2C_STO | I2C_AA); + + if (u8Start) + u32Reg |= I2C_STA; + if (u8Stop) + u32Reg |= I2C_STO; + if (u8Si) + u32Reg |= I2C_SI; + if (u8Ack) + u32Reg |= I2C_AA; + + i2c->CON = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CON &= ~I2C_CON_INTEN_Msk; +} + +/** + * @brief This function enables the interrupt (EI bit) of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CON |= I2C_CON_INTEN_Msk; +} + +/** + * @brief This function returns the real bus clock of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return Actual I2C bus clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->DIV; + + return ( SystemCoreClock / ((u32Divider+1)<<2) ); +} + +/** + * @brief This function sets bus frequency of I2C module. + * @param[in] i2c is the base address of I2C module. + * @param[in] u32BusClock is the target bus speed of I2C module. + * @return Actual I2C bus clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + + u32Div = (uint32_t) (((SystemCoreClock * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */ + i2c->DIV = u32Div; + + return ( SystemCoreClock / ((u32Div+1)<<2) ); +} + +/** + * @brief This function gets the interrupt flag of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return Interrupt flag. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + return ( (i2c->INTSTS & I2C_INTSTS_INTSTS_Msk) == I2C_INTSTS_INTSTS_Msk ? 1:0 ); +} + +/** + * @brief This function clears the interrupt flag of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_ClearIntFlag(I2C_T *i2c) +{ + i2c->INTSTS |= I2C_INTSTS_INTSTS_Msk; +} + +/** + * @brief This function returns the status of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return I2C status + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return ( i2c->STATUS ); +} + +/** + * @brief This function returns the data stored in data register of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return Data. + */ +uint32_t I2C_GetData(I2C_T *i2c) +{ + return ( i2c->DATA ); +} + +/** + * @brief This function writes the data to data register of I2C module. + * @param[in] i2c is the base address of I2C module. + * @param[in] u8Data is the data which will be write to data register of I2C module. + * @return none + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DATA = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode. + * @param[in] i2c is the base address of I2C module. + * @param[in] u8SlaveNo is the set number of salve address. + * @param[in] u8SlaveAddr is the slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref I2C_GCMODE_ENABLE + * - \ref I2C_GCMODE_DISABLE + * @return none + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch (u8SlaveNo) + { + case 0: + i2c->SADDR0 = (u8SlaveAddr << 1) | u8GCMode; + break; + case 1: + i2c->SADDR1 = (u8SlaveAddr << 1) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask of slave address. The corresponding address bit is "Don't Care". + * @param[in] i2c is the base address of I2C module. + * @param[in] u8SlaveNo is the set number of salve address. + * @param[in] u8SlaveAddrMask is the slave address mask. + * @return none + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch (u8SlaveNo) + { + case 0: + i2c->SAMASK0 = u8SlaveAddrMask << 1; + break; + case 1: + i2c->SAMASK1 = u8SlaveAddrMask << 1; + break; + } +} + +/** + * @brief This function enables timeout function and configures DIV4 function to support long timeout. + * @param[in] i2c is the base address of I2C module. + * @param[in] u8LongTimeout Enable timeout counter input clock is divide by 4. + * @return none + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + i2c->TOUT |= I2C_TOUT_DIV4_Msk; + else + i2c->TOUT &= ~I2C_TOUT_DIV4_Msk; + + i2c->TOUT |= I2C_TOUT_TOUTEN_Msk; +} + +/** + * @brief This function disables timeout function. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOUT &= ~I2C_TOUT_TOUTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKUPCON |= I2C_WKUPCON_WKUPEN_Msk; +} + +/** + * @brief This function disables the wakeup function of I2C module. + * @param[in] i2c is the base address of I2C module. + * @return none + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKUPCON &= ~I2C_WKUPCON_WKUPEN_Msk; +} + +/*@}*/ /* end of group NANO100_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_I2C_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/i2s.c b/program/Library/StdDriver/src/i2s.c new file mode 100644 index 0000000..05c3bc5 --- /dev/null +++ b/program/Library/StdDriver/src/i2s.c @@ -0,0 +1,206 @@ +/**************************************************************************//** + * @file i2s.c + * @version V1.00 + * $Revision: 4 $ + * $Date: 15/06/08 4:58p $ + * @brief Nano100 series I2S driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup NANO100_I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +/// @cond HIDDEN_SYMBOLS +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s is the base address of I2S module. + * @return I2S source clock frequency (Hz). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq, u32ClkSrcSel; + + // get I2S selection clock source + u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_I2S_S_Msk; + + switch (u32ClkSrcSel) + { + case CLK_CLKSEL2_I2S_S_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL2_I2S_S_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL2_I2S_S_HIRC: + u32Freq = __HIRC; + break; + + default: + u32Freq = __HIRC; + break; + } + + return u32Freq; +} +/// @endcond /* HIDDEN_SYMBOLS */ + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32Channels: Audio format. Valid values are: + * - \ref I2S_MONO + * - \ref I2S_STEREO + * @param[in] u32DataFormat: Data format. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_MSB + * @param[in] u32AudioInterface: Audio interface. Valid values are: + * - \ref I2S_I2S + * @return Real sample rate. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface) +{ + uint8_t u8Divider; + uint32_t u32BitRate, u32SrcClk; + + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_I2S_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_I2S_RST_Msk; + + i2s->CTRL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat | u32AudioInterface | I2S_FIFO_TX_LEVEL_WORD_4 | I2S_FIFO_RX_LEVEL_WORD_4; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + u32BitRate = u32SampleRate * (((u32WordWidth>>4) & 0x3) + 1) * 16; + u8Divider = ((u32SrcClk/u32BitRate) >> 1) - 1; + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLK_DIV_Msk) | (u8Divider << 8); + + //calculate real sample rate + u32BitRate = u32SrcClk / (2*(u8Divider+1)); + u32SampleRate = u32BitRate / ((((u32WordWidth>>4) & 0x3) + 1) * 16); + + i2s->CTRL |= I2S_CTRL_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function and I2S clock. + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTRL &= ~I2S_CTRL_I2SEN_Msk; +} + +/** + * @brief This function enables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->INTEN |= u32Mask; +} + +/** + * @brief This function disables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->INTEN &= ~u32Mask; +} + +/** + * @brief Enable MCLK . + * @param[in] i2s is the base address of I2S module. + * @param[in] u32BusClock is the target MCLK clock + * @return Actual MCLK clock + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if (u32BusClock == u32SrcClk) + u8Divider = 0; + else + u8Divider = (u32SrcClk/u32BusClock) >> 1; + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLK_DIV_Msk) | u8Divider; + + i2s->CTRL |= I2S_CTRL_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLK_DIV_Msk; + + if (u32Reg == 0) + return u32SrcClk; + else + return ((u32SrcClk >> 1) / u32Reg); +} + +/** + * @brief Disable MCLK . + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTRL &= ~I2S_CTRL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTRL = ((i2s->CTRL & ~(I2S_CTRL_TXTH_Msk | I2S_CTRL_RXTH_Msk)) | + (u32TxThreshold << I2S_CTRL_TXTH_Pos) | + (u32RxThreshold << I2S_CTRL_RXTH_Pos)); +} +/*@}*/ /* end of group NANO100_I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_I2S_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/lcd.c b/program/Library/StdDriver/src/lcd.c new file mode 100644 index 0000000..9d9799f --- /dev/null +++ b/program/Library/StdDriver/src/lcd.c @@ -0,0 +1,495 @@ +/**************************************************************************//** + * @file lcd.c + * @version V1.00 + * $Revision: 9 $ + * $Date: 15/07/06 2:08p $ + * @brief Nano100 series LCD driver header file + * The LCD driver can directly drives a LCD glass by creating the ac + * segment and common voltage signals automatically. It can support + * static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty, 1/6 duty LCD glass with up to 34 + * segments with 6 COM or 36 segments with 4 COM. + * + * @note + * Copyright (C) 2013~2014 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include +#include +#include +#include "Nano100Series.h" + + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_LCD_Driver LCD Driver + @{ +*/ + + +/// @cond HIDDEN_SYMBOLS + +/** @addtogroup NANO100_LCD_EXPORTED_VARIABLES LCD Exported Variables + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ + +double g_LCDFreq; +static uint32_t g_LCDFrameRate; /* src:32768Hz, COM:4, FREQ Div:64, frame-rate 64Hz */ +/* src:10240Hz, COM:4, FREQ Div:32, frame-rate 40Hz */ + + +/*@}*/ /* end of group NANO100_LCD_EXPORTED_VARIABLES */ + +/// @endcond /* HIDDEN_SYMBOLS */ + +/** @addtogroup NANO100_LCD_EXPORTED_FUNCTIONS LCD Exported Functions + @{ +*/ + +/** + * @brief Enables a segment on the LCD display + * + * @param[in] u32Com COM number + * @param[in] u32Seg Segment number + * @param[in] u32OnFlag 1: segment display + * 0: segment not display + * + * @return None + * + */ +void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag) +{ + int32_t memnum = u32Seg / 4; + int32_t seg_shift = 8*(u32Seg-(4*memnum)); + + if(u32OnFlag) + { + if(memnum==0) + { + LCD->MEM_0 |= (1<MEM_1 |= (1<MEM_2 |= (1<MEM_3 |= (1<MEM_4 |= (1<MEM_5 |= (1<MEM_6 |= (1<MEM_7 |= (1<MEM_8 |= (1<MEM_9 |= (1<MEM_0 &= ~((1<MEM_1 &= ~((1<MEM_2 &= ~((1<MEM_3 &= ~((1<MEM_4 &= ~((1<MEM_5 &= ~((1<MEM_6 &= ~((1<MEM_7 &= ~((1<MEM_8 &= ~((1<MEM_9 &= ~((1< 0) + SysTick->LOAD = 300 * CyclesPerUs; + else + SysTick->LOAD = 15; + SysTick->VAL = (0x00); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0); +} + +/** + * @brief LCD Enable/Disable all segments + * + * @param[in] u32OnOff 1: Enable all segments + * 0: Disable all segment + * + * @return None + * + */ +void LCD_SetAllPixels(uint32_t u32OnOff) +{ + uint32_t u32SetValue; + + if(u32OnOff) + { + u32SetValue = 0xFFFFFFFF; + } + else + { + u32SetValue = 0x00000000; + } + + LCD->MEM_0 = u32SetValue; + LCD->MEM_1 = u32SetValue; + LCD->MEM_2 = u32SetValue; + LCD->MEM_3 = u32SetValue; + LCD->MEM_4 = u32SetValue; + LCD->MEM_5 = u32SetValue; + LCD->MEM_6 = u32SetValue; + LCD->MEM_7 = u32SetValue; + LCD->MEM_8 = u32SetValue; + + if(CyclesPerUs > 0) + SysTick->LOAD = 300 * CyclesPerUs; + else + SysTick->LOAD = 15; + SysTick->VAL = (0x00); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0); +} + + +/** + * @brief Set Frame Count and Enable frame count + * + * @param[in] u32Count Frame count value + * + * + * @return real frame count value. + * + */ +uint32_t LCD_EnableFrameCounter(uint32_t u32Count) +{ + uint32_t div = 1; // default prediv == LCD_FCPRESC_DIV1 + + LCD->FCR = 0x00; + LCD->FCSTS |= LCD_FCSTS_FCSTS_Msk; // clear fcsts flag + + if(u32Count == 0) return 0; + + if(u32Count > 0x3F) // top value max. 63 = 0x3F + { + div = u32Count/64; + + if(div > 3) + { + div = 8; + LCD->FCR = (LCD->FCR & ~LCD_FCR_PRESCL_Msk) | LCD_FCPRESC_DIV8; + } + else if(div > 1) + { + div = 4; + LCD->FCR = (LCD->FCR & ~LCD_FCR_PRESCL_Msk) | LCD_FCPRESC_DIV4; + } + else + { + div = 2; + LCD->FCR = (LCD->FCR & ~LCD_FCR_PRESCL_Msk) | LCD_FCPRESC_DIV2; + } + + u32Count = (u32Count+(div/2))/div; + } + else + { + div = 1; + LCD->FCR = (LCD->FCR & ~LCD_FCR_PRESCL_Msk) | LCD_FCPRESC_DIV1; + } + + LCD->FCR = (LCD->FCR & ~LCD_FCR_FCV_Msk) | (u32Count << LCD_FCR_FCV_Pos); + + u32Count = u32Count*div; + + LCD->FCR |= LCD_FCR_FCEN_Msk; // enable LCD frame count + + return u32Count; +} + +/** + * @brief Disable frame count function + * + * @param None + * + * @return None + * + */ +void LCD_DisableFrameCounter(void) +{ + LCD->FCR = 0x00; // disable LCD frame count + + if( LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) // clear status flag + LCD->FCSTS = LCD_FCSTS_FCSTS_Msk; +} + + +/** + * @brief LCD Initialization routine. + * + * @param[in] u32DrivingType LCD driving type: \ref LCD_C_TYPE / \ref LCD_EXTERNAL_R_TYPE / \ref LCD_INTERNAL_R_TYPE / \ref LCD_EXTERNAL_C_TYPE + * @param[in] u32ComNum LCD Com number: 1 ~6 + * @param[in] u32BiasLevel LCD bias level: \ref LCD_BIAS_STATIC / \ref LCD_BIAS_HALF / \ref LCD_BIAS_THIRD + * @param[in] u32FramerateDiv LCD frequency divider: \ref LCD_FREQ_DIV32 / \ref LCD_FREQ_DIV64 / \ref LCD_FREQ_DIV96 / \ref LCD_FREQ_DIV128 / + * \ref LCD_FREQ_DIV192/ \ref LCD_FREQ_DIV256 / \ref LCD_FREQ_DIV384 / \ref LCD_FREQ_DIV512 + * @param[in] u32DrivingVol LCD charge pump driving voltage: \ref LCD_CPVOl_2_7V / \ref LCD_CPVOl_2_8V / \ref LCD_CPVOl_2_9V / \ref LCD_CPVOl_3V / + * \ref LCD_CPVOl_3_1V / \ref LCD_CPVOl_3_2V / \ref LCD_CPVOl_3_3V / \ref LCD_CPVOl_3_4V + * + * @return LCD frame rate. + * + */ +uint32_t LCD_Open(uint32_t u32DrivingType, uint32_t u32ComNum, uint32_t u32BiasLevel, uint32_t u32FramerateDiv, uint32_t u32DrivingVol) +{ + uint32_t clkdiv, muldiv; + uint32_t lcd_freq_div[] = {32, 64, 96, 128, 192, 256, 384, 512}; + uint32_t multiplex_freq_div[] = {2, 4, 6, 8, 10, 12}; + uint32_t u32clk_src; + + /* IP reset */ + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_LCD_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_LCD_RST_Msk; + + LCD_DisableDisplay(); + + /* Turn all segments off */ + LCD_SetAllPixels(0); + + + switch(u32DrivingType) + { + case LCD_C_TYPE: + case LCD_EXTERNAL_C_TYPE: + + LCD->DISPCTL &= ~LCD_DISPCTL_BV_SEL_Msk; // internal source for charge pump + LCD->DISPCTL = (LCD->DISPCTL & ~LCD_DISPCTL_CPUMP_FREQ_Msk) | (LCD_CPUMP_DIV1); + LCD->DISPCTL = (LCD->DISPCTL & ~LCD_DISPCTL_CPUMP_VOL_SET_Msk) | (u32DrivingVol); + LCD->DISPCTL &= ~LCD_DISPCTL_IBRL_EN_Msk; + LCD->DISPCTL |= LCD_DISPCTL_CPUMP_EN_Msk; // enable charge pump + + break; + + case LCD_EXTERNAL_R_TYPE: + case LCD_INTERNAL_R_TYPE: + + LCD->DISPCTL &= ~LCD_DISPCTL_CPUMP_EN_Msk; + LCD->DISPCTL |= LCD_DISPCTL_BV_SEL_Msk; + LCD->DISPCTL &= ~LCD_DISPCTL_IBRL_EN_Msk; + LCD->DISPCTL |= (u32DrivingType == LCD_INTERNAL_R_TYPE)?LCD_DISPCTL_IBRL_EN_Msk:0; + break; + + }; + + LCD->CTL &= ~LCD_CTL_FREQ_Msk; + LCD->CTL |= u32FramerateDiv; + + LCD->CTL = (LCD->CTL & ~LCD_CTL_MUX_Msk) | ((u32ComNum - 1) << LCD_CTL_MUX_Pos); + LCD->DISPCTL = (LCD->DISPCTL & ~LCD_DISPCTL_BIAS_SEL_Msk) | u32BiasLevel; + + if((CLK->CLKSEL1 & CLK_CLKSEL1_LCD_S_Msk) == 0) + u32clk_src = 32 * 1024; + else + u32clk_src = 10 * 1024; + + clkdiv = (LCD->CTL & LCD_CTL_FREQ_Msk) >> LCD_CTL_FREQ_Pos; + muldiv = (LCD->CTL & LCD_CTL_MUX_Msk) >> LCD_CTL_MUX_Pos; + + g_LCDFreq = (double)u32clk_src / lcd_freq_div[clkdiv]; + g_LCDFrameRate = (uint32_t)g_LCDFreq / multiplex_freq_div[muldiv]; + + return g_LCDFrameRate; +} + + + +/** + * @brief The function is used to disable LCD controller. + * + * @param None + * + * @return None + * + */ +void LCD_Close(void) +{ + LCD_DisableDisplay(); +} + + +/** + * @brief Enable Blink function in LCD controller + * + * @param[in] u32ms Blinking display time(unit: ms). + * + * @return Real blinking delay time(ms). + * + */ +uint32_t LCD_EnableBlink(uint32_t u32ms) +{ + uint32_t prescale=LCD_FCPRESC_DIV1, div=1; + uint32_t framecount; + + if((1000/u32ms) > g_LCDFrameRate) u32ms = (1000/g_LCDFrameRate); + + framecount = (uint32_t) (u32ms / (1000/g_LCDFrameRate)) ; + + if(framecount > 0x3F) + { + for(div=2; div<=8; div*=2) + { + framecount = (uint32_t) (u32ms / (1000/(g_LCDFrameRate/div)) ); + + if( framecount <= 0x40 ) + break; + } + if(div==2) prescale = LCD_FCPRESC_DIV2; + else if(div==4) prescale = LCD_FCPRESC_DIV4; + else if(div==8) prescale = LCD_FCPRESC_DIV8; + else return 0; + } + else if(framecount == 0) + { + framecount = 1; + } + + LCD->FCR = (LCD->FCR & ~LCD_FCR_PRESCL_Msk) | prescale; + LCD->FCR = (LCD->FCR & ~LCD_FCR_FCV_Msk) | ((framecount - 1) << LCD_FCR_FCV_Pos); + LCD->FCR |= LCD_FCR_FCEN_Msk; + + /* Enable Blink LCD */ + LCD->CTL |= LCD_CTL_BLINK_Msk; + + return ( (framecount*1000)/(g_LCDFrameRate/div) ); +} + + +/** + * @brief Disable Blink function in LCD controller + * + * @param None + * + * @return None + * + */ +void LCD_DisableBlink(void) +{ + /* Disable Blink LCD */ + LCD->CTL &= ~LCD_CTL_BLINK_Msk; + + /* Disable frame count */ + LCD->FCR = 0x00; // disable LCD frame count + + if( LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) // clear status flag + LCD->FCSTS = LCD_FCSTS_FCSTS_Msk; + +} + +/** + * @brief This function is used to enable LCD interrupt + * + * @param[in] IntSrc Interrupt Source: \ref LCD_FRAMECOUNT_INT / \ref LCD_POWERDOWN_INT / \ref LCD_ALL_INT + * + * @return None + * + */ +void LCD_EnableInt(uint32_t IntSrc) +{ + if((IntSrc & LCD_FRAMECOUNT_INT) == LCD_FRAMECOUNT_INT ) + { + LCD->FCR |= LCD_FCR_FCEN_Msk; + } + + if((IntSrc & LCD_POWERDOWN_INT) == LCD_POWERDOWN_INT ) + { + LCD->CTL |= LCD_CTL_PDINT_EN_Msk; + } + +} + +/** + * @brief This function is used to disable LCD specified interrupt + * + * @param[in] IntSrc Interrupt Source: \ref LCD_FRAMECOUNT_INT / \ref LCD_POWERDOWN_INT / \ref LCD_ALL_INT + * + * @return None + * + */ +void LCD_DisableInt(uint32_t IntSrc) +{ + if((IntSrc & LCD_FRAMECOUNT_INT) == LCD_FRAMECOUNT_INT ) + { + LCD->FCR &= ~LCD_FCR_FCEN_Msk; + LCD->FCSTS = LCD_FCSTS_FCSTS_Msk; + } + + if((IntSrc & LCD_POWERDOWN_INT) == LCD_POWERDOWN_INT ) + { + LCD->CTL &= ~LCD_CTL_PDINT_EN_Msk; + LCD->FCSTS = LCD_FCSTS_PDSTS_Msk; + } +} + +/*@}*/ /* end of group NANO100_LCD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_LCD_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/ + diff --git a/program/Library/StdDriver/src/pdma.c b/program/Library/StdDriver/src/pdma.c new file mode 100644 index 0000000..8c4c877 --- /dev/null +++ b/program/Library/StdDriver/src/pdma.c @@ -0,0 +1,244 @@ +/**************************************************************************//** + * @file pdma.c + * @version V1.00 + * $Revision: 5 $ + * $Date: 14/09/29 3:50p $ + * @brief Nano100 series PDMA driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup NANO100_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] u32Mask Channel enable bits + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(uint32_t u32Mask) +{ + PDMAGCR->GCRCSR |= (u32Mask << 8); +} + +/** + * @brief PDMA Close + * + * @param[in] None + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(void) +{ + PDMAGCR->GCRCSR = 0; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. \ref PDMA_WIDTH_8, \ref PDMA_WIDTH_16, or \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width; + switch (u32Width) + { + case PDMA_WIDTH_32: + pdma->BCR = (u32TransCount << 2); + break; + + case PDMA_WIDTH_8: + pdma->BCR = u32TransCount; + break; + + case PDMA_WIDTH_16: + pdma->BCR = (u32TransCount << 1); + break; + + default: + ; + } +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. \ref PDMA_SAR_INC, \ref PDMA_SAR_FIX, or \ref PDMA_SAR_WRA + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. \ref PDMA_DAR_INC, \ref PDMA_DAR_FIX, or \ref PDMA_DAR_WRA + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + + pdma->SAR = u32SrcAddr; + pdma->DAR = u32DstAddr; + pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk|PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. + * \ref PDMA_SPI0_TX, \ref PDMA_SPI1_TX, \ref PDMA_UART0_TX, \ref PDMA_UART1_TX, \ref PDMA_USB_TX, + * \ref PDMA_I2S_TX, \ref PDMA_DAC0_TX, \ref PDMA_DAC1_TX, \ref PDMA_SPI2_TX, \ref PDMA_TMR0, + * \ref PDMA_TMR1, \ref PDMA_TMR2, \ref PDMA_TMR3, \ref PDMA_SPI0_RX, \ref PDMA_SPI1_RX, + * \ref PDMA_UART0_RX, \ref PDMA_UART1_RX, \ref PDMA_USB_RX, \ref PDMA_I2S_RX, \ref PDMA_ADC, + * \ref PDMA_SPI2_RX, \ref PDMA_PWM0_CH0, \ref PDMA_PWM0_CH2, \ref PDMA_PWM1_CH0, \ref PDMA_PWM1_CH2, + * \ref PDMA_MEM + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + + switch (u32Ch) + { + case 1: + PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH1_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH1_SEL_Pos); + break; + case 2: + PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH2_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH2_SEL_Pos); + break; + case 3: + PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH3_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH3_SEL_Pos); + break; + case 4: + PDMAGCR->DSSR1 = (PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral; + break; + default: + ; + } + if (u32Peripheral == PDMA_MEM) + pdma->CSR &= ~PDMA_CSR_MODE_SEL_Msk; + else if (u32Peripheral & 0x10) + pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4; /* IP to memory */ + else + pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8; /* memory to IP */ +} + +/** + * @brief Set PDMA Timeout + * + * @param[in] u32Ch The selected channel + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + */ +void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + + pdma->TCR = (pdma->TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt; + pdma->CSR = (pdma->CSR & ~PDMA_CSR_TO_EN_Msk) | (u32OnOff << PDMA_CSR_TO_EN_Pos); + +} + +/** + * @brief Trigger PDMA + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(uint32_t u32Ch) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + + pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk); +} + +/** + * @brief Enable Interrupt + * + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + + pdma->IER |= u32Mask; +} + +/** + * @brief Disable Interrupt + * + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask) +{ + PDMA_T *pdma; + pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1))); + + pdma->IER &= ~u32Mask; +} + + +/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_PDMA_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/pwm.c b/program/Library/StdDriver/src/pwm.c new file mode 100644 index 0000000..8040a32 --- /dev/null +++ b/program/Library/StdDriver/src/pwm.c @@ -0,0 +1,537 @@ +/**************************************************************************//** + * @file PWM.c + * @version V1.00 + * $Revision: 14 $ + * $Date: 14/09/04 11:58a $ + * @brief NANO100 series PWM driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_PWM_Driver PWM Driver + @{ +*/ + + +/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions + @{ +*/ + +/** + * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigOutputChannel (PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32DutyCycle) +{ + uint32_t i; + uint32_t u32ClkSrc; + uint32_t u32PWM_Clock = SystemCoreClock; + uint8_t u8Divider = 1, u8Prescale = 0xFF; + uint16_t u16CNR = 0xFFFF; + + if(pwm == PWM0) + u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2)); + + else + u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2)); + + switch (u32ClkSrc) + { + case 0: + u32PWM_Clock = __HXT; + break; + case 1: + u32PWM_Clock = __LXT; + break; + case 2: + u32PWM_Clock = SystemCoreClock; + break; + case 3: + u32PWM_Clock = __HIRC12M; + break; + } + + for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16 + { + i = (u32PWM_Clock / u32Frequency) / u8Divider; + // If target value is larger than CNR * prescale, need to use a larger divider + if(i > (0x10000 * 0x100)) + continue; + + // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF + u8Prescale = (i + 0xFFFF)/ 0x10000; + + // u8Prescale must at least be 2, otherwise the output stop + if(u8Prescale < 3) + u8Prescale = 2; + + i /= u8Prescale; + + if(i <= 0x10000) + { + if(i == 1) + u16CNR = 1; // Too fast, and PWM cannot generate expected frequency... + else + u16CNR = i; + break; + } + + } + // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register + i = u32PWM_Clock / (u8Prescale * u8Divider * u16CNR); + + u8Prescale -= 1; + u16CNR -= 1; + // convert to real register value + if(u8Divider == 1) + u8Divider = 4; + else if (u8Divider == 2) + u8Divider = 0; + else if (u8Divider == 4) + u8Divider = 1; + else if (u8Divider == 8) + u8Divider = 2; + else // 16 + u8Divider = 3; + + // every two channels share a prescaler + while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk); + pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8)); + pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum)); + pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8)); + while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)); + if(u32DutyCycle == 0) + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; + else + { + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY_CM_Pos); + } + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR; + + return(i); +} + +/** + * @brief This function config PWM capture and get the nearest unit time + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec Unit time of counter + * @param[in] u32CaptureEdge Condition to latch the counter + * @return Nearest unit time in nano second + * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32UnitTimeNsec, + uint32_t u32CaptureEdge) +{ + uint32_t i; + uint32_t u32ClkSrc; + uint32_t u32PWM_Clock = SystemCoreClock; + uint8_t u8Divider = 1, u8Prescale = 0xFF; + uint16_t u16CNR = 0xFFFF; + + if(pwm == PWM0) + u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2)); + else + u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2)); + + switch (u32ClkSrc) + { + case 0: + u32PWM_Clock = __HXT; + break; + case 1: + u32PWM_Clock = __LXT; + break; + case 2: + u32PWM_Clock = SystemCoreClock; + break; + case 3: + u32PWM_Clock = __HIRC12M; + break; + } + + for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16 + { + i = ((long long)(u32PWM_Clock / u8Divider) * u32UnitTimeNsec) / 1000000000; + + // If target value is larger than 0xFF, need to use a larger divider + if(i > (0xFF)) + continue; + + u8Prescale = i; + + // u8Prescale must at least be 2, otherwise the output stop + if(u8Prescale < 3) + u8Prescale = 2; + + break; + } + + // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register + i = (long long) (u8Prescale * u8Divider) * 1000000000 / u32PWM_Clock; + + u8Prescale -= 1; + u16CNR -= 1; + // convert to real register value + if(u8Divider == 1) + u8Divider = 4; + else if (u8Divider == 2) + u8Divider = 0; + else if (u8Divider == 4) + u8Divider = 1; + else if (u8Divider == 8) + u8Divider = 2; + else // 16 + u8Divider = 3; + + // every two channels share a prescaler + while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk); + pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8)); + pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum)); + pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8)); + while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)); + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR; + + return(i); +} + +/** + * @brief This function start PWM module + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + */ +void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint8_t i; + uint32_t u32Mask = 0; + + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + u32Mask |= (PWM_CTL_CH0EN_Msk << (i * 8)); + } + + pwm->CTL |= u32Mask; +} + +/** + * @brief This function stop PWM module + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + */ +void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * i) &= ~PWM_DUTY_CN_Msk; + } + } + +} + +/** + * @brief This function stop PWM generation immediately by clear channel enable bit + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + */ +void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + pwm->CTL &= ~(PWM_CTL_CH0EN_Msk << (i * 8)); + } +} + +/** + * @brief This function enables PWM capture of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + */ +void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint8_t i; + uint32_t u32Mask = 0; + + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + { + u32Mask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8)); + } + } + + pwm->CAPCTL |= u32Mask; +} + +/** + * @brief This function disables PWM capture of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + */ +void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint8_t i; + uint32_t u32CTLMask = 0; + uint32_t u32CAPCTLMask = 0; + + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + { + u32CTLMask |= (PWM_CTL_CH0EN_Msk << (i * 8)); + u32CAPCTLMask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8)); + } + } + + pwm->CTL &= ~u32CTLMask; + pwm->CAPCTL &= ~u32CAPCTLMask; +} + +/** + * @brief This function enables PWM output generation of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + */ +void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask) +{ + pwm->OE |= u32ChannelMask; +} + +/** + * @brief This function disables PWM output generation of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + */ +void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask) +{ + pwm->OE &= ~u32ChannelMask; +} + +/** + * @brief This function enable Dead zone of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no + * dead zone. + * @return None + */ +void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + // every two channels shares the same setting + u32ChannelNum >>= 1; + // set duration + pwm->PRES = (pwm->PRES & ~(PWM_PRES_DZ01_Msk << (8 * u32ChannelNum))) | ((u32Duration << PWM_PRES_DZ01_Pos ) << (8 * u32ChannelNum)); + // enable dead zone + pwm->CTL |= (PWM_CTL_DZEN01_Msk << u32ChannelNum); +} + +/** + * @brief This function disable Dead zone of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + */ +void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum) +{ + // every two channels shares the same setting + u32ChannelNum >>= 1; + // enable dead zone + pwm->CTL &= ~(PWM_CTL_DZEN01_Msk << u32ChannelNum); +} + +/** + * @brief This function enable capture interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Capture interrupt type. It could be either + * - \ref PWM_RISING_LATCH_INT_ENABLE + * - \ref PWM_FALLING_LATCH_INT_ENABLE + * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE + * @return None + */ +void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + // enable capture interrupt + pwm->CAPINTEN |= (u32Edge << (u32ChannelNum * 8)); +} + +/** + * @brief This function disable capture interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Capture interrupt type. It could be either + * - \ref PWM_RISING_LATCH_INT_ENABLE + * - \ref PWM_FALLING_LATCH_INT_ENABLE + * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE + * @return None + */ +void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + // disable capture interrupt + pwm->CAPINTEN &= ~(u32Edge << (u32ChannelNum * 8)); +} + +/** + * @brief This function clear capture interrupt flag of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Capture interrupt type. It could be either + * - \ref PWM_RISING_LATCH_INT_FLAG + * - \ref PWM_FALLING_LATCH_INT_FLAG + * - \ref PWM_RISING_FALLING_LATCH_INT_FLAG + * @return None + */ +void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + // disable capture interrupt flag + pwm->CAPINTSTS = (u32Edge + 1) << (u32ChannelNum * 8); +} + +/** + * @brief This function get capture interrupt flag of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Capture interrupt flag of specified channel + * @retval 0 Capture interrupt did not occurred + * @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred + * @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred + * @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred + */ +uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum) +{ + return ((pwm->CAPINTSTS >> (u32ChannelNum * 8)) & (PWM_RISING_FALLING_LATCH_INT_FLAG)); +} + +/** + * @brief This function enable period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType This parameter is not used + * @return None + * @note All channels share the same period interrupt type setting. + */ +void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + // enable period interrupt + pwm->INTEN |= (PWM_INTEN_TMIE0_Msk << u32ChannelNum); +} + +/** + * @brief This function disable period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + */ +void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum) +{ + pwm->INTEN &= ~(PWM_INTEN_TMIE0_Msk << u32ChannelNum); +} + +/** + * @brief This function clear period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + */ +void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum) +{ + // write 1 clear + pwm->INTSTS = (PWM_INTSTS_TMINT0_Msk << u32ChannelNum); +} + +/** + * @brief This function get period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occurred + * @retval 1 Period interrupt occurred + */ +uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum) +{ + return ((pwm->INTSTS & (PWM_INTSTS_TMINT0_Msk << u32ChannelNum)) ? 1 : 0); +} + +/** + * @brief This function enable capture PDMA of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2 + * @param[in] u32RisingFirst Order of captured data transferred by PDMA. It could be either + * - \ref PWM_CAP_PDMA_RFORDER_R + * - \ref PWM_CAP_PDMA_RFORDER_F + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref PWM_RISING_LATCH_PDMA_ENABLE + * - \ref PWM_FALLING_LATCH_PDMA_ENABLE + * - \ref PWM_RISING_FALLING_LATCH_PDMA_ENABLE + * @return None + */ +void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + if (u32ChannelNum == 0) + pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD0_Msk | PWM_CAPCTL_CH0RFORDER_Msk)) | u32Mode | u32RisingFirst | PWM_CAPCTL_CH0PDMAEN_Msk; + else + pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD2_Msk | PWM_CAPCTL_CH2RFORDER_Msk)) | (u32Mode << 16)| (u32RisingFirst << 16)| PWM_CAPCTL_CH2PDMAEN_Msk; +} + +/** + * @brief This function disable capture PDMA of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2 + * @return None + */ +void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum) +{ + if (u32ChannelNum == 0) + pwm->CAPCTL &= ~PWM_CAPCTL_CH0PDMAEN_Msk; + else + pwm->CAPCTL &= ~PWM_CAPCTL_CH2PDMAEN_Msk; +} + +/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_PWM_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/retarget.c b/program/Library/StdDriver/src/retarget.c new file mode 100644 index 0000000..8b3ee1d --- /dev/null +++ b/program/Library/StdDriver/src/retarget.c @@ -0,0 +1,641 @@ +/**************************************************************************//** + * @file retarget.c + * @version V2.00 + * @brief Nano100 series retarget source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2024 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "Nano100Series.h" + +#if defined (__ICCARM__) + #pragma diag_suppress=Pm150 +#endif + + +#if defined ( __CC_ARM ) + #if (__ARMCC_VERSION < 400000) + #else + /* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */ + #pragma import _printf_widthprec + #endif +#endif + +#ifndef DEBUG_PORT + #define DEBUG_PORT UART0 +#endif +# define BUF_SIZE 512 + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global variables */ +/*---------------------------------------------------------------------------------------------------------*/ +#if !(defined(__ICCARM__) && (__VER__ >= 6010000)) +#if (__ARMCC_VERSION < 6040000) +struct __FILE +{ + int handle; /* Add whatever you need here */ +}; +#else +#if !defined(__MICROLIB) + #if (__OPTIMIZE__ == -O0) + __asm(".global __ARM_use_no_argv\n\t" "__ARM_use_no_argv:\n\t"); + #endif /* (__OPTIMIZE__ == -O0) */ +#endif /* !defined(__MICROLIB) */ +#endif /* (__ARMCC_VERSION < 6040000) */ + +#elif(__VER__ >= 8000000) +struct __FILE +{ + int handle; /* Add whatever you need here */ +}; +#endif /* !(defined(__ICCARM__) && (__VER__ >= 6010000)) */ + +FILE __stdout; +FILE __stdin; + +#if defined (__ARMCC_VERSION) || defined (__ICCARM__) + extern int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0); + + #if defined( __ICCARM__ ) + __WEAK + #else + __attribute__((weak)) + #endif + + uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp); +#endif + +int kbhit(void); +int IsDebugFifoEmpty(void); +void _ttywrch(int ch); +int fputc(int ch, FILE *stream); + +#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION) + #if !defined (OS_USE_SEMIHOSTING) + int _read(int fd, char *ptr, int len); + #endif + + int _write(int fd, char *ptr, int len); +#endif + +#if defined (__ARMCC_VERSION) || defined (__ICCARM__) + int fgetc(FILE *stream); + int ferror(FILE *stream); +#endif + +char GetChar(void); +void SendChar_ToUART(int ch); +void SendChar(int ch); +static volatile int32_t g_ICE_Conneced = 1; +enum { r0, r1, r2, r3, r12, lr, pc, psr}; + + +/** + * @brief Helper function to dump register while hard fault occurred + * @param[in] stack pointer points to the dumped registers in SRAM + * @return None + * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr + */ +static void DumpStack(uint32_t stack[]) +{ + /* + printf("r0 =0x%x\n", stack[r0]); + printf("r1 =0x%x\n", stack[r1]); + printf("r2 =0x%x\n", stack[r2]); + printf("r3 =0x%x\n", stack[r3]); + printf("r12=0x%x\n", stack[r12]); + printf("lr =0x%x\n", stack[lr]); + printf("pc =0x%x\n", stack[pc]); + printf("psr=0x%x\n", stack[psr]); + */ +} + + +#if defined(DEBUG_ENABLE_SEMIHOST) + +/* The static buffer is used to speed up the semihost */ +static char g_buf[16]; +static char g_buf_len = 0; + +/** + * + * @brief The function to process semihosted command + * @param[in] n32In_R0 : semihost register 0 + * @param[in] n32In_R1 : semihost register 1 + * @param[out] pn32Out_R0: semihost register 0 + * @retval 0: No ICE debug + * @retval 1: ICE debug + * + */ +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) +{ + if (g_ICE_Conneced) + { + if (pn32Out_R0) + *pn32Out_R0 = n32In_R0; + + return 1; + } + + return 0; +} + + +#else // defined(DEBUG_ENABLE_SEMIHOST) + +#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION) + +/** + * @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr + * + * @param None + * + * @returns None + * + * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr. + * + */ +__attribute__((weak)) void HardFault_Handler(void) +{ + asm("MOV R0, LR \n" + "MRS R1, MSP \n" + "MRS R2, PSP \n" + "LDR R3, =ProcessHardFault \n" + "BLX R3 \n" + "BX R0 \n" + ); +} + +#else +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0); +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) +{ + return 0; +} +#endif + +#endif /* defined(DEBUG_ENABLE_SEMIHOST) */ + + +#if defined( __ICCARM__ ) + __WEAK +#else + __attribute__((weak)) +#endif +uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp) +{ + uint32_t *sp; + uint32_t inst; + + /* It is casued by hardfault. Just process the hard fault */ + /* TODO: Implement your hardfault handle code here */ + + /* Check the used stack */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) + + if (lr & 0x40UL) + { +#endif + + /* Secure stack used */ + if (lr & 4UL) + { + sp = (uint32_t *)psp; + } + else + { + sp = (uint32_t *)msp; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) + } + else + { + /* Non-secure stack used */ + if (lr & 4) + sp = (uint32_t *)__TZ_get_PSP_NS(); + else + sp = (uint32_t *)__TZ_get_MSP_NS(); + } + +#endif + + /* Get the instruction caused the hardfault */ + inst = M16(sp[6]); + + if (inst == 0xBEAB) + { + /* + If the instruction is 0xBEAB, it means it is caused by BKPT without ICE connected. + We still return for output/input message to UART. + */ + g_ICE_Conneced = 0; // Set a flag for ICE offline + sp[6] += 2; // Return to next instruction + return lr; // Keep lr in R0 + } + + printf(" HardFault!\n\n"); + DumpStack(sp); + + /* Or *sp to remove compiler warning */ + while (1U | *sp) {} + + return lr; +} + + +/** + * @brief Routine to send a char + * + * @param[in] ch A character data writes to debug port + * + * @returns Send value from UART debug port + * + * @details Send a target char to UART debug port . + */ +#ifndef NONBLOCK_PRINTF +void SendChar_ToUART(int ch) +{ + while (DEBUG_PORT->FSR & UART_FSR_TX_FULL_F_Msk) {} + + if ((char)ch == '\n') + { + DEBUG_PORT->THR = '\r'; + + while (DEBUG_PORT->FSR & UART_FSR_TX_FULL_F_Msk) {} + + } + + DEBUG_PORT->THR = (uint32_t)ch; +} + +#else + +/* Non-block implement of send char */ +void SendChar_ToUART(int ch) +{ + static uint8_t u8Buf[BUF_SIZE] = {0}; + static int32_t i32Head = 0; + static int32_t i32Tail = 0; + int32_t i32Tmp; + + /* Only flush the data in buffer to UART when ch == 0 */ + if (ch) + { + // Push char + + if (ch == '\n') + { + i32Tmp = i32Head + 1; + + if (i32Tmp > BUF_SIZE) i32Tmp = 0; + + if (i32Tmp != i32Tail) + { + u8Buf[i32Head] = '\r'; + i32Head = i32Tmp; + } + } + + i32Tmp = i32Head + 1; + + if (i32Tmp > BUF_SIZE) i32Tmp = 0; + + if (i32Tmp != i32Tail) + { + u8Buf[i32Head] = ch; + i32Head = i32Tmp; + } + } + else + { + if (i32Tail == i32Head) + return; + } + + // Pop char + do + { + i32Tmp = i32Tail + 1; + + if (i32Tmp > BUF_SIZE) i32Tmp = 0; + + if ((DEBUG_PORT->FSR & UART_FSR_TX_FULL_F_Msk) == 0) + { + DEBUG_PORT->THR = u8Buf[i32Tail]; + i32Tail = i32Tmp; + } + else + break; // FIFO full + } while (i32Tail != i32Head); +} +#endif /* else for NONBLOCK_PRINTF */ + + +/** + * @brief Routine to send a char + * + * @param[in] ch : A character data writes to debug port + * + * @returns Send value from UART debug port or semihost + * + * @details Send a target char to UART debug port or semihost. + */ + +#if !defined( __ICCARM__ ) + #define __WEAK __attribute__((weak)) +#endif +__WEAK void SendChar(int ch) +{ +#if defined(DEBUG_ENABLE_SEMIHOST) + g_buf[g_buf_len++] = ch; + g_buf[g_buf_len] = '\0'; + + if (g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0') + { + /* Send the char */ + if (g_ICE_Conneced) + { + + if (SH_DoCommand(0x04, (int)g_buf, NULL) != 0) + { + g_buf_len = 0; + + return; + } + } + else + { +#if (DEBUG_ENABLE_SEMIHOST == 1) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=1 + int i; + + for (i = 0; i < g_buf_len; i++) + SendChar_ToUART(g_buf[i]); + +#endif + g_buf_len = 0; + } + } + +#else + SendChar_ToUART(ch); +#endif /* DEBUG_ENABLE_SEMIHOST */ +} + + +/** + * @brief Routine to get a char + * + * @param None + * + * @returns Get value from UART debug port or semihost + * + * @details Wait UART debug port or semihost to input a char. + */ +char GetChar(void) +{ +#ifdef DEBUG_ENABLE_SEMIHOST + + if (g_ICE_Conneced) + { +#if defined (__ICCARM__) + int nRet; + + while (SH_DoCommand(0x7, 0, &nRet) != 0) + { + if (nRet != 0) + return (char)nRet; + } + +#else + int nRet; + + while (SH_DoCommand(0x101, 0, &nRet) != 0) + { + if (nRet != 0) + { + SH_DoCommand(0x07, 0, &nRet); + return (char)nRet; + } + } + +#endif + + } + else + { + +#if (DEBUG_ENABLE_SEMIHOST == 1) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=1 + + /* Use debug port when ICE is not connected at semihost mode */ + while (!g_ICE_Conneced) + { + if ((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_F_Msk) == 0U) + { + return ((char)DEBUG_PORT->RBR); + } + } + +#endif + } + + return (0); + +#else + + while (1) + { + if ((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_F_Msk) == 0U) + { + return ((char)DEBUG_PORT->RBR); + } + } + +#endif +} + + +/** + * @brief Check any char input from UART + * + * @param None + * + * @retval 1: No any char input + * @retval 0: Have some char input + * + * @details Check UART RSR RX EMPTY or not to determine if any char input from UART + */ +int kbhit(void) +{ + return !((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_F_Msk) == 0U); +} + + +/** + * @brief Check if debug message finished + * + * @param None + * + * @retval 1: Message is finished + * @retval 0: Message is transmitting. + * + * @details Check if message finished (FIFO empty of debug port) + */ +int IsDebugFifoEmpty(void) +{ + return ((DEBUG_PORT->FSR & UART_FSR_TE_F_Msk) != 0U); +} + + +/** + * @brief C library retargetting + * + * @param[in] ch Write a character data + * + * @returns None + * + * @details Check if message finished (FIFO empty of debug port) + */ +void _ttywrch(int ch) +{ + SendChar(ch); + return; +} + + +/** + * @brief Write character to stream + * + * @param[in] ch Character to be written. The character is passed as its int promotion. + * @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written. + * + * @returns If there are no errors, the same character that has been written is returned. + * If an error occurs, EOF is returned and the error indicator is set (see ferror). + * + * @details Writes a character to the stream and advances the position indicator.\n + * The character is written at the current position of the stream as indicated \n + * by the internal position indicator, which is then advanced one character. + * + * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/. + * + * + */ +int fputc(int ch, FILE *stream) +{ + SendChar(ch); + return ch; +} + + +#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION) + +#if defined (OS_USE_SEMIHOSTING) + +#else + +int _write(int fd, char *ptr, int len) +{ + int i = len; + + while (i--) + { + while (DEBUG_PORT->FSR & UART_FSR_TX_FULL_F_Msk); + + if (*ptr == '\n') + { + DEBUG_PORT->THR = '\r'; + + while (DEBUG_PORT->FSR & UART_FSR_TX_FULL_F_Msk); + } + + DEBUG_PORT->THR = *ptr++; + } + + return len; +} + + +int _read(int fd, char *ptr, int len) +{ + while ((DEBUG_PORT->FSR & UART_FSR_RX_EMPTY_F_Msk) != 0); + + *ptr = DEBUG_PORT->RBR; + return 1; +} +#endif + +#else + +/** + * @brief Get character from UART debug port or semihosting input + * + * @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed. + * + * @returns The character read from UART debug port or semihosting + * + * @details For get message from debug port or semihosting. + * + */ +int fgetc(FILE *stream) +{ + return ((int)GetChar()); +} + + +/** + * @brief Check error indicator + * + * @param[in] stream Pointer to a FILE object that identifies the stream. + * + * @returns If the error indicator associated with the stream was set, the function returns a nonzero value. + * Otherwise, it returns a zero value. + * + * @details Checks if the error indicator associated with stream is set, returning a value different + * from zero if it is. This indicator is generally set by a previous operation on the stream that failed. + * + * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/. + * + */ +int ferror(FILE *stream) +{ + return EOF; +} +#endif + + +#ifdef DEBUG_ENABLE_SEMIHOST +#ifdef __ICCARM__ +void __exit(int return_code) +{ + /* Check if link with ICE */ + if (SH_DoCommand(0x18, 0x20026, NULL) == 0) + { + /* Make sure all message is print out */ + while (IsDebugFifoEmpty() == 0); + } + +label: + goto label; /* Endless loop */ +} + +#else + +void _sys_exit(int return_code) +{ + /* Check if link with ICE */ + if (SH_DoCommand(0x18, 0x20026, NULL) == 0) + { + /* Make sure all message is print out */ + while (IsDebugFifoEmpty() == 0); + } + +label: + goto label; /* Endless loop */ +} + +#endif +#endif diff --git a/program/Library/StdDriver/src/rtc.c b/program/Library/StdDriver/src/rtc.c new file mode 100644 index 0000000..2af7fac --- /dev/null +++ b/program/Library/StdDriver/src/rtc.c @@ -0,0 +1,957 @@ +/**************************************************************************//** + * @file rtc.c + * @version V1.00 + * $Revision: 11 $ + * $Date: 15/06/26 1:26p $ + * @brief Nano100 series RTC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + + +#include +#include "Nano100Series.h" + +/*---------------------------------------------------------------------------------------------------------*/ +/* Includes of local headers */ +/*---------------------------------------------------------------------------------------------------------*/ + + + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_RTC_Driver RTC Driver + @{ +*/ +/// @cond HIDDEN_SYMBOLS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32Reg, g_u32Reg1,g_u32hiYear,g_u32loYear,g_u32hiMonth,g_u32loMonth,g_u32hiDay,g_u32loDay; +static volatile uint32_t g_u32hiHour,g_u32loHour,g_u32hiMin,g_u32loMin,g_u32hiSec,g_u32loSec; + +/// @endcond HIDDEN_SYMBOLS + +/** @addtogroup NANO100_RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + + +/** + * @brief Set Frequency Compensation Data + * + * @param[in] i32FrequencyX100 Specify the RTC clock X100, ex: 3277365 means 32773.65. + * + * @return None + * + */ +void RTC_32KCalibration(int32_t i32FrequencyX100) +{ + int32_t i32RegInt,i32RegFra ; + int32_t i32TimeoutCnt = SystemCoreClock; // 1 second timeout + + /* Compute Integer and Fraction for RTC register*/ + i32RegInt = (i32FrequencyX100/100) - RTC_FCR_REFERENCE; + i32RegFra = (((i32FrequencyX100%100)) * 60) / 100; + + /* Judge Integer part is reasonable */ + if ( (i32RegInt < 0) | (i32RegInt > 15) ) + { + return; + } + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->FCR = (uint32_t)((i32RegInt<<8) | i32RegFra); + +} + +/** + * @brief This function is used to write initial key to let RTC start count and set current time. + * + * + * @param[in] sPt \n + * Specify the time property and current time. Null pointer for using default starting time. It includes: \n + * u32Year: Year value. \n + * u32Month: Month value. \n + * u32Day: Day value. \n + * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY / + * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY / + * \ref RTC_SATURDAY] \n + * u32Hour: Hour value. \n + * u32Minute: Minute value. \n + * u32Second: Second value. \n + * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n + * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n + * + * @return None + * + */ +void RTC_Open (S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + volatile int32_t i32delay=1000; + + RTC->INIR = RTC_INIT_KEY; + + if(RTC->INIR != 0x1) + { + RTC->INIR = RTC_INIT_KEY; + + while(RTC->INIR != 0x1) { + if(i32TimeoutCnt-- <= 0) + break; + } + } + + if(sPt == NULL) + return; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Second, set RTC 24/12 hour setting */ + /*-----------------------------------------------------------------------------------------------------*/ + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* important, range of 12-hour PM mode is 21 upto 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if (sPt->u32AmPm == RTC_PM) + sPt->u32Hour += 20; + } + else + { + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20; + u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16); + u32Reg |= ((sPt->u32Month / 10) << 12); + u32Reg |= ((sPt->u32Month % 10) << 8); + u32Reg |= ((sPt->u32Day / 10) << 4); + u32Reg |= (sPt->u32Day % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->CLR = (uint32_t)g_u32Reg; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + u32Reg = ((sPt->u32Hour / 10) << 20); + u32Reg |= ((sPt->u32Hour % 10) << 16); + u32Reg |= ((sPt->u32Minute / 10) << 12); + u32Reg |= ((sPt->u32Minute % 10) << 8); + u32Reg |= ((sPt->u32Second / 10) << 4); + u32Reg |= (sPt->u32Second % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->TLR = (uint32_t)g_u32Reg; + + RTC->DWR = sPt->u32DayOfWeek; + + /* Waiting for RTC settings stable */ + while(i32delay--); + +} + +/** + * @brief Read current date/time from RTC setting + * + * @param[out] sPt \n + * Specify the time property and current time. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24 \n + * u8AmPm: \ref RTC_AM / \ref RTC_PM \n + * + * @return None + * + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->TSSR & RTC_TSSR_24H_12H_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->DWR & RTC_DWR_DWR_Msk; /* Day of week */ + + g_u32hiYear = (RTC->CLR & RTC_CLR_10YEAR_Msk) >> RTC_CLR_10YEAR_Pos; + g_u32loYear = (RTC->CLR & RTC_CLR_1YEAR_Msk) >> RTC_CLR_1YEAR_Pos; + g_u32hiMonth = (RTC->CLR & RTC_CLR_10MON_Msk) >> RTC_CLR_10MON_Pos; + g_u32loMonth = (RTC->CLR & RTC_CLR_1MON_Msk) >> RTC_CLR_1MON_Pos; + g_u32hiDay = (RTC->CLR & RTC_CLR_10DAY_Msk) >> RTC_CLR_10DAY_Pos; + g_u32loDay = (RTC->CLR & RTC_CLR_1DAY_Msk); + + g_u32hiHour = (RTC->TLR & RTC_TLR_10HR_Msk) >> RTC_TLR_10HR_Pos; + g_u32loHour = (RTC->TLR & RTC_TLR_1HR_Msk) >> RTC_TLR_1HR_Pos; + g_u32hiMin = (RTC->TLR & RTC_TLR_10MIN_Msk) >> RTC_TLR_10MIN_Pos; + g_u32loMin = (RTC->TLR & RTC_TLR_1MIN_Msk) >> RTC_TLR_1MIN_Pos; + g_u32hiSec = (RTC->TLR & RTC_TLR_10SEC_Msk) >> RTC_TLR_10SEC_Pos; + g_u32loSec = (RTC->TLR & RTC_TLR_1SEC_Msk); + + u32Tmp = (g_u32hiYear * 10); /* Compute to 20XX year */ + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + u32Tmp = (g_u32hiMonth * 10); /* Compute 0~12 month */ + sPt->u32Month = u32Tmp + g_u32loMonth; + + u32Tmp = (g_u32hiDay * 10); /* Compute 0~31 day */ + sPt->u32Day = u32Tmp + g_u32loDay; + + if (sPt->u32TimeScale == RTC_CLOCK_12) /* Compute12/24 hour */ + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp+= g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if (sPt->u32Hour >= 21) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10); + u32Tmp+= g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp+= g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + +} + + + +/** + * @brief Read alarm date/time from RTC setting + * + * @param[out] sPt \n + * Specify the time property and current time. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24 \n + * u8AmPm: \ref RTC_AM / \ref RTC_PM \n + * + * @return None + * + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + sPt->u32TimeScale = RTC->TSSR & RTC_TSSR_24H_12H_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->DWR & RTC_DWR_DWR_Msk; /* Day of week */ + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + g_u32hiYear = (RTC->CAR & RTC_CAR_10YEAR_Msk) >> RTC_CAR_10YEAR_Pos; + g_u32loYear = (RTC->CAR & RTC_CAR_1YEAR_Msk) >> RTC_CAR_1YEAR_Pos; + g_u32hiMonth = (RTC->CAR & RTC_CAR_10MON_Msk) >> RTC_CAR_10MON_Pos; + g_u32loMonth = (RTC->CAR & RTC_CAR_1MON_Msk) >> RTC_CAR_1MON_Pos; + g_u32hiDay = (RTC->CAR & RTC_CAR_10DAY_Msk) >> RTC_CAR_10DAY_Pos; + g_u32loDay = (RTC->CAR & RTC_CAR_1DAY_Msk); + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + g_u32hiHour = (RTC->TAR & RTC_TAR_10HR_Msk) >> RTC_TAR_10HR_Pos; + g_u32loHour = (RTC->TAR & RTC_TAR_1HR_Msk) >> RTC_TAR_1HR_Pos; + g_u32hiMin = (RTC->TAR & RTC_TAR_10MIN_Msk) >> RTC_TAR_10MIN_Pos; + g_u32loMin = (RTC->TAR & RTC_TAR_1MIN_Msk) >> RTC_TAR_1MIN_Pos; + g_u32hiSec = (RTC->TAR & RTC_TAR_10SEC_Msk) >> RTC_TAR_10SEC_Pos; + g_u32loSec = (RTC->TAR & RTC_TAR_1SEC_Msk); + + u32Tmp = (g_u32hiYear * 10); /* Compute to 20XX year */ + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + u32Tmp = (g_u32hiMonth * 10); /* Compute 0~12 month */ + sPt->u32Month = u32Tmp + g_u32loMonth; + + u32Tmp = (g_u32hiDay * 10); /* Compute 0~31 day */ + sPt->u32Day = u32Tmp + g_u32loDay; + + if (sPt->u32TimeScale == RTC_CLOCK_12) /* Compute12/24 hour */ + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if (sPt->u32Hour >= 21) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10); + u32Tmp+= g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + +} + + + +/** + * @brief This function is used to update date/time to RTC. + * + * @param[in] sPt \n + * Specify the time property and current time. It includes: \n + * u32Year: Year value. \n + * u32Month: Month value. \n + * u32Day: Day value. \n + * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY / + * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY / + * \ref RTC_SATURDAY] \n + * u32Hour: Hour value. \n + * u32Minute: Minute value. \n + * u32Second: Second value. \n + * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n + * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n + * + * + * @return None + * + * + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + /*-----------------------------------------------------------------------------------------*/ + /* important, range of 12-hour PM mode is 21 upto 32 */ + /*-----------------------------------------------------------------------------------------*/ + if (sPt->u32AmPm == RTC_PM) + sPt->u32Hour += 20; + } + else + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + RTC->DWR = sPt->u32DayOfWeek & RTC_DWR_DWR_Msk; + + u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20; + u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16); + u32Reg |= ((sPt->u32Month / 10) << 12); + u32Reg |= ((sPt->u32Month % 10) << 8); + u32Reg |= ((sPt->u32Day / 10) << 4); + u32Reg |= (sPt->u32Day % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->CLR = (uint32_t)g_u32Reg; + + u32Reg = ((sPt->u32Hour / 10) << 20); + u32Reg |= ((sPt->u32Hour % 10) << 16); + u32Reg |= ((sPt->u32Minute / 10) << 12); + u32Reg |= ((sPt->u32Minute % 10) << 8); + u32Reg |= ((sPt->u32Second / 10) << 4); + u32Reg |= (sPt->u32Second % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->TLR = (uint32_t)g_u32Reg; + +} + +/** + * @brief This function is used to set alarm date/time to RTC. + * + * @param[in] sPt \n + * Specify the time property and current time. It includes: \n + * u32Year: Year value. \n + * u32Month: Month value. \n + * u32Day: Day value. \n + * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY / + * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY / + * \ref RTC_SATURDAY] \n + * u32Hour: Hour value. \n + * u32Minute: Minute value. \n + * u32Second: Second value. \n + * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n + * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n + * + * @return None + * + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + /*-----------------------------------------------------------------------------------------*/ + /* important, range of 12-hour PM mode is 21 upto 32 */ + /*-----------------------------------------------------------------------------------------*/ + if (sPt->u32AmPm == RTC_PM) + sPt->u32Hour += 20; + } + else + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + RTC->DWR = sPt->u32DayOfWeek & RTC_DWR_DWR_Msk; + + + u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20; + u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16); + u32Reg |= ((sPt->u32Month / 10) << 12); + u32Reg |= ((sPt->u32Month % 10) << 8); + u32Reg |= ((sPt->u32Day / 10) << 4); + u32Reg |= (sPt->u32Day % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->CAR = (uint32_t)g_u32Reg; + + u32Reg = ((sPt->u32Hour / 10) << 20); + u32Reg |= ((sPt->u32Hour % 10) << 16); + u32Reg |= ((sPt->u32Minute / 10) << 12); + u32Reg |= ((sPt->u32Minute % 10) << 8); + u32Reg |= ((sPt->u32Second / 10) << 4); + u32Reg |= (sPt->u32Second % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->TAR = (uint32_t)g_u32Reg; + +} + + +/** + * @brief This function is used to update date to RTC + * + * @param[in] u32Year The Year Calendar Digit of Alarm Setting + * @param[in] u32Month The Month Calendar Digit of Alarm Setting + * @param[in] u32Day The Day Calendar Digit of Alarm Setting + * @param[in] u32DayOfWeek The Day of Week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY / + * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY / + * \ref RTC_SATURDAY] + * + * @return None + * + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + __IO uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->DWR = u32DayOfWeek & RTC_DWR_DWR_Msk; + + u32Reg = ((u32Year - RTC_YEAR2000) / 10) << 20; + u32Reg |= (((u32Year - RTC_YEAR2000) % 10) << 16); + u32Reg |= ((u32Month / 10) << 12); + u32Reg |= ((u32Month % 10) << 8); + u32Reg |= ((u32Day / 10) << 4); + u32Reg |= (u32Day % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->CLR = (uint32_t)g_u32Reg; + +} + +/** + * @brief This function is used to update time to RTC. + * + * @param[in] u32Hour The Hour Time Digit of Alarm Setting. + * @param[in] u32Minute The Minute Time Digit of Alarm Setting + * @param[in] u32Second The Second Time Digit of Alarm Setting + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [ \ref RTC_AM / \ref RTC_PM] + * + * @return None + * + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + __IO uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + if (u32TimeMode == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + if (u32AmPm == RTC_PM) /* important, range of 12-hour PM mode is 21 upto 32 */ + u32Hour += 20; + } + else if(u32TimeMode == RTC_CLOCK_24) + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + u32Reg = ((u32Hour / 10) << 20); + u32Reg |= ((u32Hour % 10) << 16); + u32Reg |= ((u32Minute / 10) << 12); + u32Reg |= ((u32Minute % 10) << 8); + u32Reg |= ((u32Second / 10) << 4); + u32Reg |= (u32Second % 10); + + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->TLR = (uint32_t)g_u32Reg; + +} + +/** + * @brief This function is used to set alarm date to RTC + * + * @param[in] u32Year The Year Calendar Digit of Alarm Setting + * @param[in] u32Month The Month Calendar Digit of Alarm Setting + * @param[in] u32Day The Day Calendar Digit of Alarm Setting + * + * @return None + * + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + __IO uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + u32Reg = ((u32Year - RTC_YEAR2000) / 10) << 20; + u32Reg |= (((u32Year - RTC_YEAR2000) % 10) << 16); + u32Reg |= ((u32Month / 10) << 12); + u32Reg |= ((u32Month % 10) << 8); + u32Reg |= ((u32Day / 10) << 4); + u32Reg |= (u32Day % 10); + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->CAR = (uint32_t)g_u32Reg; + +} + +/** + * @brief This function is used to set alarm date to RTC + * + * @param[in] u32Hour The Hour Time Digit of Alarm Setting. + * @param[in] u32Minute The Month Calendar Digit of Alarm Setting + * @param[in] u32Second The Day Calendar Digit of Alarm Setting + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [ \ref RTC_AM / \ref RTC_PM] + * + * @return None + * + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + __IO uint32_t u32Reg; + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + if (u32TimeMode == RTC_CLOCK_12) + { + RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk; + + if (u32AmPm == RTC_PM) /* important, range of 12-hour PM mode is 21 upto 32 */ + u32Hour += 20; + } + else if(u32TimeMode == RTC_CLOCK_24) + { + RTC->TSSR |= RTC_TSSR_24H_12H_Msk; + } + + u32Reg = ((u32Hour / 10) << 20); + u32Reg |= ((u32Hour % 10) << 16); + u32Reg |= ((u32Minute / 10) << 12); + u32Reg |= ((u32Minute % 10) << 8); + u32Reg |= ((u32Second / 10) << 4); + u32Reg |= (u32Second % 10); + + g_u32Reg = u32Reg; + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->TAR = (uint32_t)g_u32Reg; + +} + + +/** + * @brief This function is used to enable tamper detection function and set tamper control register, interrupt. + * + * @param[in] u32PinCondition set tamper detection condition: 1=Falling detect, 0=Rising detect + * + * @return None + * + */ +void RTC_EnableTamperDetection(uint32_t u32PinCondition) +{ + int32_t i32TimeoutCnt = SystemCoreClock; // total 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + /* detection edge select */ + if(u32PinCondition) + RTC->SPRCTL |= RTC_SPRCTL_SNOOPEDGE_Msk; + else + RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEDGE_Msk; + + while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRDY_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } + + /* enable snooper pin event detection */ + RTC->SPRCTL |= RTC_SPRCTL_SNOOPEN_Msk; + while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRDY_Msk)) { + if(i32TimeoutCnt-- <= 0) + break; + } +} + +/** + * @brief This function is used to disable tamper detection function. + * + * @param None + * + * @return None + * + */ +void RTC_DisableTamperDetection(void) +{ + int32_t i32TimeoutCnt = SystemCoreClock; // 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEN_Msk; +} + +/** + * @brief This function is used to get day of week. + * + * @param None + * + * @return Day of week + * + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->DWR & RTC_DWR_DWR_Msk); +} + + +/** + * @brief The function is used to set time tick period for periodic time tick Interrupt. + * + * @param[in] u32TickSelection + * It is used to set the RTC time tick period for Periodic Time Tick Interrupt request. + * It consists of: \n + * \ref RTC_TICK_1_SEC : Time tick is 1 second \n + * \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second \n + * \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second \n + * \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second \n + * \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second \n + * \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second \n + * \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second \n + * \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + int32_t i32TimeoutCnt = SystemCoreClock; // 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->TTR = (RTC->TTR & ~RTC_TTR_TTR_Msk) | u32TickSelection; +} + +/** + * @brief The function is used to enable specified interrupt. + * + * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n + * \ref RTC_RIER_AIER_Msk : Alarm interrupt \n + * \ref RTC_RIER_TIER_Msk : Tick interrupt \n + * \ref RTC_RIER_SNOOPIER_Msk : Snooper Pin Event Detection Interrupt\n + * + * @return None + * + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + int32_t i32TimeoutCnt = SystemCoreClock; // 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + RTC->RIER |= u32IntFlagMask; +} + +/** + * @brief The function is used to disable specified interrupt. + * + * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n + * \ref RTC_RIER_AIER_Msk : Alarm interrupt \n + * \ref RTC_RIER_TIER_Msk : Tick interrupt \n + * \ref RTC_RIER_SNOOPIER_Msk : Snooper Pin Event Detection Interrupt\n + * + * @return None + * + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + int32_t i32TimeoutCnt = SystemCoreClock; // 1 second timeout + + RTC->AER = RTC_WRITE_KEY; + while(!(RTC->AER & RTC_AER_ENF_Msk)) { + RTC->AER = RTC_WRITE_KEY; + if(i32TimeoutCnt-- <= 0) + break; + } + + if(u32IntFlagMask & RTC_RIER_TIER_Msk) + { + RTC->RIER &= ~RTC_RIER_TIER_Msk; + RTC->RIIR = RTC_RIIR_TIF_Msk; + } + + if(u32IntFlagMask & RTC_RIER_AIER_Msk) + { + RTC->RIER &= ~RTC_RIER_AIER_Msk; + RTC->RIIR = RTC_RIIR_AIF_Msk; + } + + if(u32IntFlagMask & RTC_RIER_SNOOPIER_Msk) + { + RTC->RIER &= ~RTC_RIER_SNOOPIER_Msk; + RTC->RIIR = RTC_RIIR_SNOOPIF_Msk; + } +} + +/** + * @brief Disable RTC clock. + * + * @return None + * + */ +void RTC_Close (void) +{ + CLK->APBCLK &= ~CLK_APBCLK_RTC_EN_Msk; +} + + +/*@}*/ /* end of group NANO100_RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_RTC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + + diff --git a/program/Library/StdDriver/src/sc.c b/program/Library/StdDriver/src/sc.c new file mode 100644 index 0000000..4f1eb04 --- /dev/null +++ b/program/Library/StdDriver/src/sc.c @@ -0,0 +1,275 @@ +/**************************************************************************//** + * @file sc.c + * @version V1.00 + * $Revision: 6 $ + * $Date: 15/07/31 7:30p $ + * @brief Nano100 series Smartcard(SC) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined +/// @cond HIDDEN_SYMBOLS +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0, 0, 0}; + +/// @endcond /* HIDDEN_SYMBOLS */ + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SC_Driver SC Driver + @{ +*/ + + +/** @addtogroup NANO100_SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief This function indicates specified smartcard slot status + * @param[in] sc Base address of smartcard module + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + // put conditions into two variable to remove IAR compilation warning + uint32_t cond1 = ((sc->PINCSR & SC_PINCSR_CD_PIN_ST_Msk) >> SC_PINCSR_CD_PIN_ST_Pos); + uint32_t cond2 = ((sc->PINCSR & SC_PINCSR_CD_LEV_Msk) >> SC_PINCSR_CD_LEV_Pos); + + if(sc == SC0 && u32CardStateIgnore[0] == 1) + return TRUE; + else if(sc == SC1 && u32CardStateIgnore[1] == 1) + return TRUE; + else if(sc == SC2 && u32CardStateIgnore[2] == 1) + return TRUE; + else if(cond1 != cond2) + return FALSE; + else + return TRUE; +} + +/** + * @brief This function reset both transmit and receive FIFO of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ClearFIFO(SC_T *sc) +{ + sc->ALTCTL |= (SC_ALTCTL_TX_RST_Msk | SC_ALTCTL_RX_RST_Msk); +} + +/** + * @brief This function disable specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_Close(SC_T *sc) +{ + sc->IER = 0; + sc->PINCSR = 0; + sc->ALTCTL = 0; + sc->CTL = 0; +} + +/** + * @brief This function initialized smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card absent. Could be + * - \ref SC_PIN_STATE_HIGH + * - \ref SC_PIN_STATE_LOW + * - \ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present + * @param[in] u32PWR Power off polarity, select the PWR pin state which could set smartcard VCC to high level. Could be + * - \ref SC_PIN_STATE_HIGH + * - \ref SC_PIN_STATE_LOW + * @return None + */ +void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR) +{ + uint32_t u32Reg = 0, u32Intf; + + if(sc == SC0) + u32Intf = 0; + else if(sc == SC1) + u32Intf = 1; + else + u32Intf = 2; + + if(u32CD != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CD ? 0: SC_PINCSR_CD_LEV_Msk; + u32CardStateIgnore[u32Intf] = 0; + } + else + { + u32CardStateIgnore[u32Intf] = 1; + } + u32Reg |= u32PWR ? 0 : SC_PINCSR_POW_INV_Msk; + sc->PINCSR = u32Reg; + sc->CTL = SC_CTL_SC_CEN_Msk; +} + +/** + * @brief This function reset specified smartcard module to its default state for activate smartcard + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if(sc == SC0) + u32Intf = 0; + else if(sc == SC1) + u32Intf = 1; + else + u32Intf = 2; + + // Reset FIFO + sc->ALTCTL |= (SC_ALTCTL_TX_RST_Msk | SC_ALTCTL_RX_RST_Msk); + // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) + sc->CTL &= ~(SC_CTL_RX_FTRI_LEV_Msk | + SC_CTL_CD_DEB_SEL_Msk | + SC_CTL_TX_ERETRY_Msk | + SC_CTL_TX_ERETRY_EN_Msk | + SC_CTL_RX_ERETRY_Msk | + SC_CTL_RX_ERETRY_EN_Msk); + // Enable auto convention, and all three smartcard internal timers + sc->CTL |= SC_CTL_AUTO_CON_EN_Msk | SC_CTL_TMR_SEL_Msk; + // Disable Rx timeout + sc->RFTMR = 0; + // 372 clocks per ETU by default + sc->ETUCR = 371; + // Enable auto de-activation while card removal + sc->PINCSR = (sc->PINCSR & ~SC_PINCSR_POW_EN_Msk) | SC_PINCSR_ADAC_CD_EN_Msk; + + /* Enable necessary interrupt for smartcard operation */ + if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore + sc->IER = (SC_IER_RDA_IE_Msk | + SC_IER_TERR_IE_Msk | + SC_IER_TMR0_IE_Msk | + SC_IER_TMR1_IE_Msk | + SC_IER_TMR2_IE_Msk | + SC_IER_BGT_IE_Msk | + SC_IER_ACON_ERR_IE_Msk); + else + sc->IER = (SC_IER_RDA_IE_Msk | + SC_IER_TERR_IE_Msk | + SC_IER_TMR0_IE_Msk | + SC_IER_TMR1_IE_Msk | + SC_IER_TMR2_IE_Msk | + SC_IER_BGT_IE_Msk | + SC_IER_CD_IE_Msk | + SC_IER_ACON_ERR_IE_Msk); + + return; +} + +/** + * @brief This function block guard time (BGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32 + * @return None + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos); +} + +/** + * @brief This function character guard time (CGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267 + * @return None + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + u32CGT -= sc->CTL & SC_CTL_SLEN_Msk ? 11: 12; + sc->EGTR = u32CGT; +} + +/** + * @brief This function stop all smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + * @note This function stop the timers within smartcard module, \b not timer module + */ +void SC_StopAllTimer(SC_T *sc) +{ + sc->ALTCTL &= ~(SC_ALTCTL_TMR0_SEN_Msk | SC_ALTCTL_TMR1_SEN_Msk | SC_ALTCTL_TMR2_SEN_Msk); +} + +/** + * @brief This function configure and start a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs + * @return None + * @note This function start the timer within smartcard module, \b not timer module + * @note Depend on the timer operating mode, timer may not start counting immediately + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMR0_CNT_Msk & (u32ETUCount - 1)); + + if(u32TimerNum == 0) + { + sc->TMR0 = reg; + sc->ALTCTL |= SC_ALTCTL_TMR0_SEN_Msk; + } + else if(u32TimerNum == 1) + { + sc->TMR1 = reg; + sc->ALTCTL |= SC_ALTCTL_TMR1_SEN_Msk; + } + else // timer 2 + { + sc->TMR2 = reg; + sc->ALTCTL |= SC_ALTCTL_TMR2_SEN_Msk; + } +} + +/** + * @brief This function stop a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2. + * @return None + * @note This function stop the timer within smartcard module, \b not timer module + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + if(u32TimerNum == 0) + sc->ALTCTL &= ~SC_ALTCTL_TMR0_SEN_Msk; + else if(u32TimerNum == 1) + sc->ALTCTL &= ~SC_ALTCTL_TMR1_SEN_Msk; + else // timer 2 + sc->ALTCTL &= ~SC_ALTCTL_TMR2_SEN_Msk; +} + + + +/*@}*/ /* end of group NANO100_SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SC_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/scuart.c b/program/Library/StdDriver/src/scuart.c new file mode 100644 index 0000000..e3e2920 --- /dev/null +++ b/program/Library/StdDriver/src/scuart.c @@ -0,0 +1,215 @@ +/**************************************************************************//** + * @file scuart.c + * @version V1.00 + * $Revision: 5 $ + * $Date: 15/05/14 11:14a $ + * @brief Nano100 series Smartcard UART mode (SCUART) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SCUART_Driver SCUART Driver + @{ +*/ + + +/** @addtogroup NANO100_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief The function is used to disable smartcard interface UART mode. + * @param sc The base address of smartcard module. + * @return None + */ +void SCUART_Close(SC_T* sc) +{ + sc->IER = 0; + sc->UACTL = 0; + sc->CTL = 0; + +} + +/// @cond HIDDEN_SYMBOLS +/** + * @brief This function returns module clock of specified SC interface + * @param[in] sc The base address of smartcard module. + * @return Module clock of specified SC interface + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc = (CLK->CLKSEL2 & CLK_CLKSEL2_SC_S_Msk) >> CLK_CLKSEL2_SC_S_Pos; + uint32_t u32Clk; + + // Get smartcard module clock + if(u32ClkSrc == 0) + u32Clk = __HXT; + else if(u32ClkSrc == 1) + u32Clk = CLK_GetPLLClockFreq(); + else + u32Clk = __HIRC12M; + + if(sc == SC0) + u32Clk /= ((CLK->CLKDIV0 & CLK_CLKDIV0_SC0_N_Msk) >> CLK_CLKDIV0_SC0_N_Pos) + 1; + else if(sc == SC1) + u32Clk /= (CLK->CLKDIV1 & CLK_CLKDIV1_SC1_N_Msk) + 1; + else // SC2 + u32Clk /= ((CLK->CLKDIV1 & CLK_CLKDIV1_SC2_N_Msk) >> CLK_CLKDIV1_SC2_N_Pos) + 1; + + return u32Clk; +} + +/// @endcond HIDDEN_SYMBOLS + +/** + * @brief This function use to enable smartcard module UART mode and set baudrate. + * @param[in] sc The base address of smartcard module. + * @param[in] u32baudrate Target baudrate of smartcard module. + * @return Actual baudrate of smartcard mode + * @details This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SC_S(CLKSEL2[19:18]) SC_DIV is controlled by SC0_N(CLKDIV0[31:28]), + * SC1_N(CLKDIV1[3:0]), and SC2_N(CLKDIV1[7:4]). Since the baudrate divider is + * 12-bit wide and must be larger than 4, (clock source / baudrate) must be + * larger or equal to 5 and smaller or equal to 4096. Otherwise this function + * cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + // Calculate divider for target baudrate + u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1; + + sc->CTL = SC_CTL_SC_CEN_Msk | SC_CTL_SLEN_Msk; // Enable smartcard interface and stop bit = 1 + sc->UACTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UACTL_UA_MODE_EN_Msk; // Enable UART mode, disable parity and 8 bit per character + sc->ETUCR = u32Div; + + return(u32Clk / (u32Div + 1)); +} + +/** + * @brief The function is used to read Rx data from RX FIFO. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data + * @param[in] u32ReadBytes Target number of characters to receive + * @return Actual character number reads to buffer + * @note This function does not block and return immediately if there's no data available + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc)) // no data available + { + break; + } + pu8RxBuf[u32Count] = SCUART_READ(sc); // get data from FIFO + } + + return u32Count; +} + +/** + * @brief This function use to config smartcard UART mode line setting. + * @param[in] sc The base address of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * @return Actual baudrate of smartcard + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SC_S(CLKSEL2[19:18]) SC_DIV is controlled by SC0_N(CLKDIV0[31:28]), + * SC1_N(CLKDIV1[3:0]), and SC2_N(CLKDIV1[7:4]). Since the baudrate divider is + * 12-bit wide and must be larger than 4, (clock source / baudrate) must be + * larger or equal to 5 and smaller or equal to 4096. Otherwise this function + * cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0) // keep original baudrate setting + { + u32Div = sc->ETUCR & SC_ETUCR_ETU_RDIV_Msk; + } + else + { + // Calculate divider for target baudrate + u32Div = (u32Clk + (u32Baudrate >> 1) - 1)/ u32Baudrate - 1; + sc->ETUCR = u32Div; + } + + sc->CTL = u32StopBits | SC_CTL_SC_CEN_Msk; // Set stop bit + sc->UACTL = u32Parity | u32DataWidth | SC_UACTL_UA_MODE_EN_Msk; // Set character width and parity + + return(u32Clk / (u32Div + 1)); +} + +/** + * @brief This function use to set receive timeout count. + * @param[in] sc The base address of smartcard module. + * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable timeout counter + * @return None + * @details The time-out counter resets and starts counting whenever the RX buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RFTMR = u32TOC; +} + + +/** + * @brief This function is to write data into transmit FIFO to send data out. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * @return None + * @note This function blocks until all data write into FIFO + */ +void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes) +{ + uint32_t u32Count; + int32_t i32TimeoutCnt = SystemCoreClock/10; + + for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) + { + while(SCUART_GET_TX_FULL(sc)) { // Wait 'til FIFO not full + if(i32TimeoutCnt-- <= 0) + break; + } + sc->THR = pu8TxBuf[u32Count]; // Write 1 byte to FIFO + } +} + + +/*@}*/ /* end of group NANO100_SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SCUART_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/spi.c b/program/Library/StdDriver/src/spi.c new file mode 100644 index 0000000..584668c --- /dev/null +++ b/program/Library/StdDriver/src/spi.c @@ -0,0 +1,339 @@ +/****************************************************************************//** + * @file spi.c + * @version V0.10 + * $Revision: 7 $ + * $Date: 15/05/28 1:33p $ + * @brief NANO100 series SPI driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +/** + * @brief This function make SPI module be ready to transfer. + * By default, the SPI transfer sequence is MSB first and + * the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the SPI clock + * divider setting will be 0. + * @param[in] spi is the base address of SPI module. + * @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref SPI_MASTER + * - \ref SPI_SLAVE + * @param[in] u32SPIMode decides the transfer timing. Valid values are: + * - \ref SPI_MODE_0 + * - \ref SPI_MODE_1 + * - \ref SPI_MODE_2 + * - \ref SPI_MODE_3 + * @param[in] u32DataWidth decides the data width of a SPI transaction. + * @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + if(u32DataWidth == 32) + u32DataWidth = 0; + + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode); + + return ( SPI_SetBusClock(spi, u32BusClock) ); +} + +/** + * @brief Reset SPI module and disable SPI peripheral clock. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_Close(SPI_T *spi) +{ + /* Reset SPI */ + if(spi == SPI0) + { + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk; + } + else if(spi == SPI1) + { + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk; + } + else + { + SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI2_RST_Msk; + SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk; + } +} + +/** + * @brief Clear Rx FIFO buffer. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FFCTL |= SPI_FFCTL_RX_CLR_Msk; +} + +/** + * @brief Clear Tx FIFO buffer. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FFCTL |= SPI_FFCTL_TX_CLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSR &= ~SPI_SSR_AUTOSS_Msk; +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] spi is the base address of SPI module. + * @param[in] u32SSPinMask specifies slave select pins. (SPI_SS) + * @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are: + * - \ref SPI_SS0_ACTIVE_HIGH + * - \ref SPI_SS0_ACTIVE_LOW + * - \ref SPI_SS1_ACTIVE_HIGH + * - \ref SPI_SS1_ACTIVE_LOW + * @return none + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk; +} + +/** + * @brief Set the SPI bus clock. Only available in Master mode. + * @param[in] spi is the base address of SPI module. + * @param[in] u32BusClock is the expected frequency of SPI bus clock. + * @return Actual frequency of SPI peripheral clock. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32Div = 0; + + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + + if(u32BusClock > u32ClkSrc) + u32BusClock = u32ClkSrc; + + if(u32BusClock != 0 ) + { + u32Div = (u32ClkSrc / u32BusClock) - 1; + if(u32Div > SPI_CLKDIV_DIVIDER1_Msk) + u32Div = SPI_CLKDIV_DIVIDER1_Msk; + } + else + u32Div = 0; + + spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div; + + return ( u32ClkSrc / (u32Div+1) ); +} + +/** + * @brief Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations. + * @param[in] spi is the base address of SPI module. + * @param[in] u32TxThreshold decides the Tx FIFO threshold. + * @param[in] u32RxThreshold decides the Rx FIFO threshold. + * @return none + */ +void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FFCTL = ((spi->FFCTL & ~(SPI_FFCTL_TX_THRESHOLD_Msk | SPI_FFCTL_RX_THRESHOLD_Msk)) | + (u32TxThreshold << SPI_FFCTL_TX_THRESHOLD_Pos) | + (u32RxThreshold << SPI_FFCTL_RX_THRESHOLD_Pos)); + + spi->CTL |= SPI_CTL_FIFOM_Msk; +} + +/** + * @brief Disable FIFO mode. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_DisableFIFO(SPI_T *spi) +{ + spi->CTL &= ~SPI_CTL_FIFOM_Msk; +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi is the base address of SPI module. + * @return Actual SPI bus clock frequency. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK) + u32ClkSrc = CLK_GetHCLKFreq(); + else + u32ClkSrc = CLK_GetPLLClockFreq(); + } + + u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk; + return (u32ClkSrc / (u32Div + 1)); +} + +/** + * @brief Enable FIFO related interrupts specified by u32Mask parameter. + * @param[in] spi is the base address of SPI module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref SPI_IE_MASK + * - \ref SPI_SSTA_INTEN_MASK + * - \ref SPI_FIFO_TX_INTEN_MASK + * - \ref SPI_FIFO_RX_INTEN_MASK + * - \ref SPI_FIFO_RXOVR_INTEN_MASK + * - \ref SPI_FIFO_TIMEOUT_INTEN_MASK + * @return none + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK) + spi->CTL |= SPI_CTL_INTEN_Msk; + + if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK) + spi->SSR |= SPI_SSR_SSTA_INTEN_Msk; + + if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK) + spi->FFCTL |= SPI_FFCTL_TX_INTEN_Msk; + + if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK) + spi->FFCTL |= SPI_FFCTL_RX_INTEN_Msk; + + if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK) + spi->FFCTL |= SPI_FFCTL_RXOVR_INTEN_Msk; + + if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK) + spi->FFCTL |= SPI_FFCTL_TIMEOUT_EN_Msk; +} + +/** + * @brief Disable FIFO related interrupts specified by u32Mask parameter. + * @param[in] spi is the base address of SPI module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref SPI_IE_MASK + * - \ref SPI_SSTA_INTEN_MASK + * - \ref SPI_FIFO_TX_INTEN_MASK + * - \ref SPI_FIFO_RX_INTEN_MASK + * - \ref SPI_FIFO_RXOVR_INTEN_MASK + * - \ref SPI_FIFO_TIMEOUT_INTEN_MASK + * @return none + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK) + spi->CTL &= ~SPI_CTL_INTEN_Msk; + + if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK) + spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk; + + if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK) + spi->FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk; + + if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK) + spi->FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk; + + if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK) + spi->FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk; + + if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK) + spi->FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk; +} + +/** + * @brief Enable wake-up function. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_EnableWakeup(SPI_T *spi) +{ + spi->CTL |= SPI_CTL_WKEUP_EN_Msk; +} + +/** + * @brief Disable wake-up function. + * @param[in] spi is the base address of SPI module. + * @return none + */ +void SPI_DisableWakeup(SPI_T *spi) +{ + spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk; +} + +/*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SPI_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/sys.c b/program/Library/StdDriver/src/sys.c new file mode 100644 index 0000000..5539010 --- /dev/null +++ b/program/Library/StdDriver/src/sys.c @@ -0,0 +1,199 @@ +/**************************************************************************//** + * @file sys.c + * @version V1.00 + * $Revision: 8 $ + * $Date: 15/06/17 4:49p $ + * @brief NANO100 series SYS driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "Nano100Series.h" +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup NANO100_SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief This function clear the selected system reset source + * @param[in] u32Src is system reset source + * @return None + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RST_SRC |= u32Src; +} + +/** + * @brief This function get Brown-out detector output status + * @param None + * @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0. + * 1: System voltage is lower than BOD_VL setting. + * Note : If the BOD_EN is 0, this function always return 0. + */ +uint32_t SYS_GetBODStatus() +{ + return (SYS->BODSTS); +} + +/** + * @brief This function get the system reset source register value + * @param None + * @return Reset source + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RST_SRC); +} + +/** + * @brief This function check register write-protection bit setting + * @param None + * @return 0: Write-protection function is disabled. + * 1: Write-protection function is enabled. + */ +uint32_t SYS_IsRegLocked(void) +{ + return !(SYS->RegLockAddr & SYS_RegLockAddr_RegUnLock_Msk); +} + +/** + * @brief This function get product ID. + * @param None + * @return Product ID + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief This function reset chip. + * @param None + * @return None + */ +void SYS_ResetChip(void) +{ + SYS->IPRST_CTL1 |= SYS_IPRST_CTL1_CHIP_RST_Msk; +} + +/** + * @brief This function reset CPU. + * @param None + * @return None + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST_CTL1 |= SYS_IPRST_CTL1_CPU_RST_Msk; +} + +/** + * @brief This function reset selected modules. + * @param[in] u32ModuleIndex is module index. Including : + * - \ref CHIP_RST + * - \ref CPU_RST + * - \ref DMA_RST + * - \ref EBI_RST + * - \ref SC1_RST + * - \ref SC0_RST + * - \ref I2S_RST + * - \ref ADC_RST + * - \ref USBD_RST + * - \ref DAC_RST + * - \ref PWM1_RST + * - \ref PWM0_RST + * - \ref UART1_RST + * - \ref UART0_RST + * - \ref SPI2_RST + * - \ref SPI1_RST + * - \ref SPI0_RST + * - \ref I2C1_RST + * - \ref I2C0_RST + * - \ref TMR3_RST + * - \ref TMR2_RST + * - \ref TMR1_RST + * - \ref TMR0_RST + * - \ref GPIO_RST + * @return None + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + *(volatile uint32_t *)((uint32_t)&(SYS->IPRST_CTL1) + (u32ModuleIndex>>24)) |= 1<<(u32ModuleIndex & 0x00ffffff); + *(volatile uint32_t *)((uint32_t)&(SYS->IPRST_CTL1) + (u32ModuleIndex>>24)) &= ~(1<<(u32ModuleIndex & 0x00ffffff)); +} + +/** + * @brief This function configure BOD function. + * Configure BOD reset or interrupt mode and set Brown-out voltage level. + * Enable Brown-out function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD25_RST_EN_Msk or \ref SYS_BODCTL_BOD25_INT_EN_Msk + * - \ref SYS_BODCTL_BOD20_RST_EN_Msk or \ref SYS_BODCTL_BOD20_INT_EN_Msk + * - \ref SYS_BODCTL_BOD17_RST_EN_Msk or \ref SYS_BODCTL_BOD17_INT_EN_Msk + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BOD25_EN_Msk + * - \ref SYS_BODCTL_BOD20_EN_Msk + * - \ref SYS_BODCTL_BOD17_EN_Msk + * + * @return None + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + SYS->BODCTL = (SYS->BODCTL & ~0xFFF) | (i32Mode | u32BODLevel); +} + +/** + * @brief This function disable BOD function. + * @param None + * @return None + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL = SYS->BODCTL & ~(SYS_BODCTL_BOD25_EN_Msk | SYS_BODCTL_BOD20_EN_Msk | SYS_BODCTL_BOD17_EN_Msk); +} + +/** + * @brief This function enable HIRC trim function. + * @param[in] u32TrimSel is trim frequency selection. Including : + * - \ref SYS_IRCTRIMCTL_TRIM_11_0592M + * - \ref SYS_IRCTRIMCTL_TRIM_12M + * - \ref SYS_IRCTRIMCTL_TRIM_12_288M + * @param[in] u32TrimEnInt is HIRC trim interrupt selection. Including : + * - \ref SYS_IRCTRIMIEN_FAIL_EN + * - \ref SYS_IRCTRIMIEN_32KERR_EN + * - \ref SYS_IRCTRIMIEN_DISABLE + * @return None + */ +void SYS_EnableIRCTrim(uint32_t u32TrimSel,uint32_t u32TrimEnInt) +{ + SYS->IRCTRIMIEN = (SYS->IRCTRIMIEN & ~(SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk|SYS_IRCTRIMIEN_32K_ERR_IEN_Msk)) | u32TrimEnInt; + SYS->IRCTRIMCTL = (SYS->IRCTRIMCTL & ~SYS_IRCTRIMCTL_TRIM_SEL_Msk)|u32TrimSel; +} + +/** + * @brief This function disable HIRC trim function. + * @param None + * @return None + */ +void SYS_DisableIRCTrim(void) +{ + SYS->IRCTRIMCTL = 0; +} + +/*@}*/ /* end of group NANO100_SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_SYS_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/timer.c b/program/Library/StdDriver/src/timer.c new file mode 100644 index 0000000..8b45606 --- /dev/null +++ b/program/Library/StdDriver/src/timer.c @@ -0,0 +1,299 @@ +/**************************************************************************//** + * @file timer.c + * @version V1.00 + * $Revision: 11 $ + * $Date: 15/06/23 5:15p $ + * @brief Nano100 series TIMER driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_TIMER_Driver TIMER Driver + @{ +*/ + + +/** @addtogroup NANO100_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief This API is used to configure timer to operate in specified mode + * and frequency. If timer cannot work in target frequency, a closest + * frequency will be chose and returned. + * @param[in] timer The base address of Timer module + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * @return Real Timer working frequency + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0, u32Prescale = 0; + + // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0 + if(u32Freq > (u32Clk / 2)) + { + u32Cmpr = 2; + } + else + { + if(u32Clk >= 0x2000000) + { + u32Prescale = 3; // real prescaler value is 4 + u32Clk >>= 2; + } + else if(u32Clk >= 0x1000000) + { + u32Prescale = 1; // real prescaler value is 2 + u32Clk >>= 1; + } + u32Cmpr = u32Clk / u32Freq; + } + timer->CMPR = u32Cmpr; + timer->PRECNT = u32Prescale; + timer->CTL = u32Mode; + + + return(u32Clk / (u32Cmpr * (u32Prescale + 1))); +} + +/** + * @brief This API stops Timer counting and disable the Timer interrupt function + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0; + timer->IER = 0; +} + +/** + * @brief This API is used to create a delay loop for u32usec micro seconds + * @param[in] timer The base address of Timer module + * @param[in] u32Usec Delay period in micro seconds with 10 usec every step. Valid values are between 10~1000000 (10 micro second ~ 1 second) + * @return None + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk; + long long u64Cmpr; + + // Clear current timer configuration + timer->CTL = 0; + + if(u32Clk == 10000) // min delay is 100us if timer clock source is LIRC 10k + { + u32Usec = ((u32Usec + 99) / 100) * 100; + } + else // 10 usec every step + { + u32Usec = ((u32Usec + 9) / 10) * 10; + } + + if(u32Clk >= 0x2000000) + { + u32Prescale = 3; // real prescaler value is 4 + u32Clk >>= 2; + } + else if(u32Clk >= 0x1000000) + { + u32Prescale = 1; // real prescaler value is 2 + u32Clk >>= 1; + } + + // u32Usec * u32Clk might overflow if using uint32_t + u64Cmpr = ((long long)u32Usec * (long long)u32Clk) / (long long)1000000; + + timer->CMPR = (uint32_t)u64Cmpr; + timer->PRECNT = u32Prescale; + timer->CTL = TIMER_CTL_TMR_EN_Msk; // one shot mode + + // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. + for(; delay > 0; delay--) + { + __NOP(); + } + + delay = (SystemCoreClock / 1000000) * u32Usec * 10; + + while ((timer->CTL & TIMER_CTL_TMR_ACT_Msk) && (delay-- > 0)); +} + +/** + * @brief This API is used to enable timer capture function with specified mode and capture edge + * @param[in] timer The base address of Timer module + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_TRIGGER_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture edge. Possible values are + * - \ref TIMER_CAPTURE_FALLING_EDGE + * - \ref TIMER_CAPTURE_RISING_EDGE + * - \ref TIMER_CAPTURE_FALLING_THEN_RISING_EDGE + * - \ref TIMER_CAPTURE_RISING_THEN_FALLING_EDGE + * @return None + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + + timer->CTL = (timer->CTL & ~(TIMER_CTL_TCAP_MODE_Msk | + TIMER_CTL_TCAP_CNT_MODE_Msk | + TIMER_CTL_TCAP_EDGE_Msk)) | + u32CapMode | u32Edge | TIMER_CTL_TCAP_EN_Msk; +} + +/** + * @brief This API is used to disable the Timer capture function + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_TCAP_EN_Msk; + +} + +/** + * @brief This function is used to enable the Timer counter function with specify detection edge + * @param[in] timer The base address of Timer module + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_RISING_EDGE, or + * - \ref TIMER_COUNTER_FALLING_EDGE + * @return None + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->CTL = (timer->CTL & ~TIMER_CTL_EVENT_EDGE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EVENT_EN_Msk; +} + +/** + * @brief This API is used to disable the Timer event counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EVENT_EN_Msk; +} + +/** + * @brief This API is used to get the clock frequency of Timer + * @param[in] timer The base address of Timer module + * @return Timer clock frequency + * @note This API cannot return correct clock rate if timer source is external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src; + const uint32_t au32Clk[] = {__HXT, __LXT, __LIRC, 0}; // we don't know actual clock if external pin is clock source, set to 0 here + + if(timer == TIMER0) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos; + else if(timer == TIMER1) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos; + else if(timer == TIMER2) + u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR2_S_Msk) >> CLK_CLKSEL2_TMR2_S_Pos; + else // Timer 3 + u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR3_S_Msk) >> CLK_CLKSEL2_TMR3_S_Pos; + + if(u32Src < 4) + return au32Clk[u32Src]; + else + return __HIRC; + +} + +/** + * @brief This function is used to enable the Timer frequency counter function + * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2 + * @param[in] u32DropCount This parameter has no effect in Nano100 series BSP + * @param[in] u32Timeout This parameter has no effect in Nano100 series BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * @return None + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; // store the timer base to configure compare value + + t = (timer == TIMER0) ? TIMER1 : TIMER3; + + t->CMPR = 0xFFFFFF; + t->IER = u32EnableInt ? TIMER_IER_TCAP_IE_Msk : 0; + timer->CTL = TIMER_CTL_INTR_TRG_EN_Msk | TIMER_CTL_TMR_EN_Msk; + + return; +} +/** + * @brief This function is used to disable the Timer frequency counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTR_TRG_EN_Msk; +} + +/** + * @brief This function is used to select the interrupt source used to trigger other modules. + * @param[in] timer The base address of Timer module + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TIMEOUT_TRIGGER + * - \ref TIMER_CAPTURE_TRIGGER + * @return None + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->CTL = (timer->CTL & ~TIMER_CTL_CAP_TRG_EN_Msk) | u32Src; +} + +/** + * @brief This function is used to set modules trigger by timer interrupt + * @param[in] timer The base address of Timer module + * @param[in] u32Mask The mask of modules (ADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_CTL_PDMA_TEEN_Msk, + * - \ref TIMER_CTL_ADC_TEEN_Msk, and + * - \ref TIMER_CTL_DAC_TEEN_Msk, + * @return None + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->CTL = (timer->CTL & ~(TIMER_CTL_PDMA_TEEN_Msk | TIMER_CTL_DAC_TEEN_Msk | TIMER_CTL_ADC_TEEN_Msk)) | u32Mask; +} + +/*@}*/ /* end of group NANO100_TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_TIMER_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/uart.c b/program/Library/StdDriver/src/uart.c new file mode 100644 index 0000000..42127e2 --- /dev/null +++ b/program/Library/StdDriver/src/uart.c @@ -0,0 +1,429 @@ +/**************************************************************************//** + * @file uart.c + * @version V1.00 + * $Revision: 11 $ + * $Date: 15/06/26 1:28p $ + * @brief Nano100 series Smartcard UART mode (UART) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_UART_Driver UART Driver + @{ +*/ + + +/** @addtogroup NANO100_UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ +/// @cond HIDDEN_SYMBOLS +extern uint32_t SysGet_PLLClockFreq(void); +/// @endcond /* HIDDEN_SYMBOLS */ + + +/** + * @brief The function is used to clear UART specified interrupt flag. + * + * @param[in] uart The base address of UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module.. + * + * @return None + */ +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + + if(u32InterruptFlag & UART_ISR_RLS_IS_Msk) /* clear Receive Line Status Interrupt */ + { + uart->FSR |= UART_FSR_BI_F_Msk | UART_FSR_FE_F_Msk | UART_FSR_PE_F_Msk; + uart->TRSR |= UART_TRSR_RS485_ADDET_F_Msk; + } + + if(u32InterruptFlag & UART_ISR_MODEM_IS_Msk) /* clear Modem Interrupt */ + uart->MCSR |= UART_MCSR_DCT_F_Msk; + + if(u32InterruptFlag & UART_ISR_BUF_ERR_IS_Msk) /* clear Buffer Error Interrupt */ + { + uart->FSR |= UART_FSR_RX_OVER_F_Msk | UART_FSR_TX_OVER_F_Msk; + } + + if(u32InterruptFlag & UART_ISR_WAKE_IS_Msk) /* clear wake up Interrupt */ + { + uart->ISR |= UART_ISR_WAKE_IS_Msk; + } + + if(u32InterruptFlag & UART_ISR_ABAUD_IS_Msk) /* clear auto-baud rate Interrupt */ + { + uart->TRSR |= UART_TRSR_ABAUD_TOUT_F_Msk | UART_TRSR_ABAUD_F_Msk; + } + + if(u32InterruptFlag & UART_ISR_LIN_IS_Msk) /* clear LIN break Interrupt */ + { + uart->TRSR |= UART_TRSR_LIN_TX_F_Msk | UART_TRSR_LIN_RX_F_Msk | UART_TRSR_BIT_ERR_F_Msk; + } + +} + + +/** + * @brief The function is used to disable UART. + * + * @param[in] uart The base address of UART module. + * + * @return None + */ +void UART_Close(UART_T* uart) +{ + uart->IER = 0; +} + + +/** + * @brief The function is used to disable UART auto flow control. + * + * @param[in] uart The base address of UART module. + * + * @return None + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->CTL &= ~(UART_CTL_AUTO_RTS_EN_Msk | UART_CTL_AUTO_CTS_EN_Msk); +} + + +/** + * @brief The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + * + * @param[in] uart The base address of UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_IER_LIN_IE_Msk : LIN interrupt + * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt + * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt + * - \ref UART_IER_ABAUD_IE_Msk : Auto Baud-rate interrupt + * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt + * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt + * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt + * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt + * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt + * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt + * + * @return None + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag ) +{ + uart->IER &= ~ u32InterruptFlag; +} + + + +/** + * @brief The function is used to Enable UART auto flow control. + * + * @param[in] uart The base address of UART module. + * + * @return None + */ +void UART_EnableFlowCtrl(UART_T* uart ) +{ + uart->MCSR |= UART_MCSR_LEV_RTS_Msk | UART_MCSR_LEV_CTS_Msk; + uart->CTL |= UART_CTL_AUTO_RTS_EN_Msk | UART_CTL_AUTO_CTS_EN_Msk; +} + + +/** + * @brief The function is used to enable UART specified interrupt and disable NVIC UART IRQ. + * + * @param[in] uart The base address of UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_IER_LIN_IE_Msk : LIN interrupt + * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt + * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt + * - \ref UART_IER_ABAUD_IE_Msk : Auto Baud-rate interrupt + * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt + * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt + * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt + * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt + * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt + * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt + * + * @return None + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag ) +{ + uart->IER |= u32InterruptFlag; +} + + +/** + * @brief This function use to enable UART function and set baud-rate. + * + * @param[in] uart The base address of UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint8_t u8UartClkSrcSel; + uint32_t u32ClkTbl[4] = {__HXT, __LXT, 0, __HIRC12M}; + uint32_t u32Baud_Div; + uint32_t u32SrcFreq; + uint32_t u32SrcFreqDiv; + + u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos; + + u32SrcFreq = u32ClkTbl[u8UartClkSrcSel]; + + u32SrcFreqDiv = (((CLK->CLKDIV0 & CLK_CLKDIV0_UART_N_Msk) >> CLK_CLKDIV0_UART_N_Pos) + 1); + + if(u32SrcFreq == 0) + { + u32SrcFreq = SysGet_PLLClockFreq() / u32SrcFreqDiv; + } + else + { + u32SrcFreq = u32SrcFreq / u32SrcFreqDiv; + } + + uart->FUN_SEL = UART_FUNC_SEL_UART; + uart->TLCTL = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1 | + UART_TLCTL_RFITL_1BYTE | UART_TLCTL_RTS_TRI_LEV_1BYTE; + + if(u32baudrate != 0) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32baudrate); + + if(u32Baud_Div > 0xFFFF) + uart->BAUD = (UART_BAUD_MODE1 | UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32baudrate)); + else + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } +} + + +/** + * @brief The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + * + * @param[in] uart The base address of UART module. + * @param[out] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count: Receive byte count + * + */ +uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count=0; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0; + + while(uart->FSR & UART_FSR_RX_EMPTY_F_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if( u32delayno >= 0x40000000 ) + return FALSE; + } + pu8RxBuf[u32Count] = uart->RBR; /* Get Data from UART RX */ + } + + return u32Count; + +} + + +/** + * @brief This function use to config UART line setting. + * + * @param[in] uart The base address of UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * if u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * @param[in] u32parity The parity setting (odd/even/none) of UART module. + * @param[in] u32stop_bits The stop bit length (1/1.5 bit) of UART module. + * + * @return None + */ +void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint8_t u8UartClkSrcSel; + uint32_t u32ClkTbl[4] = {__HXT, __LXT, 0, __HIRC12M}; + uint32_t u32Baud_Div = 0; + uint32_t u32SrcFreq; + uint32_t u32SrcFreqDiv; + + u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos; + + u32SrcFreq = u32ClkTbl[u8UartClkSrcSel]; + + u32SrcFreqDiv = (((CLK->CLKDIV0 & CLK_CLKDIV0_UART_N_Msk) >> CLK_CLKDIV0_UART_N_Pos) + 1); + + if(u32SrcFreq == 0) + { + u32SrcFreq = SysGet_PLLClockFreq() / u32SrcFreqDiv; + } + else + { + u32SrcFreq = u32SrcFreq / u32SrcFreqDiv; + } + + if(u32baudrate != 0) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32baudrate); + + if(u32Baud_Div > 0xFFFF) + uart->BAUD = (UART_BAUD_MODE1 | UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32baudrate)); + else + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + + uart->TLCTL = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief This function use to set Rx timeout count. + * + * @param[in] uart The base address of UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + uart->TMCTL = (uart->TMCTL & ~UART_TMCTL_TOIC_Msk)| (u32TOC); + uart->IER |= UART_IER_RTO_IE_Msk; +} + + +/** + * @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + * + * @param[in] uart The base address of UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode. + * + * @return None + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint8_t u8UartClkSrcSel; + uint32_t u32ClkTbl[4] = {__HXT, __LXT, 0, __HIRC12M}; + uint32_t u32SrcFreq; + uint32_t u32SrcFreqDiv; + + u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos; + + u32SrcFreq = u32ClkTbl[u8UartClkSrcSel]; + + u32SrcFreqDiv = (((CLK->CLKDIV0 & CLK_CLKDIV0_UART_N_Msk) >> CLK_CLKDIV0_UART_N_Pos) + 1); + + if(u32SrcFreq == 0) + { + u32SrcFreq = SysGet_PLLClockFreq() / u32SrcFreqDiv; + } + else + { + u32SrcFreq = u32SrcFreq / u32SrcFreqDiv; + } + + uart->BAUD = UART_BAUD_MODE1 | UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32Buadrate); + + uart->IRCR &= ~UART_IRCR_INV_TX_Msk; + uart->IRCR |= UART_IRCR_INV_RX_Msk; + uart->IRCR = u32Direction ? uart->IRCR | UART_IRCR_TX_SELECT_Msk : uart->IRCR &~ UART_IRCR_TX_SELECT_Msk; + uart->FUN_SEL = (0x2 << UART_FUN_SEL_FUN_SEL_Pos); +} + + +/** + * @brief The function is used to set RS485 relative setting. + * + * @param[in] uart The base address of UART module. + * @param[in] u32Mode The operation mode( \ref UART_ALT_CTL_RS485_NMM_Msk / \ref UART_ALT_CTL_RS485_AUD_Msk / \ref UART_ALT_CTL_RS485_AAD_Msk). + * @param[in] u32Addr The RS485 address. + * + * @return None + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + uart->FUN_SEL = UART_FUNC_SEL_RS485; + uart->ALT_CTL = 0; + uart->ALT_CTL |= u32Mode | (u32Addr << UART_ALT_CTL_ADDR_PID_MATCH_Pos); +} + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - UART_ALT_CTL_LIN_TX_EN_Msk + * - UART_ALT_CTL_LIN_RX_EN_Msk + * - (UART_ALT_CTL_LIN_TX_EN_Msk|UART_ALT_CTL_LIN_RX_EN_Msk) + * @param[in] u32BreakLength The breakfield length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUN_SEL = UART_FUNC_SEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->FUN_SEL = UART_FUNC_SEL_LIN; + uart->ALT_CTL &= ~(UART_ALT_CTL_LIN_TX_BCNT_Msk | UART_ALT_CTL_LIN_RX_EN_Msk | UART_ALT_CTL_LIN_TX_EN_Msk); + uart->ALT_CTL |= u32BreakLength & UART_ALT_CTL_LIN_TX_BCNT_Msk; + uart->ALT_CTL |= u32Mode; +} + +/** + * @brief The function is to write data into TX buffer to transmit data by UART. + * + * @param[in] uart The base address of UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[in] u32WriteBytes The byte number of data. + * + * @return u32Count: transfer byte count + */ +uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count=0; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0; + while((uart->FSR & UART_FSR_TX_EMPTY_F_Msk) == 0) /* Wait Tx empty and Time-out manner */ + { + u32delayno++; + if( u32delayno >= 0x40000000 ) + return FALSE; + } + uart->THR = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + + return u32Count; + +} + + +/*@}*/ /* end of group NANO100_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_UART_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ + + + diff --git a/program/Library/StdDriver/src/usbd.c b/program/Library/StdDriver/src/usbd.c new file mode 100644 index 0000000..7414654 --- /dev/null +++ b/program/Library/StdDriver/src/usbd.c @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file usbd.c + * @brief NANO100 series USBD driver Sample file + * @version 2.0.0 + * @date 20, September, 2014 + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +/*! +#include "Nano100Series.h" + +/*--------------------------------------------------------------------------*/ +/* Global variables for Control Pipe */ +uint8_t g_usbd_SetupPacket[8] = {0}; +volatile uint8_t g_usbd_RemoteWakeupEn = 0; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static volatile uint8_t *g_usbd_CtrlInPointer = 0; +static volatile uint32_t g_usbd_CtrlInSize = 0; +static volatile uint8_t *g_usbd_CtrlOutPointer = 0; +static volatile uint32_t g_usbd_CtrlOutSize = 0; +static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0; +static volatile uint32_t g_usbd_UsbAddr = 0; +static volatile uint32_t g_usbd_CtrlMaxPktSize = 8; +static volatile uint32_t g_usbd_UsbAltInterface = 0; +static volatile uint32_t g_usbd_CtrlOutToggle = 0; +static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul; +volatile uint32_t g_usbd_UsbConfig = 0; +/** + * @endcond + */ + +S_USBD_INFO_T *g_usbd_sInfo; + +VENDOR_REQ g_usbd_pfnVendorRequest = NULL; +CLASS_REQ g_usbd_pfnClassRequest = NULL; +SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; +SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_u32EpStallLock = 0; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief USBD Initial, Enable clock and reset USB. + * @param[in] param Descriptor + * @param[in] pfnClassReq Class Request Callback Function + * @param[in] pfnSetInterface SetInterface Request Callback Function + * @retval None. + */ +void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_usbd_sInfo = param; + g_usbd_pfnClassRequest = pfnClassReq; + g_usbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + USBD->CTL = 0x29f; + USBD->PDMA |= USBD_PDMA_BYTEM_Msk; + /* Force SE0, and then clear it to connect*/ + USBD_SET_SE0(); +} + +/** + * @brief USBD Start + * + * @param None + * + * @return None + * + * @details This function is used to start transfer + */ +void USBD_Start(void) +{ + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + CLK_SysTickDelay(100000); + USBD_CLR_SE0(); +} + +/** + * @brief Get Setup Packet + * + * @param[in] buf Buffer pointer to store setup packet + * + * @return None + * + * @details This function is used to get Setup packet. + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_usbd_SetupPacket, 8); +} + +/** + * @brief Process Setup Packet + * + * @param None + * + * @return None + * + * @details This function is used to process Setup packet. + */ +void USBD_ProcessSetupPacket(void) +{ + g_usbd_CtrlOutToggle = 0; + // Setup packet process + USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8); + + switch (g_usbd_SetupPacket[0] & 0x60) /* request type */ + { + case REQ_STANDARD: // Standard + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: // Class + { + if (g_usbd_pfnClassRequest != NULL) + { + g_usbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: // Vendor + { + if (g_usbd_pfnVendorRequest != NULL) + { + g_usbd_pfnVendorRequest(); + } + break; + } + default: // reserved + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Get Descriptor request + * + * @param None + * + * @return None + * + * @details This function is used to process GetDescriptor request. + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + u32Len = 0; + u32Len = g_usbd_SetupPacket[7]; + u32Len <<= 8; + u32Len += g_usbd_SetupPacket[6]; + + switch (g_usbd_SetupPacket[3]) + { + // Get Device Descriptor + case DESC_DEVICE: + { + u32Len = Minimum(u32Len, LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len); + USBD_PrepareCtrlOut(0,0); + break; + } + // Get Configuration Descriptor + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len); + USBD_PrepareCtrlOut(0,0); + break; + } + // Get HID Descriptor + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; // u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) + u32Len = Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + USBD_PrepareCtrlOut(0,0); + break; + } + // Get Report Descriptor + case DESC_HID_RPT: + { + if (u32Len > g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]) + { + u32Len = g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len); + USBD_PrepareCtrlOut(0,0); + break; + } + // Get String Descriptor + case DESC_STRING: + { + // Get String Descriptor + if(g_usbd_SetupPacket[2] < 4) + { + if (u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]) + { + u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len); + USBD_PrepareCtrlOut(0, 0); + } + else + { + // Not support. Reply STALL. + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + } + break; + } + default: + // Not support. Reply STALL. + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process USB standard request + * + * @param None + * + * @return None + * + * @details This function is used to process USB Standard Request. + */ +void USBD_StandardRequest(void) +{ + /* clear global variables for new request */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + + if (g_usbd_SetupPacket[0] & 0x80) /* request data transfer direction */ + { + // Device to host + switch (g_usbd_SetupPacket[1]) + { + case GET_CONFIGURATION: + { + // Return current configuration setting + /* Data stage */ + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1); + /* Status stage */ + USBD_PrepareCtrlOut(0,0); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + break; + } + case GET_INTERFACE: + { + // Return current interface setting + /* Data stage */ + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1); + /* Status stage */ + USBD_PrepareCtrlOut(0,0); + break; + } + case GET_STATUS: + { + // Device + if(g_usbd_SetupPacket[0] == 0x80) + { + uint8_t u8Tmp; + + u8Tmp = 0; + if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x40) u8Tmp |= 1; // Self-Powered/Bus-Powered. + if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x20) u8Tmp |= (g_usbd_RemoteWakeupEn << 1); // Remote wake up + + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp; + } + // Interface + else if (g_usbd_SetupPacket[0] == 0x81) + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = 0; + // Endpoint + else if (g_usbd_SetupPacket[0] == 0x82) + { + uint8_t ep = g_usbd_SetupPacket[4] & 0xF; + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = USBD_GetStall(ep)? 1 : 0; + } + + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = 0; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2); + /* Status stage */ + USBD_PrepareCtrlOut(0,0); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + // Host to device + switch (g_usbd_SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + + int32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32EpStallLock is added to support it */ + epNum = g_usbd_SetupPacket[4] & 0xF; + for(i = 0; i < USBD_MAX_EP; i++) + { + if(((USBD->EP[i].CFG & 0xF) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0)) + USBD->EP[i].CFG &= ~(USBD_CFG_SSTALL_Msk | USBD_CFG_DSQ_SYNC_Msk); + } + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + g_usbd_RemoteWakeupEn = 0; + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + case SET_ADDRESS: + { + g_usbd_UsbAddr = g_usbd_SetupPacket[2]; + + // DATA IN for end of setup + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + case SET_CONFIGURATION: + { + g_usbd_UsbConfig = g_usbd_SetupPacket[2]; + + if (g_usbd_pfnSetConfigCallback) + g_usbd_pfnSetConfigCallback(); + + if (g_usbd_UsbConfig == 0) + { + int volatile i; + + /* Reset PID DATA0 */ + for (i = 2; i < USBD_MAX_EP; i++) + USBD->EP[i].CFG &= ~USBD_CFG_DSQ_SYNC_Msk; + } + + // DATA IN for end of setup + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + + case SET_FEATURE: + { + if (g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + USBD_SetStall(g_usbd_SetupPacket[4] & 0xF); + else if (g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + g_usbd_RemoteWakeupEn = 1; + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + + case SET_INTERFACE: + { + g_usbd_UsbAltInterface = g_usbd_SetupPacket[2]; + + if (g_usbd_pfnSetInterface != NULL) + g_usbd_pfnSetInterface(g_usbd_UsbAltInterface); + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0); + break; + } + + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare Control IN transaction + * + * @param[in] pu8Buf Control IN data pointer + * @param[in] u32Size IN transfer size + * + * @return None + * + * @details This function is used to prepare Control IN transfer + */ +void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size) +{ + if(u32Size > g_usbd_CtrlMaxPktSize) + { + // Data size > MXPLD + g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + } + else + { + // Data size <= MXPLD + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + USBD_SET_DATA1(EP0); + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Start Control IN transfer + * + * @param None + * + * @return None + * + * @details This function is used to start Control IN + */ +void USBD_CtrlIn(void) +{ + if(g_usbd_CtrlInSize) + { + // Process remained data + if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) + { + // Data size > MXPLD + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize; + } + else + { + // Data size <= MXPLD + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize); + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + } + } + else + { + // In ACK for Set address + if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) + { + if((USBD_GET_ADDR() != g_usbd_UsbAddr) && (USBD_GET_ADDR() == 0)) + { + USBD_SET_ADDR(g_usbd_UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_usbd_CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + } + } +} + +/** + * @brief Prepare Control OUT transaction + * + * @param[in] pu8Buf Control OUT data pointer + * @param[in] u32Size OUT transfer size + * + * @return None + * + * @details This function is used to prepare Control OUT transfer + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_usbd_CtrlOutPointer = pu8Buf; + g_usbd_CtrlOutSize = 0; + g_usbd_CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); +} + +/** + * @brief Start Control OUT transfer + * + * @param None + * + * @return None + * + * @details This function is used to start Control OUT + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + + if (g_usbd_CtrlOutToggle != (USBD->EPSTS & USBD_EPSTS_EPSTS1_Msk)) + { + g_usbd_CtrlOutToggle = USBD->EPSTS & USBD_EPSTS_EPSTS1_Msk; + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size); + g_usbd_CtrlOutPointer += u32Size; + g_usbd_CtrlOutSize += u32Size; + } + } + else + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } +} + +/** + * @brief Clear all software flags + * + * @param None + * + * @return None + * + * @details This function is used to clear all software control flag + */ +void USBD_SwReset(void) +{ + int i; + + // Reset all variables for protocol + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0; + g_usbd_CtrlOutPointer = 0; + g_usbd_CtrlOutSize = 0; + g_usbd_CtrlOutSizeLimit = 0; + memset(g_usbd_SetupPacket, 0, 8); + + /* Reset PID DATA0 */ + for (i=0; iEP[i].CFG &= ~USBD_CFG_DSQ_SYNC_Msk; + + // Reset USB device address + USBD_SET_ADDR(0); +} + + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_usbd_pfnVendorRequest = pfnVendorReq; +} +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_usbd_pfnSetConfigCallback = pfnSetConfigCallback; +} + +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_u32EpStallLock = u32EpBitmap; +} + + + diff --git a/program/Library/StdDriver/src/wdt.c b/program/Library/StdDriver/src/wdt.c new file mode 100644 index 0000000..e83a205 --- /dev/null +++ b/program/Library/StdDriver/src/wdt.c @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file wdt.c + * @version V1.00 + * $Revision: 2 $ + * $Date: 15/03/18 5:37p $ + * @brief Nano100 series WDT driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_WDT_Driver WDT Driver + @{ +*/ + + +/** @addtogroup NANO100_WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief This function make WDT module start counting with different time-out interval + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Reset delay period while WDT time-out happened. Valid values are: + * - \ref WDT_RESET_DELAY_3CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_1026CLK + * @param[in] u32EnableReset Enable WDT reset system function. Valid values are TRUE and FALSE + * @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are TRUE and FALSE + * @return None + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + + WDT->CTL = u32TimeoutInterval | u32ResetDelay | WDT_CTL_WTE_Msk | + (u32EnableReset << WDT_CTL_WTRE_Pos) | + (u32EnableWakeup << WDT_CTL_WTWKE_Pos); + return; +} + + +/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_WDT_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Library/StdDriver/src/wwdt.c b/program/Library/StdDriver/src/wwdt.c new file mode 100644 index 0000000..9a10698 --- /dev/null +++ b/program/Library/StdDriver/src/wwdt.c @@ -0,0 +1,67 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V1.00 + * $Revision: 3 $ + * $Date: 14/08/29 7:57p $ + * @brief Nano100 series WWDT driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_WWDT_Driver WWDT Driver + @{ +*/ + + +/** @addtogroup NANO100_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief This function make WWDT module start counting with different counter period and compared window value + * @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Window compared value. Valid values are between 0x0 to 0x3F + * @param[in] u32EnableInt Enable WWDT interrupt or not. Valid values are TRUE and FALSE + * @return None + * @note Application can call this function can only once after boot up + */ +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt) +{ + WWDT->IER = u32EnableInt; + WWDT->CR = u32PreScale | (u32CmpValue << WWDT_CR_WINCMP_Pos) | WWDT_CR_WWDTEN_Msk; + return; +} + + + + +/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_WDT_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ diff --git a/program/Makefile b/program/Makefile new file mode 100644 index 0000000..749520e --- /dev/null +++ b/program/Makefile @@ -0,0 +1,130 @@ +# ============================================================================= +# HERV Firmware - Nuvoton NANO100SE3BN (Cortex-M0) +# Eclipse(Nueclipse) -> VS Code + ARM-GCC 마이그레이션 +# +# 사용법: +# make : 빌드 (build/HERV.elf, .hex, .bin) +# make clean : 빌드 정리 +# make flash : Nu-Link 으로 플래시 (OpenOCD-Nuvoton 필요) +# make erase : 칩 erase +# make size : 메모리 사용량 출력 +# ============================================================================= + +PROJECT := HERV +BUILD := build + +# --- Toolchain --- +PREFIX := arm-none-eabi- +CC := $(PREFIX)gcc +AS := $(PREFIX)gcc -x assembler-with-cpp +LD := $(PREFIX)gcc +OBJCOPY := $(PREFIX)objcopy +SIZE := $(PREFIX)size + +# --- MCU --- +MCU := -mcpu=cortex-m0 -mthumb + +# --- Include 경로 (Eclipse 와 동일) --- +INCLUDES := \ + -ILibrary/CMSIS/Include \ + -ILibrary/Device/Nuvoton/Nano100Series/Include \ + -ILibrary/StdDriver/inc \ + -IUser + +# --- 공통 컴파일 플래그 (Eclipse subdir.mk 에서 추출) --- +COMMON_FLAGS := $(MCU) -Os -g \ + -fmessage-length=0 -fsigned-char \ + -ffunction-sections -fdata-sections + +CFLAGS := $(COMMON_FLAGS) $(INCLUDES) -std=gnu11 -MMD -MP +ASFLAGS := $(COMMON_FLAGS) -MMD -MP + +# --- 링커 --- +LDSCRIPT := Library/Device/Nuvoton/Nano100Series/Source/GCC/gcc_arm.ld +LDFLAGS := $(COMMON_FLAGS) -T$(LDSCRIPT) \ + -Xlinker --gc-sections \ + -Wl,-Map=$(BUILD)/$(PROJECT).map + +# --- 소스 자동 수집 --- +# 주의: User/pwm_duty10000.c 가 StdDriver/pwm.c 를 대체하므로 pwm.c 는 빌드에서 제외 +# (Eclipse Nueclipse 프로젝트도 동일하게 pwm.c 를 exclude 하고 빌드) +STDDRIVER_EXCLUDE := Library/StdDriver/src/pwm.c + +C_SRCS := \ + $(wildcard User/*.c) \ + $(filter-out $(STDDRIVER_EXCLUDE), $(wildcard Library/StdDriver/src/*.c)) \ + Library/Device/Nuvoton/Nano100Series/Source/system_Nano100Series.c \ + Library/Device/Nuvoton/Nano100Series/Source/GCC/_syscalls.c + +ASM_SRCS := \ + Library/Device/Nuvoton/Nano100Series/Source/GCC/startup_Nano100Series.S + +# --- Object 파일 (build/ 아래 같은 트리 구조 유지) --- +OBJS := $(addprefix $(BUILD)/, $(C_SRCS:.c=.o)) \ + $(addprefix $(BUILD)/, $(ASM_SRCS:.S=.o)) +DEPS := $(OBJS:.o=.d) + +# --- 출력 --- +ELF := $(BUILD)/$(PROJECT).elf +HEX := $(BUILD)/$(PROJECT).hex +BIN := $(BUILD)/$(PROJECT).bin + +# ============================================================================= +# Targets +# ============================================================================= + +.PHONY: all clean flash erase debug-server size rebuild + +all: $(ELF) $(HEX) $(BIN) size + +# clean -> all 을 순차 실행 (병렬 make -jN 에서 clean/all 동시 실행 방지) +rebuild: + @$(MAKE) clean + @$(MAKE) all + +$(ELF): $(OBJS) + @echo '[LD] $@' + @$(LD) $(LDFLAGS) -o $@ $^ + +$(HEX): $(ELF) + @echo '[HEX] $@' + @$(OBJCOPY) -O ihex $< $@ + +$(BIN): $(ELF) + @echo '[BIN] $@' + @$(OBJCOPY) -O binary $< $@ + +size: $(ELF) + @echo '' + @$(SIZE) --format=berkeley $< + @echo '' + +# C 컴파일 +$(BUILD)/%.o: %.c + @mkdir -p $(dir $@) + @echo '[CC] $<' + @$(CC) $(CFLAGS) -c $< -o $@ + +# Assembly 컴파일 +$(BUILD)/%.o: %.S + @mkdir -p $(dir $@) + @echo '[AS] $<' + @$(AS) $(ASFLAGS) -c $< -o $@ + +# Nu-Link 으로 플래시 굽기 +flash: $(ELF) + openocd -f openocd.cfg -c "program $(ELF) verify reset exit" + +# OpenOCD GDB 서버만 실행 (VS Code 디버그용) +debug-server: + openocd -f openocd.cfg + +# 칩 erase +erase: + openocd -f openocd.cfg -c "init; reset halt; nuc_chip_erase; exit" + +clean: + @echo 'Cleaning...' + @rm -rf $(BUILD) + +-include $(DEPS) diff --git a/program/User/MyControl.c b/program/User/MyControl.c new file mode 100644 index 0000000..eaaeeb8 --- /dev/null +++ b/program/User/MyControl.c @@ -0,0 +1,667 @@ +#include +#include +#include +#include +#include + +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" +#include "EEPROM_Emulate.h" + + +#include "My_define.h" + +uint32_t Read_Data(uint8_t index, uint8_t *data); +uint32_t Write_Data(uint8_t index, uint8_t data); + + +uint8_t page_data[EEP_SIZE]; + + +uint8_t Test_Fan1_Speed, Test_Fan2_Speed; +uint8_t Test_Fan1_Ven_1_dan, Test_Fan1_Ven_2_dan, Test_Fan1_Ven_3_dan, Test_Fan1_Ven_4_dan, \ + Test_Fan1_Air_1_dan, Test_Fan1_Air_2_dan, Test_Fan1_Air_3_dan, Test_Fan1_Air_4_dan,\ + Test_Fan1_Bypass_1_dan, Test_Fan1_Bypass_2_dan, Test_Fan1_Bypass_3_dan, Test_Fan1_Bypass_4_dan; +uint8_t Test_Fan2_Ven_1_dan, Test_Fan2_Ven_2_dan, Test_Fan2_Ven_3_dan, Test_Fan2_Ven_4_dan,\ + Test_Fan2_Air_1_dan, Test_Fan2_Air_2_dan, Test_Fan2_Air_3_dan , Test_Fan2_Air_4_dan,\ + Test_Fan2_Bypass_1_dan, Test_Fan2_Bypass_2_dan, Test_Fan2_Bypass_3_dan, Test_Fan2_Bypass_4_dan; + + + + + +/* 히스테리시스 프리셋(임계+데드밴드) <-> page_data (EEPROM 영역 43~127) */ +static void Hyst_To_Page(void) +{ + uint8_t pp, k, o; + page_data[EEP_HYST_PRESET] = Hyst_Preset; + for(pp = 0; pp < 3; pp++) + { + page_data[EEP_HYST_DB_BASE + 0 + pp] = (uint8_t)Co2_Db[pp]; + page_data[EEP_HYST_DB_BASE + 3 + pp] = (uint8_t)Pm25_Db[pp]; + page_data[EEP_HYST_DB_BASE + 6 + pp] = (uint8_t)Pm10_Db[pp]; + page_data[EEP_HYST_DB_BASE + 9 + pp] = (uint8_t)Voc_Db[pp]; + for(k = 0; k < 4; k++) + { + o = (uint8_t)(pp * 8 + k * 2); + page_data[EEP_THR_CO2_BASE + o] = (uint8_t)(Co2_Thr[pp][k] >> 8); + page_data[EEP_THR_CO2_BASE + o + 1] = (uint8_t)(Co2_Thr[pp][k] & 0xFF); + page_data[EEP_THR_VOC_BASE + o] = (uint8_t)(Voc_Thr[pp][k] >> 8); + page_data[EEP_THR_VOC_BASE + o + 1] = (uint8_t)(Voc_Thr[pp][k] & 0xFF); + page_data[EEP_THR_PM25_BASE + pp * 4 + k] = (uint8_t)Pm25_Thr[pp][k]; + page_data[EEP_THR_PM10_BASE + pp * 4 + k] = (uint8_t)Pm10_Thr[pp][k]; + } + } +} + +static void Hyst_From_Page(void) +{ + uint8_t pp, k, o; + if(page_data[EEP_HYST_PRESET] > 2) return; /* 미초기화(0xFF) -> 컴파일 기본값 유지 */ + Hyst_Preset = page_data[EEP_HYST_PRESET]; + for(pp = 0; pp < 3; pp++) + { + Co2_Db[pp] = page_data[EEP_HYST_DB_BASE + 0 + pp]; + Pm25_Db[pp] = page_data[EEP_HYST_DB_BASE + 3 + pp]; + Pm10_Db[pp] = page_data[EEP_HYST_DB_BASE + 6 + pp]; + Voc_Db[pp] = page_data[EEP_HYST_DB_BASE + 9 + pp]; + for(k = 0; k < 4; k++) + { + o = (uint8_t)(pp * 8 + k * 2); + Co2_Thr[pp][k] = (uint16_t)(((uint16_t)page_data[EEP_THR_CO2_BASE + o] << 8) | page_data[EEP_THR_CO2_BASE + o + 1]); + Voc_Thr[pp][k] = (uint16_t)(((uint16_t)page_data[EEP_THR_VOC_BASE + o] << 8) | page_data[EEP_THR_VOC_BASE + o + 1]); + Pm25_Thr[pp][k] = page_data[EEP_THR_PM25_BASE + pp * 4 + k]; + Pm10_Thr[pp][k] = page_data[EEP_THR_PM10_BASE + pp * 4 + k]; + } + } +} + +void init_process(void) +{ + uint16_t i; + uint8_t eep_error = 0; + + union { + uint32_t u32_val ; + uint8_t u8_val[4] ; + } tran ; + + + for(i=0; i<20; i++)Tx_roomcon232_buffer[i] = 0; + for(i=0; i<20; i++)Tx_display_buffer[i] = 0; + for(i=0; i<20; i++)Tx_homenet_buffer[i] = 0; + + + for(i=0; i>8); + page_data[EEP_FILTER_CLEAN_HOUR_L] = (uint8_t)(Filter_timer_clean&0x00FF); + page_data[EEP_FILTER_CHANGE_HOUR_H] = (uint8_t)((Filter_timer_change&0xFF00)>>8); + page_data[EEP_FILTER_CHANGE_HOUR_L] = (uint8_t)(Filter_timer_change&0x00FF); + page_data[EEP_SOJA_CHANGE_HOUR_H] = (uint8_t)((Soja_timer_change&0xFF00)>>8); + page_data[EEP_SOJA_CHANGE_HOUR_L] = (uint8_t)(Soja_timer_change&0x00FF); + + page_data[EEP_BLACKOUT_POWER_ON] = Power_On; + page_data[EEP_BLACKOUT_RUN_MODE] = Run_Mode; + page_data[EEP_BLACKOUT_FAN_MODE] = Fan_Mode; + + Hyst_To_Page(); /* 히스테리시스 임계/데드밴드/프리셋 기본값 저장 */ + + for(i=0; i= 99.9)Ret = 99.9; + + return(Ret); +} + +// LNTK103FF + +#define T_a 3.08197700643E-002 +#define T_b 8.77312053750E+002 +#define T_c -3.17755936684E+003 +#define T_d 5.62092429082E+003 +#define T_e -5.86906412922E+003 +#define T_f 3.82840309167E+003 +#define T_g -1.57651548838E+003 +#define T_h 3.97983185914E+002 +#define T_i -5.61894921403E+001 +#define T_j 3.39457675113E+000 + + + +#define PowerSupplyVoltage 3.300 // + +float Temperature_Conversion(float V) +{ + + return( T_a + T_b*V + T_c*V*V + T_d*V*V*V + T_e*V*V*V*V + T_f*V*V*V*V*V + T_g*V*V*V*V*V*V +\ + T_h*V*V*V*V*V*V*V + T_i*V*V*V*V*V*V*V*V + T_j*V*V*V*V*V*V*V*V*V ); +} + + +////////////////////////////////////////////////////////////// +// ADC Power Input + +float VoltageConversion(unsigned int in_data) +{ + return((float)((float)in_data) * (PowerSupplyVoltage / 4095)); + +} + +//========================================================================== + +float Humidity_Read(uint16_t data) +{ + float Retf, fTmp; + + fTmp = VoltageConversion(data); + + if(fTmp < 0.1)Retf = 0; + else Retf = Humidity_Conversion(fTmp)*10; + + + return(Retf); +} + + + + +float Temperature_Read(uint16_t data) +{ + float Retf, fTmp; + + fTmp = VoltageConversion(data); + + Retf = Temperature_Conversion(fTmp) ; // + + return(Retf); +} + +float Float_Aeverage_calculator(float val, float * array_val) +{ + uint8_t i; + float max = -10000; + float min = 10000; + float sum = 0; + float Rval = 0; + + for(i=9; i>0; i--) + { + *(array_val+i) = *(array_val+i-1); + } + *array_val = val; + + for(i=0; i<10; i++) + { + if(array_val[i] >= max) + { + max = array_val[i]; + } + if(array_val[i] <= min) + { + min = array_val[i]; + } + sum += array_val[i]; + } + Rval = (float)((sum - max - min)/8); + + return(Rval); +} + + +uint16_t Aeverage_calculator(uint16_t val, uint16_t * array_val) +{ + uint8_t i; + uint16_t max = 0; + uint16_t min = 10000; + uint32_t sum = 0; + uint16_t Rval = 0; + + for(i=9; i>0; i--) + { + *(array_val+i) = *(array_val+i-1); + } + *array_val = val; + + for(i=0; i<10; i++) + { + if(array_val[i] >= max) + { + max = array_val[i]; + } + if(array_val[i] <= min) + { + min = array_val[i]; + } + sum += array_val[i]; + } + Rval = (uint16_t)((sum - max - min)/8); + + return(Rval); +} + +uint16_t Current_Read(uint16_t adc_current) +{ + return adc_current; +} + + + +extern volatile uint8_t ADC_Complete; + +volatile uint8_t Err_Code = 0; + +uint16_t adc_result = 0; +uint16_t Main_Current; +signed int Out_Temperature = 0; +signed int In_Temperature = 0; + +uint8_t Sen_Pos = 0; + +int16_t Volum1_value = 0, Volum2_value = 0; + +float Avr_Temperature_1[10]={0,0,0,0,0,0,0,0,0,0}; +float Avr_Temperature_2[10]={0,0,0,0,0,0,0,0,0,0}; +uint16_t Avr_Vol_1[10]={0,0,0,0,0,0,0,0,0,0}; +uint16_t Avr_Vol_2[10]={0,0,0,0,0,0,0,0,0,0}; +uint16_t Avr_Current[10]={0,0,0,0,0,0,0,0,0,0}; + + +uint8_t Temp_sensor_error = 0; +void ADC_Sensing(void) +{ + float fTmp = 0; + signed int sTmp = 0; + uint16_t uTmp = 0; + + + if(ADC_Complete == 1) + { + ADC_Complete = 0; + + adc_result = ADC_GET_CONVERSION_DATA(ADC, 4); // in + uTmp = Aeverage_calculator(adc_result, Avr_Current); + Main_Current = Current_Read(uTmp); +//////////// in +/* adc_current = ADC_GET_CONVERSION_DATA(ADC, 0); // in + fTmp = Temperature_Read(adc_result); + + if(fTmp < 0) fTmp *= 1.05; + sTmp = (signed int)fTmp; + + + + if((sTmp > 85) || (sTmp < -40)) + { + Temp_sensor_error |= 1; + In_Temperature = 100; + } + else + { + sTmp = Float_Aeverage_calculator(sTmp, Avr_Temperature_1); + Temp_sensor_error &= ~1; + + if(sTmp >= 85)In_Temperature = 85; + else if(sTmp <= -20)In_Temperature = -20; + else In_Temperature = sTmp; + } + +*/ +//////////// out + adc_result = ADC_GET_CONVERSION_DATA(ADC, 1); // out + fTmp = Temperature_Read(adc_result); + + if(fTmp < 0) fTmp *= 1.05; + sTmp = (signed int)fTmp; + + + if((sTmp > 85) || (sTmp < -40)) + { + Temp_sensor_error |= 2; + Out_Temperature = 100; + } + else + { + sTmp = Float_Aeverage_calculator(sTmp, Avr_Temperature_2); + Temp_sensor_error &= ~2; + + if(sTmp >= 85)Out_Temperature = 85; + else if(sTmp <= -20)Out_Temperature = -20; + else Out_Temperature = sTmp; + } + + + //if(Temp_sensor_error)Err_Code |= ERROR_TEMP_SENSOR; + //else Err_Code &= ~ERROR_TEMP_SENSOR; + + +////////////// vol 1 + adc_result = ADC_GET_CONVERSION_DATA(ADC, 2); + //fTmp = Aeverage_calculator(adc_result, Avr_Vol_2); + Volum1_value = 125 - (signed int)((float)adc_result/4.095/4) + 50; // -100 ~ 100 + +//////////////// vol 2 + adc_result = ADC_GET_CONVERSION_DATA(ADC, 3); + //fTmp = Aeverage_calculator(adc_result, Avr_Vol_1); + Volum2_value = 125 - (signed int)((float)adc_result/4.095/4) + 50; // -100 ~ 100 + + } + ADC_START_CONV(ADC); +} + +void EEP_Save_process(void) +{ + uint8_t i; + + /* (구 PC메뉴용 Test_Fan -> s_FAN 복사 제거 : 대시보드 CTRL_VSP 로 설정한 s_FAN 값을 그대로 저장) */ + + page_data[EEP_FAN1_VEN_1_DAN] = s_FAN1_VEN_1_DAN; + page_data[EEP_FAN1_VEN_2_DAN] = s_FAN1_VEN_2_DAN; + page_data[EEP_FAN1_VEN_3_DAN] = s_FAN1_VEN_3_DAN; + page_data[EEP_FAN1_VEN_4_DAN] = s_FAN1_VEN_4_DAN; + page_data[EEP_FAN1_AIR_1_DAN] = s_FAN1_AIR_1_DAN; + page_data[EEP_FAN1_AIR_2_DAN] = s_FAN1_AIR_2_DAN; + page_data[EEP_FAN1_AIR_3_DAN] = s_FAN1_AIR_3_DAN; + page_data[EEP_FAN1_AIR_4_DAN] = s_FAN1_AIR_4_DAN; + page_data[EEP_FAN1_BYPASS_1_DAN] = s_FAN1_BYPASS_1_DAN; + page_data[EEP_FAN1_BYPASS_2_DAN] = s_FAN1_BYPASS_2_DAN; + page_data[EEP_FAN1_BYPASS_3_DAN] = s_FAN1_BYPASS_3_DAN; + page_data[EEP_FAN1_BYPASS_4_DAN] = s_FAN1_BYPASS_4_DAN; + + page_data[EEP_FAN2_VEN_1_DAN] = s_FAN2_VEN_1_DAN; + page_data[EEP_FAN2_VEN_2_DAN] = s_FAN2_VEN_2_DAN; + page_data[EEP_FAN2_VEN_3_DAN] = s_FAN2_VEN_3_DAN; + page_data[EEP_FAN2_VEN_4_DAN] = s_FAN2_VEN_4_DAN; + page_data[EEP_FAN2_AIR_1_DAN] = s_FAN2_AIR_1_DAN; + page_data[EEP_FAN2_AIR_2_DAN] = s_FAN2_AIR_2_DAN; + page_data[EEP_FAN2_AIR_3_DAN] = s_FAN2_AIR_3_DAN; + page_data[EEP_FAN2_AIR_4_DAN] = s_FAN2_AIR_4_DAN; + page_data[EEP_FAN2_BYPASS_1_DAN] = s_FAN2_BYPASS_1_DAN; + page_data[EEP_FAN2_BYPASS_2_DAN] = s_FAN2_BYPASS_2_DAN; + page_data[EEP_FAN2_BYPASS_3_DAN] = s_FAN2_BYPASS_3_DAN; + page_data[EEP_FAN2_BYPASS_4_DAN] = s_FAN2_BYPASS_4_DAN; + + page_data[EEP_FILTER_CLEAN_HOUR_H] = (uint8_t)((Filter_timer_clean&0xFF00)>>8); + page_data[EEP_FILTER_CLEAN_HOUR_L] = (uint8_t)(Filter_timer_clean&0x00FF); + page_data[EEP_FILTER_CHANGE_HOUR_H] = (uint8_t)((Filter_timer_change&0xFF00)>>8); + page_data[EEP_FILTER_CHANGE_HOUR_L] = (uint8_t)(Filter_timer_change&0x00FF); + page_data[EEP_SOJA_CHANGE_HOUR_H] = (uint8_t)((Soja_timer_change&0xFF00)>>8); + page_data[EEP_SOJA_CHANGE_HOUR_L] = (uint8_t)(Soja_timer_change&0x00FF); + + page_data[EEP_BLACKOUT_POWER_ON] = Power_On; + page_data[EEP_BLACKOUT_RUN_MODE] = Run_Mode; + page_data[EEP_BLACKOUT_FAN_MODE] = Fan_Mode; + + Hyst_To_Page(); /* 히스테리시스 임계/데드밴드/프리셋 저장 (대시보드 0x06/0x07/0x0D) */ + + for(i=0; i= 4000)Filter_timer_change = 0; + if(Soja_timer_change >= 20000)Soja_timer_change = 0; + + return(1); +} + + + +void Reserve_Time_Update(uint8_t rtime) +{ + if(Roomcon_connect_mode == 0) + { + Set_Reserve_timer_sec = (uint32_t)rtime * 3600; + Reserve_timer_sec = Set_Reserve_timer_sec; + Pre_Reserve_hour = rtime; + } + else + { + if(rtime != Pre_Reserve_hour) + { + Set_Reserve_timer_sec = (uint32_t)rtime * 3600; + Pre_Reserve_hour = rtime; + } + } +} + +extern uint8_t Power_On; +extern volatile uint8_t Run_Mode, Fan_Mode; +void Power_off_process(uint8_t set) +{ uint8_t i = 0; + + Reserve_hour = 0; + Pre_Reserve_hour = 0; + Reserve_timer_sec = 0; + Fan_Mode = 0; + Run_Mode = 0; + Power_On = 0; + for(i=1; i<7; i++)Diffuser_Power[i] = 0; //////diffuser off + + + if(set == 1) + { + Set_Reserve_timer_sec = 0; + Set_Run_Mode = 0; + Set_Fan_Mode = 0; + } +} + +uint8_t BlackOut_Power_On = 0; +uint8_t BlackOut_Run_Mode = 0; +uint8_t BlackOut_Fan_Mode = 0; +void Pre_Mode_Control(void) +{ + uint8_t i; + + if((BlackOut_Power_On != Power_On)||(BlackOut_Run_Mode != Run_Mode)||(BlackOut_Fan_Mode != Fan_Mode)) + { + page_data[EEP_BLACKOUT_POWER_ON] = Power_On; + page_data[EEP_BLACKOUT_RUN_MODE] = Run_Mode; + page_data[EEP_BLACKOUT_FAN_MODE] = Fan_Mode; + + for(i=EEP_BLACKOUT_POWER_ON; i +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" +#include "EEPROM_Emulate.h" + + +#include "My_define.h" + +extern volatile uint8_t Err_Code; +void Damper_Setting(uint8_t damper_num, float angle_degree); // dir = 0 ������ + +uint8_t m1_seq = 0; +uint8_t m2_seq = 0; +uint8_t m3_seq = 0; +uint8_t m4_seq = 0; +uint8_t m5_seq = 0; +uint8_t m6_seq = 0; + + +uint8_t Step_dir[7] = {0,0,0,0,0,0,0} ; +uint16_t Current_Step_Count[7] = {0,0,0,0,0,0,0} ; +uint16_t Target_Step_Count[7] = {0,0,0,0,0,0,0} ; + + +uint16_t BLDC_SPEED_TABLE[100] = {//0.5V ~ 5.45 +0, 603, 678, 753, 828, 903, 980, 1056, 1131, 1208 , +1286, 1362, 1440, 1517, 1596, 1675, 1754, 1833, 1912, 1993 , +2072, 2152, 2232, 2312, 2395, 2478, 2559, 2641, 2724, 2806 , +2889, 2973, 3057, 3141, 3226, 3311, 3396, 3482, 3568, 3655 , +3742, 3828, 3915, 4002, 4090, 4179, 4268, 4357, 4447, 4538 , +4628, 4719, 4810, 4901, 4993, 5085, 5178, 5271, 5364, 5458 , +5552, 5646, 5740, 5835, 5931, 6027, 6124, 6221, 6319, 6417 , +6515, 6614, 6713, 6813, 6913, 7014, 7115, 7217, 7319, 7421 , +7524, 7627, 7731, 7835, 7940, 8045, 8150, 8256, 8362, 8469 , +8576, 8684, 8793, 8902, 9012, 9122, 9232, 9344, 9457, 9571 +}; + + +uint16_t Test_RPM_Vent_Reference[5]={0,}; +uint16_t Test_RPM_Vent_Delta[5]={0,}; +uint16_t Test_RPM_Air_Reference[5]={0,}; +uint16_t Test_RPM_Air_Delta[5]={0,}; + +uint16_t RPM_Vent_Reference[5]={0,}; +uint16_t RPM_Vent_Delta[5]={0,}; +uint16_t RPM_Air_Reference[5]={0,}; +uint16_t RPM_Air_Delta[5]={0,}; + +uint8_t RPM_Check_Start = 0; +uint8_t RPM_Stable_Timer = 0; + +uint8_t RPM_Auto_Cal_Flag = 0; +uint8_t RPM_Auto_Cal_Status = 0; +uint8_t RPM_Auto_Cal_Start = 0; + +uint16_t Rpm_Auto_Delay = 0; +uint8_t Rpm_Auto_Pos = 10; + +void Step_M1_Process(uint8_t dir) +{ + + if(dir == 1){if(m1_seq++ >= 7)m1_seq = 0;} + else{if(m1_seq-- == 0)m1_seq = 7;} + + switch(m1_seq) + { + case 0: + REG_STEP_M1_A = 1; // 1 + REG_STEP_M1_B = 0; // 0 + REG_STEP_M1_NA = 0;// 0 + REG_STEP_M1_NB = 0;// 0 + break; + case 1: + REG_STEP_M1_A = 1 ; // 1 + REG_STEP_M1_B = 1 ; // 1 + REG_STEP_M1_NA = 0 ;// 0 + REG_STEP_M1_NB = 0 ;// 0 + break; + case 2: + REG_STEP_M1_A = 0 ; // 0 + REG_STEP_M1_B = 1 ; // 1 + REG_STEP_M1_NA = 0 ;// 0 + REG_STEP_M1_NB = 0 ;// 0 + break; + case 3: + REG_STEP_M1_A = 0 ; // 0 + REG_STEP_M1_B = 1 ; // 1 + REG_STEP_M1_NA = 1 ;// 1 + REG_STEP_M1_NB = 0 ;// 0 + break; + case 4: + REG_STEP_M1_A = 0 ; // 0 + REG_STEP_M1_B = 0 ; // 0 + REG_STEP_M1_NA = 1 ;// 1 + REG_STEP_M1_NB = 0 ;// 0 + break; + case 5: + REG_STEP_M1_A = 0 ; // 0 + REG_STEP_M1_B = 0 ; // 0 + REG_STEP_M1_NA = 1 ;// 1 + REG_STEP_M1_NB = 1 ;// 1 + break; + case 6: + REG_STEP_M1_A = 0 ; // 0 + REG_STEP_M1_B = 0 ; // 0 + REG_STEP_M1_NA = 0 ;// 0 + REG_STEP_M1_NB = 1 ;// 1 + break; + case 7: + REG_STEP_M1_A = 1 ; // 1 + REG_STEP_M1_B = 0 ; // 0 + REG_STEP_M1_NA = 0 ;// 0 + REG_STEP_M1_NB = 1 ;// 1 + break; + } +} + + + +void Step_M2_Process(uint8_t dir) +{ + + if(dir == 1){if(m2_seq++ >= 7)m2_seq = 0;} + else{if(m2_seq-- == 0)m2_seq = 7;} + + switch(m2_seq) + { + case 0: + REG_STEP_M2_A = 1 ; // 1 + REG_STEP_M2_B = 0 ; // 0 + REG_STEP_M2_NA = 0 ;// 0 + REG_STEP_M2_NB = 0 ;// 0 + break; + case 1: + REG_STEP_M2_A = 1 ; // 1 + REG_STEP_M2_B = 1 ; // 1 + REG_STEP_M2_NA = 0 ;// 0 + REG_STEP_M2_NB = 0 ;// 0 + break; + case 2: + REG_STEP_M2_A = 0 ; // 0 + REG_STEP_M2_B = 1 ; // 1 + REG_STEP_M2_NA = 0 ;// 0 + REG_STEP_M2_NB = 0 ;// 0 + break; + case 3: + REG_STEP_M2_A = 0 ; // 0 + REG_STEP_M2_B = 1 ; // 1 + REG_STEP_M2_NA = 1 ;// 1 + REG_STEP_M2_NB = 0 ;// 0 + break; + case 4: + REG_STEP_M2_A = 0 ; // 0 + REG_STEP_M2_B = 0 ; // 0 + REG_STEP_M2_NA = 1 ;// 1 + REG_STEP_M2_NB = 0 ;// 0 + break; + case 5: + REG_STEP_M2_A = 0 ; // 0 + REG_STEP_M2_B = 0 ; // 0 + REG_STEP_M2_NA = 1 ;// 1 + REG_STEP_M2_NB = 1 ;// 1 + break; + case 6: + REG_STEP_M2_A = 0 ; // 0 + REG_STEP_M2_B = 0 ; // 0 + REG_STEP_M2_NA = 0 ;// 0 + REG_STEP_M2_NB = 1 ;// 1 + break; + case 7: + REG_STEP_M2_A = 1 ; // 1 + REG_STEP_M2_B = 0 ; // 0 + REG_STEP_M2_NA = 0 ;// 0 + REG_STEP_M2_NB = 1 ;// 1 + break; + } +} + +void Step_M3_Process(uint8_t dir) +{ + if(dir == 1){if(m3_seq++ >= 7)m3_seq = 0;} + else{if(m3_seq-- == 0)m3_seq = 7;} + + switch(m3_seq) + { + case 0: + REG_STEP_M3_A = 1 ; // 1 + REG_STEP_M3_B = 0 ; // 0 + REG_STEP_M3_NA = 0 ;// 0 + REG_STEP_M3_NB = 0 ;// 0 + break; + case 1: + REG_STEP_M3_A = 1 ; // 1 + REG_STEP_M3_B = 1 ; // 1 + REG_STEP_M3_NA = 0 ;// 0 + REG_STEP_M3_NB = 0 ;// 0 + break; + case 2: + REG_STEP_M3_A = 0 ; // 0 + REG_STEP_M3_B = 1 ; // 1 + REG_STEP_M3_NA = 0 ;// 0 + REG_STEP_M3_NB = 0 ;// 0 + break; + case 3: + REG_STEP_M3_A = 0 ; // 0 + REG_STEP_M3_B = 1 ; // 1 + REG_STEP_M3_NA = 1 ;// 1 + REG_STEP_M3_NB = 0 ;// 0 + break; + case 4: + REG_STEP_M3_A = 0 ; // 0 + REG_STEP_M3_B = 0 ; // 0 + REG_STEP_M3_NA = 1 ;// 1 + REG_STEP_M3_NB = 0 ;// 0 + break; + case 5: + REG_STEP_M3_A = 0 ; // 0 + REG_STEP_M3_B = 0 ; // 0 + REG_STEP_M3_NA = 1 ;// 1 + REG_STEP_M3_NB = 1 ;// 1 + break; + case 6: + REG_STEP_M3_A = 0 ; // 0 + REG_STEP_M3_B = 0 ; // 0 + REG_STEP_M3_NA = 0 ;// 0 + REG_STEP_M3_NB = 1 ;// 1 + break; + case 7: + REG_STEP_M3_A = 1 ; // 1 + REG_STEP_M3_B = 0 ; // 0 + REG_STEP_M3_NA = 0 ;// 0 + REG_STEP_M3_NB = 1 ;// 1 + break; + } +} + +void Step_M4_Process(uint8_t dir) +{ + + if(dir == 1){if(m4_seq++ >= 7)m4_seq = 0;} + else{if(m4_seq-- == 0)m4_seq = 7;} + + switch(m4_seq) + { + case 0: + REG_STEP_M4_A = 1 ; // 1 + REG_STEP_M4_B = 0 ; // 0 + REG_STEP_M4_NA = 0 ;// 0 + REG_STEP_M4_NB = 0 ;// 0 + break; + case 1: + REG_STEP_M4_A = 1 ; // 1 + REG_STEP_M4_B = 1 ; // 1 + REG_STEP_M4_NA = 0 ;// 0 + REG_STEP_M4_NB = 0 ;// 0 + break; + case 2: + REG_STEP_M4_A = 0 ; // 0 + REG_STEP_M4_B = 1 ; // 1 + REG_STEP_M4_NA = 0 ;// 0 + REG_STEP_M4_NB = 0 ;// 0 + break; + case 3: + REG_STEP_M4_A = 0 ; // 0 + REG_STEP_M4_B = 1 ; // 1 + REG_STEP_M4_NA = 1 ;// 1 + REG_STEP_M4_NB = 0 ;// 0 + break; + case 4: + REG_STEP_M4_A = 0 ; // 0 + REG_STEP_M4_B = 0 ; // 0 + REG_STEP_M4_NA = 1 ;// 1 + REG_STEP_M4_NB = 0 ;// 0 + break; + case 5: + REG_STEP_M4_A = 0 ; // 0 + REG_STEP_M4_B = 0 ; // 0 + REG_STEP_M4_NA = 1 ;// 1 + REG_STEP_M4_NB = 1 ;// 1 + break; + case 6: + REG_STEP_M4_A = 0 ; // 0 + REG_STEP_M4_B = 0 ; // 0 + REG_STEP_M4_NA = 0 ;// 0 + REG_STEP_M4_NB = 1 ;// 1 + break; + case 7: + REG_STEP_M4_A = 1 ; // 1 + REG_STEP_M4_B = 0 ; // 0 + REG_STEP_M4_NA = 0 ;// 0 + REG_STEP_M4_NB = 1 ;// 1 + break; + } +} + +void Step_M5_Process(uint8_t dir) +{ + + if(dir == 1){if(m5_seq++ >= 7)m5_seq = 0;} + else{if(m5_seq-- == 0)m5_seq = 7;} + + switch(m5_seq) + { + case 0: + REG_STEP_M5_A = 1 ; // 1 + REG_STEP_M5_B = 0 ; // 0 + REG_STEP_M5_NA = 0 ;// 0 + REG_STEP_M5_NB = 0 ;// 0 + break; + case 1: + REG_STEP_M5_A = 1 ; // 1 + REG_STEP_M5_B = 1 ; // 1 + REG_STEP_M5_NA = 0 ;// 0 + REG_STEP_M5_NB = 0 ;// 0 + break; + case 2: + REG_STEP_M5_A = 0 ; // 0 + REG_STEP_M5_B = 1 ; // 1 + REG_STEP_M5_NA = 0 ;// 0 + REG_STEP_M5_NB = 0 ;// 0 + break; + case 3: + REG_STEP_M5_A = 0 ; // 0 + REG_STEP_M5_B = 1 ; // 1 + REG_STEP_M5_NA = 1 ;// 1 + REG_STEP_M5_NB = 0 ;// 0 + break; + case 4: + REG_STEP_M5_A = 0 ; // 0 + REG_STEP_M5_B = 0 ; // 0 + REG_STEP_M5_NA = 1 ;// 1 + REG_STEP_M5_NB = 0 ;// 0 + break; + case 5: + REG_STEP_M5_A = 0 ; // 0 + REG_STEP_M5_B = 0 ; // 0 + REG_STEP_M5_NA = 1 ;// 1 + REG_STEP_M5_NB = 1 ;// 1 + break; + case 6: + REG_STEP_M5_A = 0 ; // 0 + REG_STEP_M5_B = 0 ; // 0 + REG_STEP_M5_NA = 0 ;// 0 + REG_STEP_M5_NB = 1 ;// 1 + break; + case 7: + REG_STEP_M5_A = 1 ; // 1 + REG_STEP_M5_B = 0 ; // 0 + REG_STEP_M5_NA = 0 ;// 0 + REG_STEP_M5_NB = 1 ;// 1 + break; + } +} + +void Step_M6_Process(uint8_t dir) +{ + + if(dir == 1){if(m6_seq++ >= 7)m6_seq = 0;} + else{if(m6_seq-- == 0)m6_seq = 7;} + + switch(m6_seq) + { + case 0: + REG_STEP_M6_A = 1 ; // 1 + REG_STEP_M6_B = 0 ; // 0 + REG_STEP_M6_NA = 0 ;// 0 + REG_STEP_M6_NB = 0 ;// 0 + break; + case 1: + REG_STEP_M6_A = 1 ; // 1 + REG_STEP_M6_B = 1 ; // 1 + REG_STEP_M6_NA = 0 ;// 0 + REG_STEP_M6_NB = 0 ;// 0 + break; + case 2: + REG_STEP_M6_A = 0 ; // 0 + REG_STEP_M6_B = 1 ; // 1 + REG_STEP_M6_NA = 0 ;// 0 + REG_STEP_M6_NB = 0 ;// 0 + break; + case 3: + REG_STEP_M6_A = 0 ; // 0 + REG_STEP_M6_B = 1 ; // 1 + REG_STEP_M6_NA = 1 ;// 1 + REG_STEP_M6_NB = 0 ;// 0 + break; + case 4: + REG_STEP_M6_A = 0 ; // 0 + REG_STEP_M6_B = 0 ; // 0 + REG_STEP_M6_NA = 1 ;// 1 + REG_STEP_M6_NB = 0 ;// 0 + break; + case 5: + REG_STEP_M6_A = 0 ; // 0 + REG_STEP_M6_B = 0 ; // 0 + REG_STEP_M6_NA = 1 ;// 1 + REG_STEP_M6_NB = 1 ;// 1 + break; + case 6: + REG_STEP_M6_A = 0 ; // 0 + REG_STEP_M6_B = 0 ; // 0 + REG_STEP_M6_NA = 0 ;// 0 + REG_STEP_M6_NB = 1 ;// 1 + break; + case 7: + REG_STEP_M6_A = 1 ; // 1 + REG_STEP_M6_B = 0 ; // 0 + REG_STEP_M6_NA = 0 ;// 0 + REG_STEP_M6_NB = 1 ;// 1 + break; + } +} + +void Step_M1_Stop(void) +{ + REG_STEP_M1_A = 0 ; + REG_STEP_M1_B = 0 ; + REG_STEP_M1_NA = 0 ; + REG_STEP_M1_NB = 0 ; +} +void Step_M2_Stop(void) +{ + REG_STEP_M2_A = 0 ; + REG_STEP_M2_B = 0 ; + REG_STEP_M2_NA = 0 ; + REG_STEP_M2_NB = 0 ; +} +void Step_M3_Stop(void) +{ + REG_STEP_M3_A = 0 ; + REG_STEP_M3_B = 0 ; + REG_STEP_M3_NA = 0 ; + REG_STEP_M3_NB = 0 ; +} +void Step_M4_Stop(void) +{ + REG_STEP_M4_A = 0 ; + REG_STEP_M4_B = 0 ; + REG_STEP_M4_NA = 0 ; + REG_STEP_M4_NB = 0 ; +} +void Step_M5_Stop(void) +{ + REG_STEP_M5_A = 0 ; + REG_STEP_M5_B = 0 ; + REG_STEP_M5_NA = 0 ; + REG_STEP_M5_NB = 0 ; +} +void Step_M6_Stop(void) +{ + REG_STEP_M6_A = 0 ; + REG_STEP_M6_B = 0 ; + REG_STEP_M6_NA = 0 ; + REG_STEP_M6_NB = 0 ; +} + +#define MODE_OFF 10 + +uint8_t Pre_Damper_Mode = 0; +volatile uint8_t Step_Status = 0; +uint8_t Step_pos = 0; + +void Damper_Mode(uint8_t mmm) +{ + + switch(mmm) + { + case MODE_VENTILATION: + Damper_Setting(DAMPER_OA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_EA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_BYPASS, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_SA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_RA, 70); // 90 = close, 0 = open 3step--reverse + Damper_Setting(DAMPER_AIR, 105); // 90 = close, 0 = open + + break; + case MODE_AIRCLEAN: + Damper_Setting(DAMPER_OA, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_EA, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_BYPASS, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_SA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_RA, 140); // 90 = close, 0 = open 3step--reverse + Damper_Setting(DAMPER_AIR, 0); // 90 = close, 0 = open + break; + case MODE_BYPASS: + Damper_Setting(DAMPER_OA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_EA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_BYPASS, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_SA, 0); // 90 = close, 0 = open + Damper_Setting(DAMPER_RA, 140); // 90 = close, 0 = open 3step--reverse + Damper_Setting(DAMPER_AIR, 105); // 90 = close, 0 = open + break; + case MODE_OFF: + default: + Damper_Setting(DAMPER_OA, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_EA, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_BYPASS, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_SA, 100); // 90 = close, 0 = open + Damper_Setting(DAMPER_RA, 0); // 90 = close, 0 = open 3step--reverse + Damper_Setting(DAMPER_AIR, 105); // 90 = close, 0 = open + break; + } + + if(Pre_Damper_Mode != mmm) + { + Step_Status = 0; + + + if(Pre_Damper_Mode == MODE_VENTILATION) + { + Step_pos = 2; + } + else if(mmm == MODE_OFF) + { + Step_pos = 2; + } + else + { + Step_pos = 0; + } + + } + + Pre_Damper_Mode = mmm; +} + +// step x = angle*85 / 7.5 +// angle 90 -> x = 1020 +uint8_t Step_motor_init(void) // Rev = 0 ������ , +{ + + uint16_t i; + + for(i=0; i<7; i++) + { + Step_dir[i] = 0; + Current_Step_Count[i] = 1020; + Target_Step_Count[i] = 1020; + + } + + for(i=0; i<1077; i++){Step_M5_Process(1);Step_M6_Process(0);delay_us(2000);} // + for(i=0; i<400; i++){Step_M5_Process(1);delay_us(1500);} // EBSN + Step_M5_Stop(); + Step_M6_Stop(); + + for(i=0; i<1077; i++){Step_M1_Process(0);Step_M2_Process(0);delay_us(1500);} + Step_M1_Stop(); + Step_M2_Stop(); + + for(i=0; i<1077; i++){Step_M3_Process(0);Step_M4_Process(0);delay_us(1500);} + Step_M3_Stop(); + Step_M4_Stop(); + + + Damper_Mode(MODE_OFF); + + for(i=0; i<7; i++) + { + Current_Step_Count[i] = Target_Step_Count[i]; + } + return 0; + +} + + +void Damper_Setting(uint8_t damper_num, float angle_degree) // dir = 0 ������ +{ + Target_Step_Count[damper_num] = (uint16_t)(angle_degree * 85 / 7.5); +} + +#define StepInterval_Fast 1 +#define StepInterval_Slow 5 + +uint8_t Step_Interval1 = StepInterval_Slow; +uint8_t Step_Interval2 = StepInterval_Slow; +uint8_t Step_Interval3 = StepInterval_Slow; +uint8_t Step_Interval4 = StepInterval_Slow; +uint8_t Step_Interval5 = StepInterval_Slow; +uint8_t Step_Interval6 = StepInterval_Slow; + +uint16_t StartFlag1 = 0; +uint16_t StartFlag2 = 0; +uint16_t StartFlag3 = 0; +uint16_t StartFlag4 = 0; +uint16_t StartFlag5 = 0; +uint16_t StartFlag6 = 0; + +void Step_process(void) +{ +// 1ms process + + switch(Step_pos) + { + case 0: + if(Step_Interval1) + { + Step_Interval1 -- ; + } + else + { + if(Current_Step_Count[1] > Target_Step_Count[1]) + { + Step_M1_Process(1); + Step_Interval1 = 3; + Current_Step_Count[1]--; + Step_Status &= ~1; + } + else if(Current_Step_Count[1] < Target_Step_Count[1]) + { + Step_M1_Process(0); + Step_Interval1 = 3; + Current_Step_Count[1]++; + Step_Status &= ~1; + } + else + { + Step_M1_Stop(); + Step_Status |= 1; + StartFlag1 = 0; + Step_Interval1 = 0; + } + } + + if(Step_Interval2) + { + Step_Interval2 -- ; + } + else + { + if(Current_Step_Count[2] > Target_Step_Count[2]) + { + Step_M2_Process(1); + if(StartFlag2 < 400)Step_Interval2 = StepInterval_Slow; + else Step_Interval2 = StepInterval_Fast; + + StartFlag2++; + + Current_Step_Count[2]--; + Step_Status &= ~2; + } + else if(Current_Step_Count[2] < Target_Step_Count[2]) + { + Step_M2_Process(0); + if(StartFlag2 < 400)Step_Interval2 = StepInterval_Slow; + else Step_Interval2 = StepInterval_Fast; + + StartFlag2++; + + Current_Step_Count[2]++; + Step_Status &= ~2; + } + else + { + Step_M2_Stop(); + Step_Status |= 2; + StartFlag2 = 0; + Step_Interval2 = 0; + } + } + + if((Step_Status & 0x03) == 0x03)Step_pos++; + break; + case 1: + if(Step_Interval3) + { + Step_Interval3 -- ; + } + else + { + if(Current_Step_Count[3] > Target_Step_Count[3]) + { + Step_M3_Process(1); + if(StartFlag3 < 511)Step_Interval3 = StepInterval_Slow; + else Step_Interval3 = StepInterval_Fast; + + StartFlag3++; + + Current_Step_Count[3]--; + Step_Status &= ~4; + } + else if(Current_Step_Count[3] < Target_Step_Count[3]) + { + Step_M3_Process(0); + if(StartFlag3 < 511)Step_Interval3 = StepInterval_Slow; + else Step_Interval3 = StepInterval_Fast; + + StartFlag3++; + + Current_Step_Count[3]++; + Step_Status &= ~4; + } + else + { + Step_M3_Stop(); + Step_Status |= 4; + StartFlag3 = 0; + Step_Interval3 = 0; + } + } + + if(Step_Interval4) + { + Step_Interval4 -- ; + } + else + { + if(Current_Step_Count[4] > Target_Step_Count[4]) + { + Step_M4_Process(1); + if(StartFlag4 < 511)Step_Interval4 = StepInterval_Slow; + else Step_Interval4 = StepInterval_Fast; + + StartFlag4++; + + Current_Step_Count[4]--; + Step_Status &= ~8; + } + else if(Current_Step_Count[4] < Target_Step_Count[4]) + { + Step_M4_Process(0); + if(StartFlag4 < 511)Step_Interval4 = StepInterval_Slow; + else Step_Interval4 = StepInterval_Fast; + + StartFlag4++; + + Current_Step_Count[4]++; + Step_Status &= ~8; + } + else + { + Step_M4_Stop(); + Step_Status |= 8; + StartFlag4 = 0; + Step_Interval4 = 0; + } + } + + + if((Step_Status & 0x0C) == 0x0C)Step_pos++; + + break; + case 2: + if(Step_Interval5)// RA is 3 Dan + { + Step_Interval5 -- ; + } + else + { + if(Current_Step_Count[5] > Target_Step_Count[5]) // RA is 3 Dan + { + Step_M5_Process(1); + Step_Interval5 = 3; + Current_Step_Count[5]--; + Step_Status &= ~0x10; + } + else if(Current_Step_Count[5] < Target_Step_Count[5]) + { + Step_M5_Process(0); + Step_Interval5 = 3; + Current_Step_Count[5]++; + Step_Status &= ~0x10; + } + else + { + Step_M5_Stop(); + Step_Status |= 0x10; + Step_Interval5 = 0; + } + } + + if(Step_Interval6) + { + Step_Interval6 -- ; + } + else + { + if(Current_Step_Count[6] > Target_Step_Count[6]) + { + Step_M6_Process(1); + if(StartFlag6 < 511)Step_Interval6 = StepInterval_Slow; + else Step_Interval6 = StepInterval_Fast; + + StartFlag6++; + + Current_Step_Count[6]--; + Step_Status &= ~0x20; + } + else if(Current_Step_Count[6] < Target_Step_Count[6]) + { + Step_M6_Process(0); + if(StartFlag6 < 511)Step_Interval6 = StepInterval_Slow; + else Step_Interval6 = StepInterval_Fast; + + StartFlag6++; + + Current_Step_Count[6]++; + Step_Status &= ~0x20; + } + else + { + Step_M6_Stop(); + Step_Status |= 0x20; + StartFlag6 = 0; + Step_Interval6 = 0; + } + } + + if((Step_Status & 0x30) == 0x30)Step_pos = 0; + break; + default: + Step_pos=0; + break; + } +} + + + +uint8_t s_FAN1_VEN_1_DAN; +uint8_t s_FAN1_VEN_2_DAN; +uint8_t s_FAN1_VEN_3_DAN; +uint8_t s_FAN1_VEN_4_DAN; +uint8_t s_FAN1_AIR_1_DAN; +uint8_t s_FAN1_AIR_2_DAN; +uint8_t s_FAN1_AIR_3_DAN; +uint8_t s_FAN1_AIR_4_DAN; +uint8_t s_FAN1_BYPASS_1_DAN; +uint8_t s_FAN1_BYPASS_2_DAN; +uint8_t s_FAN1_BYPASS_3_DAN; +uint8_t s_FAN1_BYPASS_4_DAN; + +uint8_t s_FAN2_VEN_1_DAN; +uint8_t s_FAN2_VEN_2_DAN; +uint8_t s_FAN2_VEN_3_DAN; +uint8_t s_FAN2_VEN_4_DAN; +uint8_t s_FAN2_AIR_1_DAN; +uint8_t s_FAN2_AIR_2_DAN; +uint8_t s_FAN2_AIR_3_DAN; +uint8_t s_FAN2_AIR_4_DAN; +uint8_t s_FAN2_BYPASS_1_DAN; +uint8_t s_FAN2_BYPASS_2_DAN; +uint8_t s_FAN2_BYPASS_3_DAN; +uint8_t s_FAN2_BYPASS_4_DAN; + + +extern int16_t Volum1_value, Volum2_value; + +extern uint8_t Rommcon_Version; + + +uint8_t Fan1_Speed = 0, Fan2_Speed = 0; +uint8_t Target_Fan1_Speed = 0, Target_Fan2_Speed = 0; + +uint8_t Pre_Run_Mode = 100; +uint16_t Auto_Time = 0; +uint16_t Damper_wait_time = 0; + +volatile uint8_t Vsp_Mode[5] = {0,}; +volatile uint8_t Pre_Vsp_Mode = 0; + +float Pre_Fan1_pwm = 0; +float Pre_Fan2_pwm = 0; + +uint8_t Motor_Off_Count; +void PWM_out_process(void) +{ + float Fan1_pwm = 0, Fan2_pwm = 0; + + if((Fan_Mode != 0)||(RJ_Vsp_Mode == RX_DATA_MODE_VSP)) + { + BLDC_PW = 0; // ON + Motor_Off_Count = 0; + } + else if((Fan_Mode == 0) && (Fan1_Speed == 0) && (Fan2_Speed == 0)) + { + Motor_Off_Count++; + + if(Motor_Off_Count >= 5) + { + BLDC_PW = 1; // OFF + Motor_Off_Count = 5; + } + } + Fan1_pwm = (float)(BLDC_SPEED_TABLE[Fan1_Speed] + BLDC_SPEED_TABLE[Fan1_Speed]*Volum1_value/1000); +// if(Fan1_Speed > 50) Fan1_pwm -= (float)((BLDC_SPEED_TABLE[Fan1_Speed]-BLDC_SPEED_TABLE[50])*Volum1_value/10000); +// else if(Fan1_Speed < 50)Fan1_pwm += (float)((BLDC_SPEED_TABLE[50]-BLDC_SPEED_TABLE[Fan1_Speed])*Volum1_value/10000); + + Fan2_pwm = (float)(BLDC_SPEED_TABLE[Fan2_Speed] + BLDC_SPEED_TABLE[Fan2_Speed]*Volum2_value/1000); +// if(Fan2_Speed > 50) Fan2_pwm += (float)((BLDC_SPEED_TABLE[Fan2_Speed]-BLDC_SPEED_TABLE[50])*Volum2_value/100); +// else if(Fan2_Speed < 50)Fan2_pwm -= (float)((BLDC_SPEED_TABLE[50]-BLDC_SPEED_TABLE[Fan2_Speed])*Volum2_value/100); + + + if(Fan1_pwm > 10000)Fan1_pwm = 10000;if(Fan1_pwm < 0)Fan1_pwm = 0; + if(Fan2_pwm > 10000)Fan2_pwm = 10000;if(Fan2_pwm < 0)Fan2_pwm = 0; + + Fan1_pwm = 10000 - Fan1_pwm; + Fan2_pwm = 10000 - Fan2_pwm; + + if(Pre_Fan1_pwm != Fan1_pwm)BLDC1_Duty_Change((uint32_t)Fan1_pwm); + if(Pre_Fan2_pwm != Fan2_pwm)BLDC2_Duty_Change((uint32_t)Fan2_pwm); + + Pre_Fan1_pwm = Fan1_pwm; + Pre_Fan2_pwm = Fan2_pwm; +} + + +extern uint8_t Vsp_Select; +uint8_t Pre_Auto_Mode = 0; +uint8_t Pre_Auto_Fan_Mode = 0; +uint16_t Auto_Mode_Timer = 0; + +void Fan_Speed_process(void) // 100ms +{ + uint8_t i = 0; + + if((Fan_Mode == 0)&&(Run_Mode == MODE_VENTILATION)&&(RJ_Vsp_Mode != RX_DATA_MODE_VSP)&&(Vsp_Mode[1] != 0x10)) + { + Power_off_process(0); + + for(i=1; i<7; i++)Diffuser_Power[i] = 0; //////diffuser off + + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + + if(Fan1_Speed > Target_Fan1_Speed)Fan1_Speed--; + if(Fan2_Speed > Target_Fan2_Speed)Fan2_Speed--; + + PWM_out_process(); + + if((Fan1_Speed == 0) && (Fan2_Speed == 0)) + { + Damper_Mode(MODE_OFF); + Diffuser_Damper_process(MODE_OFF); + } + return; + } + + + //if(Vsp_Mode == VSP_SETTING_MODE) + if((Vsp_Mode[1] == 0x10)||(RJ_Vsp_Mode == RX_DATA_MODE_VSP)) + { + Pre_Vsp_Mode = Vsp_Mode[1]; + + if((Vsp_Select >= 0x10)&&(Vsp_Select <= 0x20)) + { + + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + Damper_Mode(MODE_OFF); + goto PASS1; + } + + if(Vsp_Select <= 4)//vent + { + Damper_Mode(MODE_VENTILATION); + Target_Fan1_Speed = Test_Fan1_Speed; + Target_Fan2_Speed = Test_Fan2_Speed; + } + else if(Vsp_Select <= 5) // bypass + { + Damper_Mode(MODE_BYPASS); + Target_Fan1_Speed = Test_Fan1_Speed; + Target_Fan2_Speed = Test_Fan2_Speed; + } + else if(Vsp_Select <= 9) //air + { + Damper_Mode(MODE_AIRCLEAN); + Target_Fan1_Speed = Test_Fan1_Speed; + Target_Fan2_Speed = Test_Fan2_Speed; + } + else if(Vsp_Select == 0x25) + { + Filter_Rpm_Auto_Cal_Process(); + } + + goto PASS1; + } + + RPM_Auto_Cal_Start = 0; + + if(Run_Mode == MODE_VENTILATION) + { + if((Pre_Run_Mode != MODE_VENTILATION)||(Power_On == 0)) + { + Power_On = 1; + for(i=1; i<7; i++)Diffuser_Power[i] = 1; //////diffuser on + Target_Fan1_Speed = 0; // off + Target_Fan2_Speed = 0; // off + + Damper_wait_time = 5; //0.5sec + } + else + { + if((Fan1_Speed != 0)||(Fan2_Speed != 0)) + { + if(Damper_wait_time == 5)goto PASS1; + } + Damper_Mode(MODE_VENTILATION); + + + + if(Step_Status != 0x3F)goto PASS1; + + if(Damper_wait_time == 1) + { + //if(Target_Fan1_Speed == 0)Target_Fan1_Speed = s_FAN1_VEN_1_DAN; // default + //if(Target_Fan2_Speed == 0)Target_Fan2_Speed = s_FAN2_VEN_1_DAN; // default + } + + if(Damper_wait_time)Damper_wait_time--; + else + { + ; + } + } + } + else if(Run_Mode == MODE_AUTO) + { + + if((Pre_Run_Mode != MODE_AUTO)||(Power_On == 0)) + { + Power_On = 1; + for(i=1; i<7; i++)Diffuser_Power[i] = 1; //////diffuser on + Target_Fan1_Speed = 0; // off + Target_Fan2_Speed = 0; // off + + Damper_wait_time = 5; //0.5sec + } + else + { + if((Fan1_Speed != 0)||(Fan2_Speed != 0)) + { + if(Damper_wait_time == 5)goto PASS1; + } + Damper_Mode(MODE_VENTILATION); + + + if(Step_Status != 0x3F)goto PASS1; + + if(Damper_wait_time == 1) + { + //if(Target_Fan1_Speed == 0)Target_Fan1_Speed = s_FAN1_VEN_1_DAN; // default + //if(Target_Fan2_Speed == 0)Target_Fan2_Speed = s_FAN2_VEN_1_DAN; // default + } + + if(Damper_wait_time)Damper_wait_time--; + else + { + ; + } + } + } + else if(Run_Mode == MODE_BYPASS) + { + if((Pre_Run_Mode != MODE_BYPASS)||(Power_On == 0)) + { + Power_On = 1; + for(i=1; i<7; i++)Diffuser_Power[i] = 1; //////diffuser on + Target_Fan1_Speed = 0; // off + Target_Fan2_Speed = 0; // off + + Damper_wait_time = 5; //0.5sec + } + else + { + if((Fan1_Speed != 0)||(Fan2_Speed != 0)) + { + if(Damper_wait_time == 5)goto PASS1; + } + Damper_Mode(MODE_BYPASS); + + if(Step_Status != 0x3F)goto PASS1; + + if(Damper_wait_time == 1) + { + // if(Target_Fan1_Speed == 0)Target_Fan1_Speed = s_FAN1_VEN_1_DAN; // default + // if(Target_Fan2_Speed == 0)Target_Fan2_Speed = s_FAN2_VEN_1_DAN; // default + } + + if(Damper_wait_time)Damper_wait_time--; + else + { + ; + } + } + } + else if(Run_Mode == MODE_AIRCLEAN) + { + if((Pre_Run_Mode != MODE_AIRCLEAN)||(Power_On == 0)) + { + Power_On = 1; + for(i=1; i<7; i++)Diffuser_Power[i] = 1; //////diffuser on + Target_Fan1_Speed = 0; // off + Target_Fan2_Speed = 0; // off + + Damper_wait_time = 5; //0.5sec + } + else + { + if((Fan1_Speed != 0)||(Fan2_Speed != 0)) + { + if(Damper_wait_time == 5)goto PASS1; + } + Damper_Mode(MODE_AIRCLEAN); + + if(Step_Status != 0x3F)goto PASS1; + + if(Damper_wait_time == 1) + { + // if(Target_Fan1_Speed == 0)Target_Fan1_Speed = s_FAN1_VEN_1_DAN; // default + // if(Target_Fan2_Speed == 0)Target_Fan2_Speed = 0; // default + } + + if(Damper_wait_time)Damper_wait_time--; + else + { + ; + } + } + + } + else if(Run_Mode == MODE_FAN_TEST) + { + if(Vsp_Select <= 4) // vent + { + Damper_Mode(MODE_VENTILATION); + } + else if(Vsp_Select == 5)//bypass + { + Damper_Mode(MODE_BYPASS); + } + else // air 6,7,8 + { + Damper_Mode(MODE_AIRCLEAN); + } + Target_Fan1_Speed = Test_Fan1_Speed; + Target_Fan2_Speed = Test_Fan2_Speed; + } + +PASS1: + + if((Vsp_Mode[1] == 0x10)||(RJ_Vsp_Mode == RX_DATA_MODE_VSP)) + { + ; + } + else + { + Diffuser_Damper_process(Run_Mode); + } + + if(Fan1_Speed > Target_Fan1_Speed)Fan1_Speed--; + else if(Fan1_Speed < Target_Fan1_Speed)Fan1_Speed++; + + if(Fan2_Speed > Target_Fan2_Speed)Fan2_Speed--; + else if(Fan2_Speed < Target_Fan2_Speed)Fan2_Speed++; + + + PWM_out_process(); + + + Pre_Run_Mode = Run_Mode; + +} + + +extern float Float_Aeverage_calculator(float val, float * array_val); + +float rpm1_buff[20]={0,}; +float rpm2_buff[20]={0,}; + +extern volatile uint32_t Bldc1_signal, Bldc2_signal; + +uint32_t urpm1=0, urpm2=0; + +void Bldc_check(void) +{ + float rpm1=0, rpm2=0; + + rpm1 = (float)Bldc1_signal; + rpm2 = (float)Bldc2_signal; + Bldc1_signal = Bldc2_signal = 0; + + rpm1 = rpm1*60/12; + rpm2 = rpm2*60/12; + + urpm1 = (uint32_t)Float_Aeverage_calculator(rpm1, rpm1_buff); + urpm2 = (uint32_t)Float_Aeverage_calculator(rpm2, rpm2_buff); + + Filter_RPM_Check(); +} + + +extern uint32_t urpm1, urpm2; + + +uint8_t Fan1_ErrCount = 0, Fan2_ErrCount = 0; +void Fan_Error_Check(void) +{ + + if(Run_Mode == MODE_FAN_TEST)return; + if(Power_On == 0)return; + + if((Fan1_Speed >= s_FAN1_VEN_1_DAN) && (urpm1 == 0)) + { + if(Fan1_ErrCount++ > 100){Fan1_ErrCount = 0; Err_Code |= ERROR_SA_FAN;Power_off_process(1);} + } + else if((Fan1_Speed >= s_FAN1_VEN_1_DAN) && (urpm1 != 0)) + { + Fan1_ErrCount = 0; + Err_Code &= ~ERROR_SA_FAN; + } + + if((Fan2_Speed >= s_FAN2_VEN_1_DAN) && (urpm2 == 0)) + { + if(Fan2_ErrCount++ > 100){Fan2_ErrCount = 0; Err_Code |= ERROR_EA_FAN;Power_off_process(1);} + } + else if((Fan2_Speed >= s_FAN2_VEN_1_DAN) && (urpm2 != 0)) + { + Fan2_ErrCount = 0; + Err_Code &= ~ERROR_EA_FAN; + } +} + +void Fan_Speed_Setting(uint8_t r_mode, uint8_t f_speed) // Run_Mode, fanspeed +{ + if(r_mode == MODE_VENTILATION) + { + switch(f_speed) + { + case 1: + Target_Fan1_Speed = s_FAN1_VEN_1_DAN; + Target_Fan2_Speed = s_FAN2_VEN_1_DAN; + break; + case 2: + Target_Fan1_Speed = s_FAN1_VEN_2_DAN; + Target_Fan2_Speed = s_FAN2_VEN_2_DAN; + break; + case 3: + Target_Fan1_Speed = s_FAN1_VEN_3_DAN; + Target_Fan2_Speed = s_FAN2_VEN_3_DAN; + break; + case 4: + Target_Fan1_Speed = s_FAN1_VEN_4_DAN; + Target_Fan2_Speed = s_FAN2_VEN_4_DAN; + break; + default: + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + break; + } + } + else if(r_mode == MODE_AUTO) + { + if(Auto_Mode == MODE_VENTILATION+1) + { + switch(f_speed) + { + case 1: + Target_Fan1_Speed = s_FAN1_VEN_1_DAN; + Target_Fan2_Speed = s_FAN2_VEN_1_DAN; + break; + case 2: + Target_Fan1_Speed = s_FAN1_VEN_2_DAN; + Target_Fan2_Speed = s_FAN2_VEN_2_DAN; + break; + case 3: + Target_Fan1_Speed = s_FAN1_VEN_3_DAN; + Target_Fan2_Speed = s_FAN2_VEN_3_DAN; + break; + case 4: + Target_Fan1_Speed = s_FAN1_VEN_4_DAN; + Target_Fan2_Speed = s_FAN2_VEN_4_DAN; + break; + default: + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + break; + } + } + else if(Auto_Mode == MODE_AIRCLEAN+1) + { + switch(f_speed) + { + case 1: + Target_Fan1_Speed = s_FAN1_AIR_1_DAN; + Target_Fan2_Speed = 0;//s2 400 // s_FAN2_AIR_1_DAN; + break; + case 2: + Target_Fan1_Speed = s_FAN1_AIR_2_DAN; + Target_Fan2_Speed = 0;//s2 400 / s_FAN2_AIR_2_DAN; + break; + case 3: + Target_Fan1_Speed = s_FAN1_AIR_3_DAN; + Target_Fan2_Speed = 0;//s2 400 / s_FAN2_AIR_3_DAN; + break; + case 4: + Target_Fan1_Speed = s_FAN1_AIR_4_DAN; + Target_Fan2_Speed = 0;//s2 400 / s_FAN2_AIR_3_DAN; + break; + default: + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + break; + } + } + else // AUTO MODE NONE + { + switch(f_speed) + { + case 1: + Target_Fan1_Speed = s_FAN1_VEN_1_DAN; + Target_Fan2_Speed = s_FAN2_VEN_1_DAN; + break; + case 2: + Target_Fan1_Speed = s_FAN1_VEN_2_DAN; + Target_Fan2_Speed = s_FAN2_VEN_2_DAN; + break; + case 3: + Target_Fan1_Speed = s_FAN1_VEN_3_DAN; + Target_Fan2_Speed = s_FAN2_VEN_3_DAN; + break; + case 4: + Target_Fan1_Speed = s_FAN1_VEN_4_DAN; + Target_Fan2_Speed = s_FAN2_VEN_4_DAN; + break; + default: + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + break; + } + } + } + else if(r_mode == MODE_AIRCLEAN) + { + switch(f_speed) + { + case 1: + Target_Fan1_Speed = s_FAN1_AIR_1_DAN; + Target_Fan2_Speed = 0;//s2 400 // s_FAN2_AIR_1_DAN; + break; + case 2: + Target_Fan1_Speed = s_FAN1_AIR_2_DAN; + Target_Fan2_Speed = 0;//s2 400 / s_FAN2_AIR_2_DAN; + break; + case 3: + Target_Fan1_Speed = s_FAN1_AIR_3_DAN; + Target_Fan2_Speed = 0;//s2 400 / s_FAN2_AIR_3_DAN; + break; + case 4: + Target_Fan1_Speed = s_FAN1_AIR_4_DAN; + Target_Fan2_Speed = 0;//s2 400 / s_FAN2_AIR_3_DAN; + break; + default: + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + break; + } + } + else if(r_mode == MODE_BYPASS) + { + switch(f_speed) + { + case 1: + Target_Fan1_Speed = s_FAN1_BYPASS_1_DAN; ; + Target_Fan2_Speed = s_FAN2_BYPASS_1_DAN; + break; + case 2: + Target_Fan1_Speed = s_FAN1_BYPASS_2_DAN; + Target_Fan2_Speed = s_FAN2_BYPASS_2_DAN; + break; + case 3: + Target_Fan1_Speed = s_FAN1_BYPASS_3_DAN; + Target_Fan2_Speed = s_FAN2_BYPASS_3_DAN; + break; + case 4: + Target_Fan1_Speed = s_FAN1_BYPASS_4_DAN; + Target_Fan2_Speed = s_FAN2_BYPASS_4_DAN; + break; + default: + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + break; + } + } + + +} + + +void Filter_Rpm_Auto_Cal_Process(void) +{ + if(RPM_Auto_Cal_Start == 0) + { + RPM_Auto_Cal_Start = 1; + Rpm_Auto_Pos = 0; + } + + RPM_Auto_Cal_Status = 1; + + switch(Rpm_Auto_Pos) + { + case 0: + Damper_Mode(MODE_VENTILATION); + Rpm_Auto_Delay = 50; //5sec + Rpm_Auto_Pos++; + break; + case 1: + if(Rpm_Auto_Delay){Rpm_Auto_Delay--;break;} + Target_Fan1_Speed = s_FAN1_VEN_2_DAN; ////////////////// S1400 + Target_Fan2_Speed = s_FAN2_VEN_2_DAN; + Rpm_Auto_Delay = 500; //50sec + Rpm_Auto_Pos++; + break; + case 2: + if(Rpm_Auto_Delay){Rpm_Auto_Delay--;break;} + Test_RPM_Vent_Reference[1] = (uint16_t)urpm2; ////////////////// S400 + Rpm_Auto_Pos++; + break; + case 3: + Target_Fan1_Speed = s_FAN1_VEN_3_DAN; ////////////////// S400 + Target_Fan2_Speed = s_FAN2_VEN_3_DAN; + Rpm_Auto_Delay = 400; //50sec + Rpm_Auto_Pos++; + break; + case 4: + if(Rpm_Auto_Delay){Rpm_Auto_Delay--;break;} + Test_RPM_Vent_Reference[2] = (uint16_t)urpm2; ////////////////// S400 + Target_Fan1_Speed = 0; + Target_Fan2_Speed = 0; + Rpm_Auto_Delay = 50; //5sec + Rpm_Auto_Pos++; + break; + case 5: + if(Rpm_Auto_Delay){Rpm_Auto_Delay--;break;} + Damper_Mode(MODE_OFF); + Rpm_Auto_Delay = 50; //3sec + Rpm_Auto_Pos++; + break; + case 6: + if(Rpm_Auto_Delay){Rpm_Auto_Delay--;break;} + EEP_Save_Flag = 1; + Rpm_Auto_Pos++; + break; + default: + RPM_Auto_Cal_Status = 0; + break; + + } +} + + +void Filter_RPM_Check(void)//1sec +{ + float sDelta = 0; + + //if(Filter_timer_change <= 3000)return; //TEST + + if((Fan1_Speed == Target_Fan1_Speed)&&(Fan_Mode >= 2)) + { + if(Target_Fan1_Speed != 0)RPM_Check_Start = 1; + else RPM_Check_Start = 0; + } + else + { + RPM_Check_Start = 0; + } + + + if(RPM_Check_Start == 1) + { + if(RPM_Stable_Timer++ >= 60) // 1min + { + RPM_Stable_Timer = 60; + + switch(Fan_Mode) + { + case 0: + break; + case 1: + break; + case 2: + sDelta = (float)urpm2 - (float)RPM_Vent_Reference[1]; + if((sDelta > RPM_Vent_Delta[1])&&(RPM_Vent_Delta[1] != 0)) + { + Err_Code |= ERROR_FILTER_CHANGE; + } + break; + case 3: + sDelta = (float)urpm2 - (float)RPM_Vent_Reference[2]; + if((sDelta > RPM_Vent_Delta[2])&&(RPM_Vent_Delta[2] != 0)) + { + Err_Code |= ERROR_FILTER_CHANGE; + } + break; + default: + break; + } + } + } + else + { + RPM_Stable_Timer = 0; + } + +} + +uint8_t Total_Air_Volume = 0, Pre_Total_Air_Volume = 0; + +uint8_t Pre_Diffuser_mode = 0; +uint16_t Diffuser_mode_change_timer = 0; +uint8_t Diffuser_mode_type = 0; +uint16_t Get_Air_Volume_Timer = 0; + +uint8_t First_Diffuser_excute_flag = 0; +uint16_t Diffuser_Damper_process(uint8_t mode)//100ms +{ + if(Focus_Mode_RunTime)Focus_Mode_RunTime--; + + + if(Diffuser_mode_change_timer == 0) + { + Diffuser_mode_change_timer = 180;//about 24sec + + if((Pre_Total_Air_Volume == 0) && (Total_Air_Volume != 0)) + { + Diffuser_mode_type = 4; + } + else if((Pre_Total_Air_Volume != 0) && (Total_Air_Volume == 0)) + { + Diffuser_mode_type = 3; + } + else if(Pre_Total_Air_Volume > Total_Air_Volume) //dicrease + { + Diffuser_mode_type = 3; + } + else //increase + { + Diffuser_mode_type = 4; + } + + Pre_Total_Air_Volume = Total_Air_Volume; + + Pre_Auto_Mode = Auto_Mode; + } + else + { + if((Pre_Diffuser_mode == mode)&&(First_Diffuser_excute_flag == 0)) + { + // Fan_Speed_Setting(Run_Mode, Fan_Mode); + } + } + + if(Diffuser_mode_change_timer == 180) + { + switch(Diffuser_mode_type) + { + case 1: // power on + case 4: // mode change - Air_volum increse + Diffuser_Dmp_Ang_SA[1] = Memory_Diffuser_Dmp_Ang_SA[1]; + Diffuser_Dmp_Ang_RA[1] = Memory_Diffuser_Dmp_Ang_RA[1]; + Diffuser_Dmp_Ang_SA[2] = Memory_Diffuser_Dmp_Ang_SA[2]; + Diffuser_Dmp_Ang_RA[2] = Memory_Diffuser_Dmp_Ang_RA[2]; + + + //Diffuser_Air_quality[1] = Memory_Diffuser_Air_quality[1]; + //Diffuser_Air_quality[2] = Memory_Diffuser_Air_quality[2]; + break; + case 2: // power off + case 3: // mode change - Air_volum dicrese + Fan_Speed_Setting(Run_Mode, Fan_Mode); + break; + default: + break; + } + } + else if(Diffuser_mode_change_timer == 120) + { + switch(Diffuser_mode_type) + { + case 1: // power on + case 4: // mode change - Air_volum increse + case 2: // power off + case 3: // mode change - Air_volum dicrese + + Diffuser_Dmp_Ang_SA[3] = Memory_Diffuser_Dmp_Ang_SA[3]; + Diffuser_Dmp_Ang_RA[3] = Memory_Diffuser_Dmp_Ang_RA[3]; + Diffuser_Dmp_Ang_SA[4] = Memory_Diffuser_Dmp_Ang_SA[4]; + Diffuser_Dmp_Ang_RA[4] = Memory_Diffuser_Dmp_Ang_RA[4]; + + + //Diffuser_Air_quality[3] = Memory_Diffuser_Air_quality[3]; + //Diffuser_Air_quality[4] = Memory_Diffuser_Air_quality[4]; + break; + default: + break; + } + } + else if(Diffuser_mode_change_timer == 60) + { + switch(Diffuser_mode_type) + { + case 1: // power on + case 4: // mode change - Air_volum increse + Fan_Speed_Setting(Run_Mode, Fan_Mode); + break; + case 2: // power off + case 3: // mode change - Air_volum dicrese + Diffuser_Dmp_Ang_SA[1] = Memory_Diffuser_Dmp_Ang_SA[1]; + Diffuser_Dmp_Ang_RA[1] = Memory_Diffuser_Dmp_Ang_RA[1]; + Diffuser_Dmp_Ang_SA[2] = Memory_Diffuser_Dmp_Ang_SA[2]; + Diffuser_Dmp_Ang_RA[2] = Memory_Diffuser_Dmp_Ang_RA[2]; + + //Diffuser_Air_quality[1] = Memory_Diffuser_Air_quality[1]; + //Diffuser_Air_quality[2] = Memory_Diffuser_Air_quality[2]; + break; + default: + break; + } + } + if(Diffuser_mode_change_timer)Diffuser_mode_change_timer--; + + Pre_Diffuser_mode = mode; + + return(Diffuser_mode_change_timer); + +} diff --git a/program/User/MyMotor.h b/program/User/MyMotor.h new file mode 100644 index 0000000..1a01d4c --- /dev/null +++ b/program/User/MyMotor.h @@ -0,0 +1,5 @@ +extern void Step_process(void); +extern uint8_t Step_motor_init(void); +extern void Fan_Error_Check(void); +extern uint8_t Limit_Mode_Process(void); + diff --git a/program/User/My_Homenet.c b/program/User/My_Homenet.c new file mode 100644 index 0000000..28b5969 --- /dev/null +++ b/program/User/My_Homenet.c @@ -0,0 +1,451 @@ +/* ============================================================================= + * My_Homenet.c — HOMENET(UART1, 115200 N81) <-> ErvDashboard 바이너리 프로토콜 + * 규격 : TestProgram/PC_ERV_Protocol.md + * (My_Uart.c 에서 분리 — PC 대시보드 통신 전용. 공용 전역/CRC16은 My_bunbaeggi.c 정의, My_define.h extern) + * ===========================================================================*/ + +#include +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" + +#include "My_define.h" + +/* ============================================================================ + * HOMENET (UART1, 115200 N81) <-> ErvDashboard 바이너리 프로토콜 (Rev2.0) + * 규격 : TestProgram/PC_ERV_Protocol.md + * 프레임 : STX(0xAA) | CMD | DATA[240] | CRC_L | CRC_H (항상 244B 고정) + * CRC-16/MODBUS (CMD~DATA[240]=241B), 리틀엔디안. 멀티바이트 값은 빅엔디안. + * PC->ERV : 명령 인자는 DATA 앞쪽, 나머지 0 패딩 + * ERV->PC : STATUS(0x81) DATA=240B 상태 / ACK(0x82) DATA[0]=echoCmd DATA[1]=result + * ==========================================================================*/ +#define HN_STX 0xAA +#define HN_STATUS 0x81 +#define HN_ACK 0x82 +#define HN_DATA_LEN 240 /* 고정 DATA 크기 */ +#define HN_STATUS_LEN 240 /* 238 + 2((꺼짐)예약 잔여초 u16) */ + +/* ---- 수신 파서 상태 (ISR 컨텍스트) ---- Hn_rx[0]=CMD, [1..240]=DATA ---- */ +static uint8_t Hn_step = 0, Hn_pos = 0, Hn_crc_lo = 0; +static uint8_t Hn_rx[1 + HN_DATA_LEN]; +/* ---- 처리 대기 명령 (메인 컨텍스트로 전달) ---- */ +volatile uint8_t Hn_cmd_ready = 0; +static uint8_t Hn_cmd = 0, Hn_cmd_pl[HN_DATA_LEN]; +/* PC대시보드 제어 → 룸컨(RJ2) 상태 푸시 래치 (My_RJ2.c roomcon_parsing 에서 소비/클리어) */ +volatile uint8_t Homenet_RJ_Request = 0; + +uint8_t Homenet_Reset_State = 0; + +void Homenet_Rx_Byte(uint8_t b) +{ + switch(Hn_step) + { + case 0: if(b == HN_STX) Hn_step = 1; break; + case 1: Hn_rx[0] = b; Hn_pos = 0; Hn_step = 2; break; /* CMD */ + case 2: /* DATA[240] */ + Hn_rx[1 + Hn_pos] = b; + if(++Hn_pos >= HN_DATA_LEN) Hn_step = 3; + break; + case 3: Hn_crc_lo = b; Hn_step = 4; break; /* 첫 CRC 바이트(표준 하위) */ + case 4: + { + /* 수신 바이트(하위먼저) -> CRC16() 반환형식(바이트스왑)으로 재구성하여 비교 */ + uint16_t rxcrc = ((uint16_t)Hn_crc_lo << 8) | b; + uint16_t i; + /* CRC 대상 = CMD + DATA[240] = Hn_rx[0..240] (241B) */ + if((CRC16(Hn_rx, (uint16_t)(1 + HN_DATA_LEN)) == rxcrc) && (Hn_cmd_ready == 0)) + { + Hn_cmd = Hn_rx[0]; + for(i = 0; i < HN_DATA_LEN; i++) Hn_cmd_pl[i] = Hn_rx[1 + i]; + Hn_cmd_ready = 1; + } + Hn_step = 0; + break; + } + default: Hn_step = 0; break; + } +} + +/* 고정 244B 송신 : STX | CMD | DATA[240] | CRC_L | CRC_H. payload는 len만큼 채우고 나머지 0 패딩 */ +static void Homenet_Send_Frame(uint8_t cmd, uint8_t *payload, uint16_t len) +{ + static uint8_t buf[1 + 1 + HN_DATA_LEN + 2]; /* 244 */ + uint16_t crc; uint16_t n = 0; uint16_t i; + + buf[n++] = HN_STX; + buf[n++] = cmd; + for(i = 0; i < HN_DATA_LEN; i++) buf[n++] = (i < len) ? payload[i] : 0; + crc = CRC16(&buf[1], (uint16_t)(1 + HN_DATA_LEN)); /* CMD+DATA[240]=241B. CRC16()는 표준 MODBUS값의 바이트스왑 반환 */ + buf[n++] = (uint8_t)(crc >> 8); /* CRC_L (표준 하위바이트) - bunbaegi 와 동일 순서 */ + buf[n++] = (uint8_t)(crc & 0xFF); /* CRC_H (표준 상위바이트) */ + + HOMENET_485_DIR = 1; + UART_Write(UART1, buf, n); + while(!(UART1->FSR & UART_FSR_TX_EMPTY_F_Msk)); + while(!(UART1->FSR & UART_FSR_TE_F_Msk)); + HOMENET_485_DIR = 0; +} + +static void hn_w16(uint8_t *p, uint16_t v){ p[0] = (uint8_t)(v >> 8); p[1] = (uint8_t)(v & 0xFF); } + +static uint8_t hn_runmode_code(void) +{ + if(Power_On != 1) return 0x00; + switch(Run_Mode) + { + case MODE_VENTILATION: return 0x01; + case MODE_AUTO: return 0x02; + case MODE_AIRCLEAN: return 0x03; + case MODE_BYPASS: return 0x04; + default: return 0x01; + } +} + +/* Room_Level(0좋음~4매우나쁨) -> 프로토콜 공기질코드(1매우나쁨~4좋음) */ +static uint8_t hn_airq_code(uint8_t level) +{ + switch(level){ case 0: return 4; case 1: return 3; case 2: return 2; default: return 1; } +} + +void Homenet_Build_Status(uint8_t *p) +{ + uint8_t r; + uint16_t i; + + for(i = 0; i < HN_STATUS_LEN; i++) p[i] = 0; + + /* --- 글로벌 0~16 --- */ + p[0] = Power_On; + p[1] = hn_runmode_code(); + p[2] = Auto_Concentrate; /* 0 분산 / 1 집중 */ + p[3] = Fan_Mode; + p[4] = (uint8_t)(((Ext_Run_Mode == 4) ? 0x01 : 0) /* 스마트수면 */ + | (Hood_YeunDong_Enable ? 0x02 : 0) /* 쾌적조리 */ + | ((Ext_Run_Mode == 1) ? 0x04 : 0)); /* 안심회복 */ + /* bit0 연동Enable / bit1 연동운전중 / bit2 후드 통신연결(폴 응답 생존) */ + p[5] = (uint8_t)((Hood_YeunDong_Enable ? 0x01 : 0) | ((Hood_Status != 0) ? 0x02 : 0) | ((Hood_Conn_Timeout != 0) ? 0x04 : 0)); + p[6] = Hyst_Preset; + hn_w16(&p[7], Pm25_Db[Hyst_Preset]); + hn_w16(&p[9], Pm10_Db[Hyst_Preset]); + hn_w16(&p[11], Voc_Db[Hyst_Preset]); + hn_w16(&p[13], Co2_Db[Hyst_Preset]); + hn_w16(&p[15], (uint16_t)Err_Code); + + /* --- 각실 17~ (14B x 4) : 거실=1, 침1=2, 침2=3, 침3=4 --- */ + for(r = 0; r < 4; r++) + { + uint8_t room = (uint8_t)(r + 1); + uint8_t o = (uint8_t)(17 + r * 14); + /* damper 비트맵 : bit0=급기(SA) 열림 / bit1=배기(RA/EA) 열림 */ + p[o+0] = (uint8_t)((Diffuser_Dmp_Ang_SA[room] != 0 ? 0x01 : 0) + | (Diffuser_Dmp_Ang_RA[room] != 0 ? 0x02 : 0)); + hn_w16(&p[o+1], SEN66_pm2p5[room]); + hn_w16(&p[o+3], SEN66_pm10p0[room]); + hn_w16(&p[o+5], (uint16_t)SEN66_VOC_value[room]); + hn_w16(&p[o+7], SEN66_CO2_value[room]); + p[o+9] = hn_airq_code(Room_Level[room]); + p[o+10] = Light_Bright[room]; + hn_w16(&p[o+11], (uint16_t)Room_Level[room]); /* 각실 부하점수 = 실 Level */ + p[o+13] = Fan_Mode; /* 최종 풍량(전체 단수) */ + } + + /* --- ERV 리셋 73 --- */ + p[73] = Homenet_Reset_State; + + /* --- VSP 74~109 : 환기1~4, 바이패스, 공청1~4 (각 SA,EA u16 BE) --- */ + hn_w16(&p[74], s_FAN1_VEN_1_DAN); hn_w16(&p[76], s_FAN2_VEN_1_DAN); + hn_w16(&p[78], s_FAN1_VEN_2_DAN); hn_w16(&p[80], s_FAN2_VEN_2_DAN); + hn_w16(&p[82], s_FAN1_VEN_3_DAN); hn_w16(&p[84], s_FAN2_VEN_3_DAN); + hn_w16(&p[86], s_FAN1_VEN_4_DAN); hn_w16(&p[88], s_FAN2_VEN_4_DAN); + hn_w16(&p[90], s_FAN1_BYPASS_1_DAN); hn_w16(&p[92], s_FAN2_BYPASS_1_DAN); + hn_w16(&p[94], s_FAN1_AIR_1_DAN); hn_w16(&p[96], s_FAN2_AIR_1_DAN); + hn_w16(&p[98], s_FAN1_AIR_2_DAN); hn_w16(&p[100], s_FAN2_AIR_2_DAN); + hn_w16(&p[102], s_FAN1_AIR_3_DAN); hn_w16(&p[104], s_FAN2_AIR_3_DAN); + hn_w16(&p[106], s_FAN1_AIR_4_DAN); hn_w16(&p[108], s_FAN2_AIR_4_DAN); + + /* --- 히스테리시스 데드밴드 테이블 110~133 : ECO/NORMAL/TURBO x (PM2.5,PM10,VOC,CO2) --- */ + for(r = 0; r < 3; r++) + { + uint8_t o = (uint8_t)(110 + r * 8); + hn_w16(&p[o+0], Pm25_Db[r]); + hn_w16(&p[o+2], Pm10_Db[r]); + hn_w16(&p[o+4], Voc_Db[r]); + hn_w16(&p[o+6], Co2_Db[r]); + } + + /* --- 모드별 오염단계 임계표 134~229 : 3프리셋 x [CO2,PM2.5,PM10,VOC] x L1~L4 --- */ + for(r = 0; r < 3; r++) + { + int o = 134 + r * 32; + uint8_t k; + for(k = 0; k < 4; k++) hn_w16(&p[o + 0 + k*2], Co2_Thr[r][k]); + for(k = 0; k < 4; k++) hn_w16(&p[o + 8 + k*2], Pm25_Thr[r][k]); + for(k = 0; k < 4; k++) hn_w16(&p[o + 16 + k*2], Pm10_Thr[r][k]); + for(k = 0; k < 4; k++) hn_w16(&p[o + 24 + k*2], Voc_Thr[r][k]); + } + + /* --- 각실 온도/습도 230~237 : 4실 x [Temp, Humi] (디퓨저 SEN66 값, 0~255 클램프) --- */ + for(r = 0; r < 4; r++) + { + uint8_t room = (uint8_t)(r + 1); + uint8_t o = (uint8_t)(230 + r * 2); + int16_t t = SEN66_temperature_value[room]; + int16_t h = SEN66_humidity_value[room]; + p[o+0] = (uint8_t)((t < 0) ? 0 : (t > 255) ? 255 : t); + p[o+1] = (uint8_t)((h < 0) ? 0 : (h > 255) ? 255 : h); + } + + /* --- (꺼짐)예약 잔여초 238~239 (u16 BE) --- */ + hn_w16(&p[238], Reserve_Remain_Sec); +} + +static uint8_t hn_set_vsp(uint8_t grp, uint8_t idx, uint8_t sa, uint8_t ea) +{ + if(grp == 0) /* 환기 idx 1~4 */ + { + switch(idx){ + case 1: s_FAN1_VEN_1_DAN=sa; s_FAN2_VEN_1_DAN=ea; break; + case 2: s_FAN1_VEN_2_DAN=sa; s_FAN2_VEN_2_DAN=ea; break; + case 3: s_FAN1_VEN_3_DAN=sa; s_FAN2_VEN_3_DAN=ea; break; + case 4: s_FAN1_VEN_4_DAN=sa; s_FAN2_VEN_4_DAN=ea; break; + default: return 1; + } + } + else if(grp == 1) /* 바이패스 idx 1 */ + { + if(idx == 1){ s_FAN1_BYPASS_1_DAN=sa; s_FAN2_BYPASS_1_DAN=ea; } else return 1; + } + else if(grp == 2) /* 공청 idx 1~4 */ + { + switch(idx){ + case 1: s_FAN1_AIR_1_DAN=sa; s_FAN2_AIR_1_DAN=ea; break; + case 2: s_FAN1_AIR_2_DAN=sa; s_FAN2_AIR_2_DAN=ea; break; + case 3: s_FAN1_AIR_3_DAN=sa; s_FAN2_AIR_3_DAN=ea; break; + case 4: s_FAN1_AIR_4_DAN=sa; s_FAN2_AIR_4_DAN=ea; break; + default: return 1; + } + } + else return 1; + return 0; +} + +/* 수신 제어명령 적용 + ACK. result 0=OK / 1=ERR */ +static void hn_apply_cmd(uint8_t cmd, uint8_t *pl, uint8_t len) +{ + uint8_t result = 0, i; + uint8_t ack[2]; + + switch(cmd) + { + case 0x01: /* CTRL_POWER [onoff] */ + if(len >= 1) + { + Power_On = pl[0] ? 1 : 0; + for(i = 1; i < 7; i++) Diffuser_Power[i] = Power_On; + /* 전원 OFF : OFF 표현은 Fan_Mode==0 && Run_Mode==MODE_VENTILATION(0). + Set_* 만 0 으로 두면 Run_Mode/Fan_Mode 가 이전값(유효모드/풍량)으로 남아 + Fan_Speed_process 의 OFF 분기가 성립 안 돼 모터가 Power_On 을 다시 켬 → 직접 0 설정 */ + if(Power_On == 0){ Set_Run_Mode = Run_Mode = MODE_VENTILATION; Set_Fan_Mode = Fan_Mode = 0; } + else + { + /* 전원 ON : 환기 모드 + 풍량 1단 (ERVSimulator HomeNetProtocol 와 동일) */ + Set_Run_Mode = Run_Mode = MODE_VENTILATION; + Set_Fan_Mode = Fan_Mode = 1; + Fan_Speed_Setting(Run_Mode, Fan_Mode); /* 즉시 반영 (모드전환과 동일) */ + } + /* 전원 토글 시 수동 댐퍼/LED 해제 → 자동 추종 복귀 */ + for(i = 1; i <= 4; i++) { Diffuser_Damper_Manual[i] = 0; Diffuser_Led_Manual[i] = 0; } + /* 각실분배기 : 전원 비트(TYPE_POWER) + 모드/풍량. 룸컨(RJ2) : 별도 래치로 확실히 푸시 */ + Command_request_type |= (TYPE_POWER | TYPE_MODE | TYPE_FAN_SPEED); + Homenet_RJ_Request |= (TYPE_MODE | TYPE_FAN_SPEED); + } else result = 1; + break; + case 0x02: /* CTRL_RUNMODE [mode] 0off/1환기/2자동/3공청/4바이패스 */ + if(len >= 1) + { + if(pl[0] == 0) Power_On = 0; + else + { + Power_On = 1; + switch(pl[0]) + { + case 1: Set_Run_Mode = MODE_VENTILATION; break; + case 2: Set_Run_Mode = MODE_AUTO; break; + case 3: Set_Run_Mode = MODE_AIRCLEAN; break; + case 4: Set_Run_Mode = MODE_BYPASS; break; + default: result = 1; break; + } + if(result == 0) + { + Run_Mode = Set_Run_Mode; + Command_request_type |= TYPE_MODE; + Homenet_RJ_Request |= TYPE_MODE; /* 룸컨이 새 모드 덮어쓰지 않게 푸시 */ + /* 운전모드 전환 시 풍량 1단 (자동 제외 - 자동은 부하점수로 결정) */ + if(Set_Run_Mode != MODE_AUTO) + { + Set_Fan_Mode = Fan_Mode = 1; + Command_request_type |= TYPE_FAN_SPEED; + Homenet_RJ_Request |= TYPE_FAN_SPEED; + /* 즉시 반영 : 풍량 단수(Total_Air_Volume)가 안 바뀌는 모드전환 + (예: 환기1단→공청1단)에서도 새 모드 VSP가 걸리도록 CTRL_FAN 과 동일하게 직접 호출 */ + Fan_Speed_Setting(Run_Mode, Fan_Mode); + } + } + } + /* 모드 전환 시 수동 댐퍼 해제 → 새 모드는 기본(전실 개방)에서 시작 */ + for(i = 1; i <= 4; i++) Diffuser_Damper_Manual[i] = 0; + } else result = 1; + break; + case 0x03: /* CTRL_FAN [speed] */ + if(len >= 1) + { + Set_Fan_Mode = Fan_Mode = pl[0]; + Command_request_type |= TYPE_FAN_SPEED; + Homenet_RJ_Request |= TYPE_FAN_SPEED; /* 룸컨이 새 풍량 덮어쓰지 않게 푸시 */ + if(Run_Mode != MODE_AUTO) Fan_Speed_Setting(Run_Mode, Fan_Mode); /* 즉시 반영(자동은 부하점수로 결정) */ + } + else result = 1; + break; + case 0x04: /* CTRL_SUBMODE [type][onoff] 1수면/2조리/3회복 */ + if(len >= 2) + { + if(pl[0] == 1) Ext_Run_Mode = pl[1] ? 4 : 0; + else if(pl[0] == 2) Hood_YeunDong_Enable = pl[1] ? 1 : 0; + else if(pl[0] == 3){ Ext_Run_Mode = pl[1] ? 1 : 0; Ext_Select_Room = 2; } + else result = 1; + /* 부가모드 변경 시 수동 댐퍼 해제 (수동 댐퍼는 환기/공청/바이패스에서만) */ + if(result == 0) for(i = 1; i <= 4; i++) Diffuser_Damper_Manual[i] = 0; + } else result = 1; + break; + case 0x05: /* CTRL_HOOD [onoff] */ + if(len >= 1) Hood_YeunDong_Enable = pl[0] ? 1 : 0; else result = 1; + break; + case 0x06: /* CTRL_HYST_PRESET [preset] */ + if(len >= 1 && pl[0] < 3) Hyst_Preset = pl[0]; else result = 1; + break; + case 0x07: /* CTRL_HYST_VALUE [preset][pm25][pm10][voc][co2] u16 BE */ + if(len >= 9 && pl[0] < 3) + { + uint8_t ps = pl[0]; + Pm25_Db[ps] = (uint16_t)(((uint16_t)pl[1] << 8) | pl[2]); + Pm10_Db[ps] = (uint16_t)(((uint16_t)pl[3] << 8) | pl[4]); + Voc_Db[ps] = (uint16_t)(((uint16_t)pl[5] << 8) | pl[6]); + Co2_Db[ps] = (uint16_t)(((uint16_t)pl[7] << 8) | pl[8]); + } else result = 1; + break; + case 0x08: /* CTRL_DAMPER [room][type 0급기SA/1배기EA][onoff] — 수동 댐퍼(비자동에서 위치 유지) */ + if(len >= 3 && pl[0] >= 1 && pl[0] <= 4) + { + uint8_t ang = pl[2] ? 110 : 0; + if(pl[1] == 0) Memory_Diffuser_Dmp_Ang_SA[pl[0]] = Diffuser_Dmp_Ang_SA[pl[0]] = ang; /* 급기 */ + else if(pl[1] == 1) Memory_Diffuser_Dmp_Ang_RA[pl[0]] = Diffuser_Dmp_Ang_RA[pl[0]] = ang; /* 배기 */ + else result = 1; + if(result == 0) Diffuser_Damper_Manual[pl[0]] = 1; /* 자동로직 덮어쓰기 차단(자동/모드전환 시 해제) */ + } else result = 1; + break; + case 0x09: /* CTRL_LED [room][dim] — 수동 LED : 자동 추종 해제하고 지정값 유지(모든 모드, 전원OFF만 해제) */ + if(len >= 2 && pl[0] >= 1 && pl[0] <= 4) { Light_Bright[pl[0]] = pl[1]; Diffuser_Led_Manual[pl[0]] = 1; } + else result = 1; + break; + case 0x0A: /* REQ_STATUS : 응답은 호출부에서 */ + break; + case 0x0B: /* CTRL_RESET [onoff] */ + if(len >= 1) Homenet_Reset_State = pl[0] ? 1 : 0; else result = 1; + break; + case 0x0C: /* CTRL_VSP [group][index][sa(2)][ea(2)] */ + if(len >= 6) + result = hn_set_vsp(pl[0], pl[1], + (uint8_t)(((uint16_t)pl[2] << 8) | pl[3]), + (uint8_t)(((uint16_t)pl[4] << 8) | pl[5])); + else result = 1; + break; + case 0x0D: /* CTRL_HYST_THR [preset][pollutant 0CO2/1PM2.5/2PM10/3VOC][L1~L4 u16] */ + if(len >= 10 && pl[0] < 3 && pl[1] < 4) + { + uint8_t ps = pl[0], g = pl[1], k; + uint16_t *arr = 0; + if(g == 0) arr = Co2_Thr[ps]; + else if(g == 1) arr = Pm25_Thr[ps]; + else if(g == 2) arr = Pm10_Thr[ps]; + else if(g == 3) arr = Voc_Thr[ps]; + if(arr) { for(k = 0; k < 4; k++) arr[k] = (uint16_t)(((uint16_t)pl[2 + k*2] << 8) | pl[3 + k*2]); } + else result = 1; + } + else result = 1; + break; + case 0x0E: /* CTRL_RESERVE [hours 0~8] : N시간 후 전원 OFF (0=해제) */ + if(len >= 1 && pl[0] <= 8) Reserve_Remain_Sec = (uint16_t)(pl[0] * 3600); + else result = 1; + break; + default: result = 1; break; + } + + /* 히스테리시스 프리셋/데드밴드/임계, VSP 변경은 EEPROM 영속화 */ + if(result == 0 && (cmd == 0x06 || cmd == 0x07 || cmd == 0x0C || cmd == 0x0D)) + EEP_Save_Flag = 1; + + ack[0] = cmd; ack[1] = result; + Homenet_Send_Frame(HN_ACK, ack, 2); +} + +/* 메인 루프(빠른 주기)에서 호출 : 수신 명령 처리 + REQ_STATUS 즉시 응답 */ +void Homenet_Process(void) +{ + static uint8_t status_buf[HN_STATUS_LEN]; + + if(Hn_cmd_ready) + { + uint8_t cmd = Hn_cmd, pl[HN_DATA_LEN]; uint16_t i; + for(i = 0; i < HN_DATA_LEN; i++) pl[i] = Hn_cmd_pl[i]; + Hn_cmd_ready = 0; + + hn_apply_cmd(cmd, pl, HN_DATA_LEN); + + if(cmd == 0x0A) /* REQ_STATUS */ + { + Homenet_Build_Status(status_buf); + Homenet_Send_Frame(HN_STATUS, status_buf, HN_STATUS_LEN); + } + } +} + +/* 1초 주기 STATUS 자동 송신 */ +void Homenet_Send_Status(void) +{ + static uint8_t status_buf[HN_STATUS_LEN]; + Homenet_Build_Status(status_buf); + Homenet_Send_Frame(HN_STATUS, status_buf, HN_STATUS_LEN); +} + + +void UART1_HANDLE() +{ + uint8_t u8InChar=0xFF; + uint32_t u32IntSts= UART1->ISR; + + if(u32IntSts & UART_ISR_RDA_IS_Msk) + { + u8InChar = UART_READ(UART1); /* Rx trigger level is 1 byte*/ + + Homenet_Rx_Byte(u8InChar); // HOMENET(ErvDashboard) 바이너리 프레임 수신 + } + + if(u32IntSts & UART_ISR_THRE_IS_Msk) + { +; + } +} + + +void UART1_IRQHandler(void) +{ + UART1_HANDLE(); +} diff --git a/program/User/My_Hood.c b/program/User/My_Hood.c new file mode 100644 index 0000000..d7c4b07 --- /dev/null +++ b/program/User/My_Hood.c @@ -0,0 +1,248 @@ + + +#include +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" + +#include "My_define.h" + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////// HOOD 485 ////////////////////////////////////////////// +extern uint16_t Hood_polling_timer; +extern uint8_t rx_hood_485_TimeOut; +uint8_t Tx_Hood_Buff[20], Rx_Hood_Buff[20]; +uint8_t Yeungong_Status = 0; +uint8_t Hood_Power_On = 0; +uint8_t Hood_Fan_Mode = 0; +uint8_t Hood_Control = 0; +uint8_t Hood_Rx_Complete = 0; +uint8_t Hood_Status = 0; + +uint8_t CheckSum_Creator(uint8_t *buf, uint8_t len) +{ + uint8_t i, rt; + + rt = 0; + + for(i=0; iISR; + + if(u32IntSts & UART_ISR_RDA_IS_Msk) + { + u8InChar = UART_READ(UART0); /* Rx trigger level is 1 byte*/ + + rx_hood_check(u8InChar); + rx_hood_485_TimeOut = 10; + } + + if(u32IntSts & UART_ISR_THRE_IS_Msk) + { +; + } +} + + +void UART0_IRQHandler(void) +{ + UART0_HANDLE(); +} +//---------------------------------- + +void Hood_Tx_packet(void) +{ + Tx_Hood_Buff[0] = 0xAA; + Tx_Hood_Buff[1] = 0x21; + Tx_Hood_Buff[2] = 0x01; + Tx_Hood_Buff[3] = Run_Mode; + Tx_Hood_Buff[4] = Fan_Mode; + Tx_Hood_Buff[5] = Hood_YeunDong_Enable; + Tx_Hood_Buff[6] = Yeungong_Status; + Tx_Hood_Buff[7] = 0x00; + Tx_Hood_Buff[8] = Hood_Power_On | Hood_Control; + Tx_Hood_Buff[9] = Hood_Fan_Mode | Hood_Control; + Tx_Hood_Buff[10] = 0x00; + Tx_Hood_Buff[11] = 0x00; + Tx_Hood_Buff[12] = CheckSum_Creator(Tx_Hood_Buff, 12); + + if(Hood_Control == 0x80)Hood_Control = 0; + + HOOD_485_DIR = 1; // DIR + UART_Write(UART0,Tx_Hood_Buff, 13); + while ( !(UART0->FSR & UART_FSR_TX_EMPTY_F_Msk) ); + while ( !(UART0->FSR & UART_FSR_TE_F_Msk) ); + HOOD_485_DIR = 0; // DIR; +} + +void Hood_RS485_process(void) +{ + if(Hood_Rx_Complete == 1) + { + Hood_Rx_Complete = 0; + Hood_Conn_Timeout = 1500; /* 유효 응답 수신 -> 통신연결 생존(폴 500ms 기준 ~3회 누락 허용) */ + Hood_Status = Rx_Hood_Buff[3]; +// if((Hood_Status == 1)&&(Hood_Yeundong_flag == 0))Command_request_type |= TYPE_HOOD_STATE;// add 2022.1.25 +// if((Hood_Status == 0)&&(Hood_Yeundong_flag == 1))Command_request_type |= TYPE_HOOD_STATE;// add 2022.1.25 +// Hood_Yeundong_flag = Hood_Status; + } + else + { + if(Hood_polling_timer == 0) + { + Hood_polling_timer = 500; + Hood_Tx_packet(); + } + } +} + + + +uint8_t HREV_Hood_Control = 0; +uint16_t Hood_Warming_up_Timer = 0; +uint8_t Pre_Hood_Status = 0; +uint8_t Tx_Yeundong_Delay = 0; + +/* 후드 단수 -> 환기장치 풍량 추종 매핑(사양 260613 9p 3.2) : 1->1,2->2,3->3,4->4,5->4 */ +static uint8_t Hood_Step_To_Fan(uint8_t hs) +{ + if(hs == 0) return 0; + return (hs > 4) ? 4 : hs; +} + +uint8_t Hood_process(void)//200ms +{ + if((Hood_YeunDong_Enable == 0)||(HREV_Hood_Control == 1))return(0); + + if(Hood_Status != Pre_Hood_Status) + { + if((Pre_Hood_Status == 0)&&(Hood_Status != 0)) // 후드 ON : 메이크업 에어 진입(자동/수동 일시정지) + { + My_Memory_Run_Mode = Run_Mode; + if((Run_Mode == MODE_AUTO)&&(Fan_Mode == 0))My_Memory_Fan_Mode = 1; + else My_Memory_Fan_Mode = Fan_Mode; + + Set_Run_Mode = MODE_VENTILATION; + Set_Fan_Mode = Hood_Step_To_Fan(Hood_Status); // 후드 단수 추종(사양 260613 9p 3.2) + + if(Set_Reserve_timer_sec != 0) + { + Set_Reserve_timer_sec = 0; + Command_request_type |= (TYPE_RESERVATION); + } + + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + Tx_Yeundong_Delay = 30; + } + else if(Hood_Status == 0) // 후드 OFF : 즉시 원래 모드/풍량 복귀 (메이크업 유지는 후드측 담당, 사양 260613 9p 3.3) + { + Set_Run_Mode = My_Memory_Run_Mode; + Set_Fan_Mode = My_Memory_Fan_Mode; + + if(Set_Reserve_timer_sec != 0) + { + Set_Reserve_timer_sec = 0; + Command_request_type |= (TYPE_RESERVATION); + } + + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED|TYPE_HOOD_STATE); + Hood_Yeundong_flag = 0; + Hood_Warming_up_Timer = 0; + Tx_Yeundong_Delay = 0; + } + else // 후드 단수 변경(1~5) : 메이크업 풍량 단수 추종 갱신 + { + uint8_t f = Hood_Step_To_Fan(Hood_Status); + if(Set_Fan_Mode != f) + { + Set_Fan_Mode = f; + Command_request_type |= (TYPE_FAN_SPEED); + Tx_Yeundong_Delay = 30; // 룸컨(My_RJ2)이 연동 풍량변경을 수동명령으로 오인하지 않도록 디바운스 + } + } + } + + /* 메이크업 진입/단수변경 MODE/FAN 전송 후 연동 플래그 set + 룸컨 통지. + Tx_Yeundong_Delay 는 룸컨(My_RJ2)이 연동 명령을 사용자 수동명령과 구분하는 데 사용(불변). + 조리 종료 후 잔여 배출(메이크업 유지)은 후드측이 담당하므로 여기서 롤백 타이머는 두지 않음. */ + if(Tx_Yeundong_Delay) + { + Tx_Yeundong_Delay--; + if(Tx_Yeundong_Delay == 0) + { + Hood_Yeundong_flag = 1; + Command_request_type |= TYPE_HOOD_STATE;// add 2022.1.25 + } + } + + Pre_Hood_Status = Hood_Status; + + return(1); +} diff --git a/program/User/My_RJ2.c b/program/User/My_RJ2.c new file mode 100644 index 0000000..b7184bc --- /dev/null +++ b/program/User/My_RJ2.c @@ -0,0 +1,781 @@ + +#include +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" + +#include "My_define.h" + + + +extern uint8_t Tx_roomcon232_buffer[25]; +extern uint8_t Rx_roomcon232_buffer[25]; + +extern volatile uint8_t Err_Code; +extern uint8_t Target_Fan1_Speed, Target_Fan2_Speed; + +extern volatile uint32_t Reserve_timer_sec; + + + +extern signed int In_Temperature; +extern signed int Out_Temperature; + +//-------------------- SC 0 ----------------------------------- +//-------------------- roomcon ------------------------------ + +uint8_t Rx_roomcon_TimeOut = 0; +uint8_t Rx_roomcon_Pos = 0; +void rx_roomcon_check(uint8_t data) +{ + uint8_t cksum = 0, i = 0; + + if(Rx_roomcon_TimeOut == 0)Rx_roomcon_Pos = 0; + switch(Rx_roomcon_Pos) + { + case 0: + if(data != 0xAA)break; + Rx_roomcon232_buffer[Rx_roomcon_Pos++] = data; + break; + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + Rx_roomcon232_buffer[Rx_roomcon_Pos++] = data; + break; + case 13: + for(i=0; i<13; i++)cksum ^= Rx_roomcon232_buffer[i]; + + if(cksum == data) + { + Rx_roomcon232_buffer[Rx_roomcon_Pos++] = data; + } + else + { + Rx_roomcon_Pos = 0; + } + break; + case 14: + if(data == 0xEE) + { + com_roomcon_delay = 50; + Rx_roomcon_complete = 1; + } + Rx_roomcon_Pos = 0; + break; + default: + Rx_roomcon_Pos = 0; + break; + } +} + + +volatile uint8_t Roomcon_connect_mode = 0; +uint8_t roomcon_com_count = 0; + +void com_roomcon_process(void) +{ + if(Rx_roomcon_complete == 1) + { + if(com_roomcon_delay)return; + Rx_roomcon_complete = 0; + roomcon_parsing(); + + Roomcon_connect_mode = 1; + roomcon_com_count = 0; + } +} + +uint8_t Com_Err_Flag = 0; +void RJ_Com_Err_Check(void) +{ + if(Roomcon_connect_mode == 0) + { + //Reservation_process(); + //Exception_mode_process(); + + roomcon_com_count = 0; + Com_Err_Flag = 0; + RJ_Vsp_Mode = 0; + } + else // exist roomcon + { + if(roomcon_com_count++ >= 10) + { + roomcon_com_count = 10; + Roomcon_connect_mode = 0; + Com_Err_Flag = 1; + + RJ_Vsp_Mode = 0; +// Power_off_process(1); + } + } +} + + +volatile uint32_t Set_Reserve_timer_sec = 0; +volatile uint8_t Set_Run_Mode = 0, Set_Fan_Mode = 0; + + +uint8_t Rommcon_Version = 0; +uint8_t Vsp_Select = 0; +uint8_t Heater_OnOff = 0, UV_OnOff = 0; +uint8_t Filter_Reset_Flag = 0; +uint8_t EEP_Save_Flag = 0; + +uint8_t Command_request_type = 0; +uint8_t Roomcon_Filter_Error = 0; // 2021.5.31 + + +#define COMMAND_REQUEST_FILTER_INFO 0x05 +#define COMMAND_REQUEST_SENSOR_INFO 0x06 +#define COMMAND_CONTROLL 0x07 // mode / speed / reservaion + +#define TYPE_MODE 0x01 +#define TYPE_FAN_SPEED 0x02 +#define TYPE_RESERVATION 0x04 +#define TYPE_FILTER_INFO 0x10 +#define TYPE_SENSOR_INFO 0x20 +#define TYPE_SEND_FLAG 0x80 + + +uint8_t Kijer_Enable = 0, Heater_Enable = 0, UV_Enable = 0; + +void Txbuff_init(void) +{ + uint8_t i; + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = 0; + Tx_roomcon232_buffer[2] = Run_Mode; + if(Run_Mode == MODE_AUTO)Fan_Mode = Set_Fan_Mode;///////////////// DEMO + Tx_roomcon232_buffer[3] = Fan_Mode; + Tx_roomcon232_buffer[4] = Auto_Mode; + + Tx_roomcon232_buffer[5] = (Heater_Enable|(UV_Enable<<4)|Kijer_Enable); + Tx_roomcon232_buffer[6] = 0; + Tx_roomcon232_buffer[7] = Err_Code & (ERROR_EA_FAN|ERROR_SA_FAN|ERROR_TEMP_SENSOR|ERROR_FILTER_CLEAN|ERROR_FILTER_CHANGE|ERROR_SOJA_CHANGE|ERROR_PROTECT|ERROR_SOMETIME); + Tx_roomcon232_buffer[7] |= Roomcon_Filter_Error; // 2021.5.31 + + + if(Out_Temperature < 0)Tx_roomcon232_buffer[8] = 0x01; + else Tx_roomcon232_buffer[8] = 0x00; + + if(Out_Temperature == 100) Tx_roomcon232_buffer[9] = 0xFF; + else Tx_roomcon232_buffer[9] = (uint8_t)(Out_Temperature+20); + + if(In_Temperature == 100)Tx_roomcon232_buffer[10] = 0xFF; + else Tx_roomcon232_buffer[10] = (uint8_t)(In_Temperature+20); + + Tx_roomcon232_buffer[11] = 0; //reserve hour + Tx_roomcon232_buffer[12] = 0; //reserve min + + Tx_roomcon232_buffer[13] = 0; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; +} + + + +void Spec_info_reply(void) +{ + uint8_t i; + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = RX_DATA_CONTROLL_INFO; + Tx_roomcon232_buffer[2] = SPEC_VERSION1_INFO; + Tx_roomcon232_buffer[3] = SPEC_VERSION2_INFO; + Tx_roomcon232_buffer[4] = SPEC_DEVICE_TYPE_INFO; + + Tx_roomcon232_buffer[5] = SPEC_CMH_INFO; + Tx_roomcon232_buffer[6] = SPEC_MODE_INFO; + Tx_roomcon232_buffer[7] = SPEC_HOMENET_INFO; + + Tx_roomcon232_buffer[8] = SPEC_HOOD_INFO ; // add 2022.1.25 + Tx_roomcon232_buffer[9] = 0; // add 2022.1.25 + Tx_roomcon232_buffer[10] = 0; + Tx_roomcon232_buffer[11] = 0; + Tx_roomcon232_buffer[12] = 0; + Tx_roomcon232_buffer[13] = 0; + + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; +} + + +void Rpm_info_reply(void) +{ + uint8_t i; + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = RX_DATA_RPM_INFO; + Tx_roomcon232_buffer[2] = 0x41; + Tx_roomcon232_buffer[3] = (uint8_t)((uint16_t)urpm1>>8); + Tx_roomcon232_buffer[4] = (uint8_t)((uint16_t)urpm1); + Tx_roomcon232_buffer[5] = 0; + + Tx_roomcon232_buffer[6] = 0x42; + Tx_roomcon232_buffer[7] = (uint8_t)((uint16_t)urpm2>>8); + Tx_roomcon232_buffer[8] = (uint8_t)((uint16_t)urpm2); + + Tx_roomcon232_buffer[9] = 0; + Tx_roomcon232_buffer[10] = 0; + Tx_roomcon232_buffer[11] = 0; + Tx_roomcon232_buffer[12] = 0; + Tx_roomcon232_buffer[13] = 0; + + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + +} + +void Filter_info_reply(void) +{ + uint8_t i; + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = RX_DATA_FILTER_INFO; + Tx_roomcon232_buffer[2] = 0x01; + Tx_roomcon232_buffer[3] = (uint8_t)((Filter_timer_clean>>8)&0x00FF); + Tx_roomcon232_buffer[4] = (uint8_t)(Filter_timer_clean&0x00FF); + Tx_roomcon232_buffer[5] = 0; + Tx_roomcon232_buffer[6] = 0x02; + Tx_roomcon232_buffer[7] = (uint8_t)((Filter_timer_change>>8)&0x00FF); + Tx_roomcon232_buffer[8] = (uint8_t)(Filter_timer_change&0x00FF); + Tx_roomcon232_buffer[9] = 0; + Tx_roomcon232_buffer[10] = 0x03; + Tx_roomcon232_buffer[11] = (uint8_t)((Soja_timer_change>>8)&0x00FF); + Tx_roomcon232_buffer[12] = (uint8_t)(Soja_timer_change&0x00FF); + Tx_roomcon232_buffer[13] = 0; + + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; +} + +uint8_t Hood_Yeundong_flag = 0; +void Hood_info_command(void)// add 2022.1.25 +{ + uint8_t i; + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = RX_DATA_HOOD_INFO; + + if(Hood_Yeundong_flag == 1)//on + { + Tx_roomcon232_buffer[2] = MODE_VENTILATION; + Tx_roomcon232_buffer[3] = 1; + } + else + { + Tx_roomcon232_buffer[2] = Set_Run_Mode; + Tx_roomcon232_buffer[3] = Set_Fan_Mode; + } + + + Tx_roomcon232_buffer[4] = Auto_Mode; + + Tx_roomcon232_buffer[5] = 0; + + + if((Hood_Yeundong_flag == 1) && (Hood_YeunDong_Enable == 1))//2023.02.14 Hood Enable Add + { + Tx_roomcon232_buffer[6] = 0x81; //ON + } + else + { + Tx_roomcon232_buffer[6] = 0x80; //OFF + } + + + Tx_roomcon232_buffer[7] = 0; + Tx_roomcon232_buffer[8] = 0; + Tx_roomcon232_buffer[9] = 0; + Tx_roomcon232_buffer[10] = 0; + Tx_roomcon232_buffer[11] = 0; + Tx_roomcon232_buffer[12] = 0; + Tx_roomcon232_buffer[13] = 0; + + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; +} + + +uint8_t RJ_Vsp_Mode = 0; +void roomcon_parsing(void) +{ + uint8_t i = 0; + + RJ_Vsp_Mode = Rx_roomcon232_buffer[1]; + switch(Rx_roomcon232_buffer[1]) + { + case RX_DATA_MODE_NORMAL: + + Err_Code &= ~(ERROR_FILTER_CLEAN|ERROR_FILTER_CHANGE|ERROR_SOJA_CHANGE|ERROR_PROTECT|ERROR_SOMETIME); + Err_Code |= Rx_roomcon232_buffer[7]&(ERROR_FILTER_CLEAN|ERROR_FILTER_CHANGE|ERROR_SOJA_CHANGE|ERROR_PROTECT|ERROR_SOMETIME); + + if((Command_request_type & (TYPE_MODE|TYPE_FAN_SPEED|TYPE_RESERVATION)) || Homenet_RJ_Request ) + { + Command_request_type |= Homenet_RJ_Request; /* PC대시보드 푸시 래치 병합(bunbaegi 클리어 무관) */ + if((Hood_Yeundong_flag == 1)&&(Tx_Yeundong_Delay == 0)) + { + Hood_Warming_up_Timer = 0;///////////////// + Hood_Yeundong_flag = 0; + Command_request_type |= (TYPE_HOOD_STATE); + } + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = COMMAND_CONTROLL; + + Tx_roomcon232_buffer[2] = Set_Run_Mode; + Tx_roomcon232_buffer[3] = Set_Fan_Mode; + Tx_roomcon232_buffer[4] = Auto_Mode; + + Tx_roomcon232_buffer[5] = (Heater_Enable|(UV_Enable<<4)|Kijer_Enable); + Tx_roomcon232_buffer[6] = 0; + Tx_roomcon232_buffer[7] = 0; + Tx_roomcon232_buffer[8] = 0; + Tx_roomcon232_buffer[9] = 0; + if(Command_request_type & TYPE_RESERVATION) + { + Tx_roomcon232_buffer[10] = 1; + Tx_roomcon232_buffer[11] = (uint8_t)(Set_Reserve_timer_sec/3600); //// extern setting timer + Tx_roomcon232_buffer[12] = (uint8_t)(Set_Reserve_timer_sec%3600/60); ////extern setting timer + } + else + { + Tx_roomcon232_buffer[10] = 0; + Tx_roomcon232_buffer[11] = 0; + Tx_roomcon232_buffer[12] = 0; + } + + + Tx_roomcon232_buffer[13] = 0; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + + Command_request_type |= TYPE_SEND_FLAG; + + } + else if(Command_request_type & (TYPE_HOOD_STATE))// add 2022.1.25 + { + Hood_info_command(); + } + else + { + Set_Reserve_timer_sec = (uint32_t)Rx_roomcon232_buffer[11]*3600 + (uint32_t)Rx_roomcon232_buffer[12]*60 ; + Txbuff_init(); + } + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + + break; + + case RX_DATA_MODE_EVENT: + + Run_Mode = Rx_roomcon232_buffer[2]; + if(Run_Mode != MODE_AUTO) + { + Fan_Mode = Rx_roomcon232_buffer[3]; + } + + if(Fan_Mode != 0)Err_Code &= ~(ERROR_EA_FAN|ERROR_SA_FAN); + + if(Command_request_type & TYPE_SEND_FLAG) + { + Command_request_type = 0; + Command_request_type &= ~TYPE_SEND_FLAG; + Homenet_RJ_Request = 0; /* PC대시보드 푸시 래치 소비 완료 */ + Run_Mode = Rx_roomcon232_buffer[2]; + if(Run_Mode != MODE_AUTO) + { + Fan_Mode = Rx_roomcon232_buffer[3];//DEMO + } + //if(Run_Mode != MODE_AUTO)Fan_Mode = Rx_roomcon232_buffer[3];//DEMO + //else Fan_Mode = Set_Fan_Mode; + } + else + { + + Set_Run_Mode = Run_Mode = Rx_roomcon232_buffer[2]; + Set_Fan_Mode = Fan_Mode = Rx_roomcon232_buffer[3]; + + if((Fan_Mode == 0)&&(Run_Mode == MODE_VENTILATION)&&(RJ_Vsp_Mode != RX_DATA_MODE_VSP)) + { + if((Memory_Hood_Status != Hood_Status)&&(Hood_YeunDong_Enable == 1)) + { + if(Memory_Hood_Status == 0) + { + Hood_Power_On = 0; + Hood_Fan_Mode = 0; + Hood_Control = 0x80; + } + else + { + Hood_Power_On = 1; + Hood_Fan_Mode = Memory_Hood_Status; + Hood_Control = 0x80; + } + + Hood_Status = Memory_Hood_Status; + } + + Set_Run_Mode = My_Memory_Run_Mode = 0; + Set_Fan_Mode = My_Memory_Fan_Mode = 0; + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + + Force_Damper_Mode = 0; + Ext_Run_Mode = 0; + Ext_Run_Mode_Off_Delay = 0; + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + + HREV_Hood_Control = 0; + } + + if(Hood_Yeundong_flag == 1) + { + Hood_Yeundong_flag = 0; + Command_request_type |= (TYPE_HOOD_STATE); + } + } + + + //Auto_Mode = Rx_roomcon232_buffer[4]; + Heater_OnOff = Rx_roomcon232_buffer[5]&0x01; + UV_OnOff = Rx_roomcon232_buffer[5]&0x10; + + Filter_Reset_Flag |= Rx_roomcon232_buffer[7]&0x01; + + if(Rx_roomcon232_buffer[10] == 1) + { + Set_Reserve_timer_sec = (uint32_t)Rx_roomcon232_buffer[11]*3600 + (uint32_t)Rx_roomcon232_buffer[12]*60 ; + } + + if(Run_Mode == MODE_VENTILATION) + { + for(i=1; i<7; i++)Diffuser_Run_Mode[i] = 1; ////// difuser run mode; + } + else if(Run_Mode == MODE_AUTO) + { + for(i=1; i<7; i++)Diffuser_Run_Mode[i] = 2; ////// difuser run mode; + } + else if(Run_Mode == MODE_BYPASS) + { + for(i=1; i<7; i++)Diffuser_Run_Mode[i] = 4; ////// difuser run mode; + } + else if(Run_Mode == MODE_AIRCLEAN) + { + for(i=1; i<7; i++)Diffuser_Run_Mode[i] = 8; ////// difuser run mode; + } + + for(i=1; i<7; i++)Diffuser_Fan_Speed[i] = Fan_Mode; ////// difuser fan mode; + + + + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = 0x01; + Tx_roomcon232_buffer[2] = Run_Mode; + //if(Run_Mode == MODE_AUTO)Fan_Mode = Set_Fan_Mode;///////////////// DEMO + Tx_roomcon232_buffer[3] = Fan_Mode; + + Tx_roomcon232_buffer[5] = (Heater_Enable|(UV_Enable<<4)|Kijer_Enable); + Tx_roomcon232_buffer[6] = 0; + Tx_roomcon232_buffer[7] = Err_Code & (ERROR_EA_FAN|ERROR_SA_FAN|ERROR_TEMP_SENSOR|ERROR_FILTER_CLEAN|ERROR_FILTER_CHANGE|ERROR_SOJA_CHANGE|ERROR_PROTECT|ERROR_SOMETIME); + Tx_roomcon232_buffer[7] |= Roomcon_Filter_Error; // 2021.5.31 + + if(Out_Temperature < 0)Tx_roomcon232_buffer[8] = 0x01; + else Tx_roomcon232_buffer[8] = 0x00; + + if(Out_Temperature == 100) Tx_roomcon232_buffer[9] = 0xFF; + else Tx_roomcon232_buffer[9] = (uint8_t)(Out_Temperature+20); + + if(In_Temperature == 100)Tx_roomcon232_buffer[10] = 0xFF; + else Tx_roomcon232_buffer[10] = (uint8_t)(In_Temperature+20); + + Tx_roomcon232_buffer[11] = 0; //reserve hour + Tx_roomcon232_buffer[12] = 0; //reserve min + + Tx_roomcon232_buffer[13] = 0; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + + + + break; + + + case RX_DATA_MODE_RESTART1: + Run_Mode = 0; + Fan_Mode = 0; + Reserve_hour = 0; + Reserve_timer_sec = 0; + //Reserve_Time_Update(Reserve_hour); + Err_Code = 0; + + Rommcon_Version = Rx_roomcon232_buffer[2]; + + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = 0x02; + Tx_roomcon232_buffer[2] = 0; + Tx_roomcon232_buffer[3] = 0; + Tx_roomcon232_buffer[4] = 0x10; + + Tx_roomcon232_buffer[5] = s_FAN1_VEN_1_DAN; + Tx_roomcon232_buffer[6] = s_FAN2_VEN_1_DAN; + + Tx_roomcon232_buffer[7] = s_FAN1_VEN_2_DAN; + Tx_roomcon232_buffer[8] = s_FAN2_VEN_2_DAN; + + Tx_roomcon232_buffer[9] = s_FAN1_VEN_3_DAN; + Tx_roomcon232_buffer[10] = s_FAN2_VEN_3_DAN; + + Tx_roomcon232_buffer[11] = s_FAN1_VEN_4_DAN; + Tx_roomcon232_buffer[12] = s_FAN2_VEN_4_DAN; + Tx_roomcon232_buffer[13] = 0; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + + case RX_DATA_MODE_RESTART2: + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = 0x12; + Tx_roomcon232_buffer[2] = 0; + Tx_roomcon232_buffer[3] = 0; + Tx_roomcon232_buffer[4] = 0x10; + + Tx_roomcon232_buffer[5] = s_FAN1_BYPASS_1_DAN; + Tx_roomcon232_buffer[6] = s_FAN2_BYPASS_1_DAN; + + Tx_roomcon232_buffer[7] = s_FAN1_AIR_1_DAN; + Tx_roomcon232_buffer[8] = s_FAN1_AIR_2_DAN; + Tx_roomcon232_buffer[9] = s_FAN1_AIR_3_DAN; + Tx_roomcon232_buffer[10] = s_FAN1_AIR_4_DAN; + Tx_roomcon232_buffer[11] = 0; + Tx_roomcon232_buffer[12] = 0; // + + Tx_roomcon232_buffer[13] = 0;; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + + case RX_DATA_MODE_VSP: // in test mode + + Vsp_Select = Rx_roomcon232_buffer[3]; + + switch(Vsp_Select) + { + case 1: // + Test_Fan1_Ven_1_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Ven_1_dan = Rx_roomcon232_buffer[5]; + break; + case 2: // + Test_Fan1_Ven_2_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Ven_2_dan = Rx_roomcon232_buffer[5]; + break; + case 3: // + Test_Fan1_Ven_3_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Ven_3_dan = Rx_roomcon232_buffer[5]; + break; + case 4: // + Test_Fan1_Ven_4_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Ven_4_dan = Rx_roomcon232_buffer[5]; + break; + case 5: // + Test_Fan1_Bypass_1_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Bypass_1_dan = Rx_roomcon232_buffer[5]; + break; + case 6: // + Test_Fan1_Air_1_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Air_1_dan = 0;//Rx_roomcon232_buffer[5]; + break; + case 7: // + Test_Fan1_Air_2_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Air_2_dan = 0;//Rx_roomcon232_buffer[5]; + break; + case 8: // + Test_Fan1_Air_3_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Air_3_dan = 0;//Rx_roomcon232_buffer[5]; + case 9: // + Test_Fan1_Air_4_dan = Rx_roomcon232_buffer[4]; + Test_Fan2_Air_4_dan = 0;//Rx_roomcon232_buffer[5]; + break; + default: + break; + } + + Test_Fan1_Speed = Rx_roomcon232_buffer[4]; + Test_Fan2_Speed = Rx_roomcon232_buffer[5]; + if((Vsp_Select == 6)||(Vsp_Select == 7)||(Vsp_Select == 8)||(Vsp_Select == 9))Test_Fan2_Speed = 0; + + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = 0x03; + Tx_roomcon232_buffer[2] = 0; + Tx_roomcon232_buffer[3] = Rx_roomcon232_buffer[3]; + Tx_roomcon232_buffer[4] = Rx_roomcon232_buffer[4]; + Tx_roomcon232_buffer[5] = Rx_roomcon232_buffer[5]; + + Tx_roomcon232_buffer[6] = 0; + Tx_roomcon232_buffer[7] = 0; + Tx_roomcon232_buffer[8] = 0; + + Tx_roomcon232_buffer[9] = (uint8_t)((urpm1>>8)&0x00FF); //2021.5.31 + Tx_roomcon232_buffer[10] = (uint8_t)(urpm1&0x00FF); + Tx_roomcon232_buffer[11] = (uint8_t)((urpm2>>8)&0x00FF); + Tx_roomcon232_buffer[12] = (uint8_t)(urpm2&0x00FF); + + + Tx_roomcon232_buffer[13] = 0; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + + case RX_DATA_MODE_EXIT: // out test mode + Run_Mode = Rx_roomcon232_buffer[2]; + + EEP_Save_Flag = 1; + Tx_roomcon232_buffer[0] = 0xAA; + Tx_roomcon232_buffer[1] = 0x04; + Tx_roomcon232_buffer[2] = 0; + Tx_roomcon232_buffer[3] = 0; + Tx_roomcon232_buffer[4] = 0; + Tx_roomcon232_buffer[5] = 0; + Tx_roomcon232_buffer[6] = 0; + Tx_roomcon232_buffer[7] = 0; + Tx_roomcon232_buffer[8] = 0; + Tx_roomcon232_buffer[9] = 0; + Tx_roomcon232_buffer[10] = 0; + Tx_roomcon232_buffer[11] = 0; + Tx_roomcon232_buffer[12] = 0; + + Tx_roomcon232_buffer[13] = 0; + for(i=0; i<13; i++)Tx_roomcon232_buffer[13] ^= Tx_roomcon232_buffer[i]; + Tx_roomcon232_buffer[14] = 0xEE; + + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + + break; + case RX_DATA_SENSOR_INFO: // + Command_request_type &= ~(TYPE_SENSOR_INFO); + Txbuff_init(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + + case RX_DATA_FILTER_INFO: //룸콘 + Command_request_type &= ~(TYPE_FILTER_INFO); + Filter_info_reply(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + + case RX_DATA_CONTROLL: // + if(Command_request_type & TYPE_SEND_FLAG) + { + Command_request_type &= ~TYPE_SEND_FLAG; + Run_Mode = Rx_roomcon232_buffer[2]; + if(Run_Mode != MODE_AUTO) + { + Fan_Mode = Rx_roomcon232_buffer[3];///////////////// DEMO + } + } + else + { + Set_Run_Mode = Run_Mode = Rx_roomcon232_buffer[2]; + if(Run_Mode != MODE_AUTO) + { + Set_Fan_Mode = Fan_Mode = Rx_roomcon232_buffer[3]; + } + } + //Auto_Mode = Rx_roomcon232_buffer[4]; + Heater_OnOff = Rx_roomcon232_buffer[5]&0x01; + UV_OnOff = Rx_roomcon232_buffer[5]&0x10; + + Filter_Reset_Flag |= Rx_roomcon232_buffer[7]; + + Reserve_timer_sec = (uint32_t)Rx_roomcon232_buffer[11]*3600 + (uint32_t)Rx_roomcon232_buffer[12]*60 ; + + + if(Set_Run_Mode == Run_Mode)Command_request_type &= ~TYPE_MODE; + if(Set_Fan_Mode == Fan_Mode)Command_request_type &= ~TYPE_FAN_SPEED; + + if(Reserve_timer_sec == 0){if(Set_Reserve_timer_sec == 0)Command_request_type &= ~TYPE_RESERVATION;} + else + { + if(Set_Reserve_timer_sec != 0) + { + if(((Reserve_timer_sec-1)/3600 + 1) == ((Set_Reserve_timer_sec-1)/3600 + 1))Command_request_type &= ~TYPE_RESERVATION; + } + } + Txbuff_init(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + + case RX_DATA_CONTROLL_INFO: // 룸콘 + Spec_info_reply(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + case RX_DATA_RPM_INFO: //2021.5.31 + + if(Rx_roomcon232_buffer[2] == 1)Roomcon_Filter_Error |= ERROR_FILTER_CLEAN; + else Roomcon_Filter_Error &= ~ERROR_FILTER_CLEAN; + + if(Rx_roomcon232_buffer[3] == 1)Roomcon_Filter_Error |= ERROR_FILTER_CHANGE; + else Roomcon_Filter_Error &= ~ERROR_FILTER_CHANGE; + + if(Rx_roomcon232_buffer[4] == 1)Roomcon_Filter_Error |= ERROR_SOJA_CHANGE; + else Roomcon_Filter_Error &= ~ERROR_SOJA_CHANGE; + + Rpm_info_reply(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + case RX_DATA_ERROR_CLEAR: //2021.5.31 + + if(Rx_roomcon232_buffer[1] == 0x22) + { + Err_Code &= ~(ERROR_SA_FAN|ERROR_EA_FAN); + } + Txbuff_init(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + case RX_DATA_HOOD_INFO: // add 2022.1.25 + Command_request_type &= ~(TYPE_HOOD_STATE); + Txbuff_init(); + SCUART_Write(SC0,Tx_roomcon232_buffer,15); + break; + default: + break; + + } +} + + +void SC0_IRQHandler(void) +{ + uint8_t data; + + data = SCUART_READ(SC0); + + rx_roomcon_check(data); + Rx_roomcon_TimeOut = 50; + + return; +} diff --git a/program/User/My_bunbaeggi.c b/program/User/My_bunbaeggi.c new file mode 100644 index 0000000..1e103ca --- /dev/null +++ b/program/User/My_bunbaeggi.c @@ -0,0 +1,992 @@ + +#include +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" + +#include "My_define.h" + + +uint8_t test_num1=0,test_num2=0,test_num3=0; + + +uint16_t com_bunbaegi_delay = 0; + + +volatile uint8_t Rx_bunbaegi_complete=0, Rx_homenet_complete=0, Rx_roomcon_complete=0, Rx_debug_complete=0; +volatile uint8_t Tx_bunbaegi_flag = 0, Tx_homenet_flag = 0, Tx_roomcon_flag = 0, Tx_debug_flag = 0; +volatile uint8_t Tx_display_flag=0; +uint8_t Tx_display_buffer[25], Rx_display_buffer[25]; + +uint8_t Tx_homenet_buffer[60],Tx_bunbaegi_buffer[40],Tx_roomcon232_buffer[25],Tx_debug_buffer[60]; +uint8_t Rx_homenet_buffer[60],Rx_bunbaegi_buffer[40],Rx_roomcon232_buffer[25],Rx_debug_buffer[20]; + +volatile uint8_t Reserve_hour = 0; +volatile uint8_t Pre_Reserve_hour = 0; + +extern volatile uint8_t Err_Code; +extern uint8_t Target_Fan1_Speed, Target_Fan2_Speed; + +extern volatile uint32_t Reserve_timer_sec; + +extern signed int In_Temperature; +extern signed int Out_Temperature; + +extern uint16_t InCom_polling_timer; + +uint16_t SEN66_pm1p0[7] = {0,}, SEN66_pm2p5[7] = {0,}, SEN66_pm4p0[7] = {0,}, SEN66_pm10p0[7] = {0,}; +int16_t SEN66_humidity_value[7] = {0}; +int16_t SEN66_temperature_value[7] = {0}; +int16_t SEN66_VOC_value[7] = {0}; +int16_t SEN66_NOx_value[7] = {0}; +uint16_t SEN66_CO2_value[7] = {0}; + +//uint8_t Diffuser_VSP_Mode[6] = {0}; +uint8_t Diffuser_VSP_Mode = 0; +uint8_t Diffuser_Power[7] = {0,}; +uint8_t Diffuser_Run_Mode[7] = {0,}; +uint8_t Diffuser_Fan_Speed[7] = {0,}; +uint8_t Diffuser_Dmp_Ang_SA[7] = {0,}, Memory_Diffuser_Dmp_Ang_SA[7] = {0,}; //Damper Angle +uint8_t Diffuser_Dmp_Ang_RA[7] = {0,}, Memory_Diffuser_Dmp_Ang_RA[7] = {0,}; //Damper Angle +uint8_t Diffuser_Air_quality[7] = {0,}, Memory_Diffuser_Air_quality[7] = {0,}; +/* 대시보드 수동 댐퍼 제어(CTRL_DAMPER) : 1이면 환기/공청/바이패스에서 자동 개방이 덮어쓰지 않음. + 자동/부가모드/전원OFF/모드전환 시 해제. (각실 1~4 사용) */ +uint8_t Diffuser_Damper_Manual[7] = {0,}; +/* 대시보드 수동 LED 디밍(CTRL_LED) : 1이면 자동 추종(댐퍼개방→ON/닫힘→소등)이 덮어쓰지 않음. + 모든 운전모드에서 수동값 유지, 전원OFF 시에만 해제. (각실 1~4 사용) */ +uint8_t Diffuser_Led_Manual[7] = {0,}; +/* (꺼짐)예약 잔여초 : CTRL_RESERVE 로 설정(N시간×3600), 1초마다 감소, 0 도달 시 전원 OFF. 0=예약없음. 최대 8h=28800 */ +uint16_t Reserve_Remain_Sec = 0; + +uint8_t Roomcon_Num = 5, Diffuser_Num = 6, VSP_Select_Num = 0; +uint8_t VSP_Status_Trans = 0; + +const unsigned char auchCRCHi[] = { +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, +0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, +0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, +0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, +0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, +0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, +0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, +0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, +0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, +0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, +0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, +0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, +0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, +0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, +0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +} ; + +// Table of CRC values for low-order byte +const unsigned char auchCRCLo[] = { +0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, +0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, +0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, +0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, +0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, 0x14, 0xD4, +0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, +0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, +0xF2, 0x32, 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, +0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, +0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, +0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, +0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, +0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, +0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, +0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, +0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, +0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, 0xBE, 0x7E, +0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, +0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, +0x70, 0xB0, 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, +0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, +0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, +0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, +0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, +0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, +0x43, 0x83, 0x41, 0x81, 0x80, 0x40 +} ; + +uint16_t CRC16(uint8_t *puchMsg, uint16_t usDataLen) +{ + uint8_t uchCRCHi = 0xFF ; // high CRC byte initialized + uint8_t uchCRCLo = 0xFF ; // low CRC byte initialized + uint8_t uIndex ; // will index into CRC lookup table + + while (usDataLen--) // pass through message buffer + { + uIndex = uchCRCHi ^ *puchMsg++ ; // calculate the CRC + + uchCRCHi = uchCRCLo ^ auchCRCHi[uIndex] ; + uchCRCLo = auchCRCLo[uIndex] ; + } + return ((uint16_t)uchCRCHi << 8 | (uint16_t)uchCRCLo) ; + +} + + +//-------------------- SC 1 ----------------------------------- +//-------------------- BunBaeGi ------------------------------ + +void bunbaegi_run_mode_check(void) +{ + +} + +uint8_t Packet_Type = 0; +uint8_t Rx_bunbaegi_Pos = 0; +uint8_t Packet_Length = 0; + +void rx_bunbaegi_check(uint8_t data) +{ + uint16_t iTmp = 0, icrc = 0; + + if(Rx_roomcon_TimeOut == 0)Rx_bunbaegi_Pos = 0; + switch(Rx_bunbaegi_Pos) + { + case 0: + if(data != 0xAA)break; + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + break; + case 1: + if(data != 0x01)break; + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + break; + case 2: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + if(data == 0x03){Packet_Type = 0x02;} //RoomCon + else{Packet_Type = 0x01;} //Diffuser + break; + case 3: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + Packet_Length = 39; + break; + case 4: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + if(Packet_Type == 0x02) + { + if((data == 0x01)||(data == 0x02)||(data == 0x03)) //29byte + { + Packet_Length = 39; + } + } //RoomCon + break; + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + break; + case 28: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + if(Packet_Length == 29) + { + iTmp = (uint16_t)Rx_bunbaegi_buffer[27]<<8; + icrc = iTmp + (uint16_t)Rx_bunbaegi_buffer[28] ; + if(icrc == CRC16(Rx_bunbaegi_buffer, 27)) + { + Rx_bunbaegi_complete = 1; + } + Rx_bunbaegi_Pos = 0; + } + break; + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + break; + case 38: + Rx_bunbaegi_buffer[Rx_bunbaegi_Pos++] = data; + if(Packet_Length == 39) + { + iTmp = (uint16_t)Rx_bunbaegi_buffer[37]<<8; + icrc = iTmp + (uint16_t)Rx_bunbaegi_buffer[38] ; + if(icrc == CRC16(Rx_bunbaegi_buffer, 37)) + { + Rx_bunbaegi_complete = 1; + } + Rx_bunbaegi_Pos = 0; + } + break; + default: + Rx_bunbaegi_Pos = 0; + break; + } +} + + +volatile uint8_t Bunbaegi_connect_mode = 0; +uint8_t bunbaegi_com_count = 0; + +void com_bunbaegi_process(void) +{ + if(Rx_bunbaegi_complete == 1) + { + if(com_bunbaegi_delay)return; + Rx_bunbaegi_complete = 0; + bunbaegi_parsing(); + +// Roomcon_connect_mode = 1; + bunbaegi_com_count = 0; + } +} + +uint8_t Light_Bright[6] = {0,0,0,0,0,0}; + +uint8_t sa_sel = 1; //SA ID SELECTION +uint8_t ea_sel = 1; //EA ID SELECTION +uint8_t rc_sel = 1; //ROOMCON ID SELECTION +uint8_t tx_sel = 1; //TX MODE SELECTION [1:SA],[2:EA],[3:RoomCon] + +uint8_t id_tbl[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06 }; + +uint8_t Polling_VSP_Mode = 0; + +void Bunbaegi_Polling(void) +{ + uint8_t id_1 = 0, id_2 = 0; + uint16_t icrc = 0; + uint8_t Tmp_sel = 0; + + Tx_bunbaegi_buffer[0] = 0xAA; + Tx_bunbaegi_buffer[1] = 0x10; + Tx_bunbaegi_buffer[2] = tx_sel; + + if(tx_sel == 1) // TX -> SA + { + id_2 = sa_sel; + } + else if(tx_sel == 2) + { + id_2 = ea_sel; + } + else if(tx_sel == 3) // roomcon + { + Polling_VSP_Mode = 0x00; + if(rc_sel == 1){rc_sel = 2;Polling_VSP_Mode = 0x00;} + else if(rc_sel == 2){rc_sel = 3;Polling_VSP_Mode = 0x11;} + else if(rc_sel == 3){rc_sel = 1;Polling_VSP_Mode = 0x12;} + + id_2 = 5; // room4 e����i?? roomcon + + } + id_1 = tx_sel; //sa/ea/roomcon + Tx_bunbaegi_buffer[3] = id_2; // number + + + if(tx_sel == 3) //RoomCon Polling + { + if((Diffuser_VSP_Mode == 1) && (id_2==5)) // room4 e����i?? roomcon + { + Tx_bunbaegi_buffer[4] = Diffuser_VSP_Mode; + + Tx_bunbaegi_buffer[5] = (uint8_t)s_FAN1_VEN_1_DAN; + Tx_bunbaegi_buffer[6] = (uint8_t)s_FAN2_VEN_1_DAN; + Tx_bunbaegi_buffer[7] = (uint8_t)s_FAN1_VEN_2_DAN; + Tx_bunbaegi_buffer[8] = (uint8_t)s_FAN2_VEN_2_DAN; + Tx_bunbaegi_buffer[9] = (uint8_t)s_FAN1_VEN_3_DAN; + Tx_bunbaegi_buffer[10] = (uint8_t)s_FAN2_VEN_3_DAN; + + Tx_bunbaegi_buffer[11] = (uint8_t)s_FAN1_VEN_4_DAN; + Tx_bunbaegi_buffer[12] = (uint8_t)s_FAN2_VEN_4_DAN; + Tx_bunbaegi_buffer[13] = 0; + Tx_bunbaegi_buffer[14] = 0; //5DAN + + Tx_bunbaegi_buffer[15] = (uint8_t)s_FAN1_AIR_1_DAN; + Tx_bunbaegi_buffer[16] = (uint8_t)s_FAN2_AIR_1_DAN; + Tx_bunbaegi_buffer[17] = (uint8_t)s_FAN1_AIR_2_DAN; + Tx_bunbaegi_buffer[18] = (uint8_t)s_FAN2_AIR_2_DAN; + Tx_bunbaegi_buffer[19] = (uint8_t)s_FAN1_AIR_3_DAN; + Tx_bunbaegi_buffer[20] = (uint8_t)s_FAN2_AIR_3_DAN; + + Tx_bunbaegi_buffer[21] = 0; + Tx_bunbaegi_buffer[22] = 0; //4DAN + Tx_bunbaegi_buffer[23] = 0; + Tx_bunbaegi_buffer[24] = 0; //5DAN + + Tx_bunbaegi_buffer[25] = 0; + Tx_bunbaegi_buffer[26] = 0; //BLANK + + icrc = CRC16(Tx_bunbaegi_buffer, 27); + Tx_bunbaegi_buffer[27] = (uint8_t)(icrc>>8); //CRC16 + Tx_bunbaegi_buffer[28] = (uint8_t)(icrc & 0x00FF); //CRC16 + + BUNBAGI_485_DIR = 1; + SCUART_Write(SC1, Tx_bunbaegi_buffer, 29); + while ( !(SC1->TRSR & SC_TRSR_TX_EMPTY_F_Msk) ); + delay_us(200); + BUNBAGI_485_DIR = 0; + Diffuser_VSP_Mode = 0; + } + else if((Diffuser_VSP_Mode == 2) && (id_2==5)) // room4 e����i?? roomcon + { + Tx_bunbaegi_buffer[4] = Diffuser_VSP_Mode; + + Tx_bunbaegi_buffer[5] = s_FAN1_BYPASS_1_DAN; Tx_bunbaegi_buffer[6] = s_FAN2_BYPASS_1_DAN; + Tx_bunbaegi_buffer[7] = s_FAN1_BYPASS_2_DAN; Tx_bunbaegi_buffer[8] = s_FAN2_BYPASS_2_DAN; + Tx_bunbaegi_buffer[9] = s_FAN1_BYPASS_3_DAN; Tx_bunbaegi_buffer[10] = s_FAN2_BYPASS_3_DAN; + + Tx_bunbaegi_buffer[11] = 0; Tx_bunbaegi_buffer[12] = 0; //4DAN + Tx_bunbaegi_buffer[13] = 0; Tx_bunbaegi_buffer[14] = 0; //5DAN + + Tx_bunbaegi_buffer[15] = 0; Tx_bunbaegi_buffer[16] = 0; //BLANK + + Tx_bunbaegi_buffer[17] = Roomcon_Num; + Tx_bunbaegi_buffer[18] = Diffuser_Num; + + Tx_bunbaegi_buffer[19] = 0; Tx_bunbaegi_buffer[20] = 0; //BLANK + Tx_bunbaegi_buffer[21] = 0; Tx_bunbaegi_buffer[22] = 0; //BLANK + Tx_bunbaegi_buffer[23] = 0; Tx_bunbaegi_buffer[24] = 0; //BLANK + Tx_bunbaegi_buffer[25] = 0; Tx_bunbaegi_buffer[26] = 0; //BLANK + + icrc = CRC16(Tx_bunbaegi_buffer, 27); + Tx_bunbaegi_buffer[27] = (uint8_t)(icrc>>8); //CRC16 + Tx_bunbaegi_buffer[28] = (uint8_t)(icrc & 0x00FF); //CRC16 + + BUNBAGI_485_DIR = 1; + SCUART_Write(SC1, Tx_bunbaegi_buffer, 29); + while ( !(SC1->TRSR & SC_TRSR_TX_EMPTY_F_Msk) ); + delay_us(200); + BUNBAGI_485_DIR = 0; + Diffuser_VSP_Mode = 0; + } + else if((Diffuser_VSP_Mode == 3) && (id_2==5)) // room4 e����i?? roomcon + { + Tx_bunbaegi_buffer[4] = Diffuser_VSP_Mode; + + Tx_bunbaegi_buffer[5] = (uint8_t)Test_RPM_Vent_Reference[1]; + Tx_bunbaegi_buffer[6] = (uint8_t)(Test_RPM_Vent_Reference[1]>>8); // VENT RPM REF 2DAN + Tx_bunbaegi_buffer[7] = (uint8_t)Test_RPM_Vent_Delta[1]; + Tx_bunbaegi_buffer[8] = (uint8_t)(Test_RPM_Vent_Delta[1]>>8); // VENT RPM DELTA 2DAN + Tx_bunbaegi_buffer[9] = (uint8_t)Test_RPM_Vent_Reference[2]; + Tx_bunbaegi_buffer[10] = (uint8_t)(Test_RPM_Vent_Reference[2]>>8); // VENT RPM REF 3DAN + Tx_bunbaegi_buffer[11] = (uint8_t)Test_RPM_Vent_Delta[2]; + Tx_bunbaegi_buffer[12] = (uint8_t)(Test_RPM_Vent_Delta[2]>>8);; //VENT RPM DELTA 3DAN + Tx_bunbaegi_buffer[13] = (uint8_t)Test_RPM_Air_Reference[1]; + Tx_bunbaegi_buffer[14] = (uint8_t)(Test_RPM_Air_Reference[1]>>8); //AIR RPM REF 2DAN + Tx_bunbaegi_buffer[15] = (uint8_t)Test_RPM_Air_Delta[1]; + Tx_bunbaegi_buffer[16] = (uint8_t)(Test_RPM_Air_Delta[1]>>8); //AIR RPM DELTA 2DAN + Tx_bunbaegi_buffer[17] = (uint8_t)Test_RPM_Air_Reference[2]; + Tx_bunbaegi_buffer[18] = (uint8_t)(Test_RPM_Air_Reference[2]>>8); //AIR RPM REF 3DAN + Tx_bunbaegi_buffer[19] = (uint8_t)Test_RPM_Air_Delta[2]; + Tx_bunbaegi_buffer[20] = (uint8_t)(Test_RPM_Air_Delta[2]>>8); //AIR RPM DELTA 3DAN + Tx_bunbaegi_buffer[21] = 0; Tx_bunbaegi_buffer[22] = 0; //21byte Modbus ID + Tx_bunbaegi_buffer[23] = 0; Tx_bunbaegi_buffer[24] = 0; //BLANK + Tx_bunbaegi_buffer[25] = 0; Tx_bunbaegi_buffer[26] = 0; //BLANK + + icrc = CRC16(Tx_bunbaegi_buffer, 27); + Tx_bunbaegi_buffer[27] = (uint8_t)(icrc>>8); //CRC16 + Tx_bunbaegi_buffer[28] = (uint8_t)(icrc & 0x00FF); //CRC16 + + BUNBAGI_485_DIR = 1; + SCUART_Write(SC1, Tx_bunbaegi_buffer, 29); + while ( !(SC1->TRSR & SC_TRSR_TX_EMPTY_F_Msk) ); + delay_us(200); + BUNBAGI_485_DIR = 0; + Diffuser_VSP_Mode = 0; + } + else + { + if(id_2 == 5) // room4 e����i?? roomcon + { + if(Polling_VSP_Mode == 0x11) //air qurity + { + Tx_bunbaegi_buffer[4] = 0x11; //VSP_MODE +// room1 + Tx_bunbaegi_buffer[5] = (uint8_t)(SEN66_pm10p0[3]>>8); + Tx_bunbaegi_buffer[6] = (uint8_t)(SEN66_pm10p0[3]); + Tx_bunbaegi_buffer[7] = (uint8_t)(SEN66_humidity_value[3]>>8); + Tx_bunbaegi_buffer[8] = (uint8_t)(SEN66_humidity_value[3]); + Tx_bunbaegi_buffer[9] = (uint8_t)(SEN66_temperature_value[3]>>8); + Tx_bunbaegi_buffer[10] = (uint8_t)(SEN66_temperature_value[3]); + Tx_bunbaegi_buffer[11] = (uint8_t)(SEN66_CO2_value[3]>>8); + Tx_bunbaegi_buffer[12] = (uint8_t)(SEN66_CO2_value[3]); + Tx_bunbaegi_buffer[13] = (uint8_t)(SEN66_VOC_value[3]>>8);; + Tx_bunbaegi_buffer[14] = (uint8_t)(SEN66_VOC_value[3]); + + Tx_bunbaegi_buffer[15] = 0; + Tx_bunbaegi_buffer[16] = 0; + Tx_bunbaegi_buffer[17] = 0; + Tx_bunbaegi_buffer[18] = 0; + Tx_bunbaegi_buffer[19] = 0; + Tx_bunbaegi_buffer[20] = 0; + Tx_bunbaegi_buffer[21] = 0; +//room2 + Tx_bunbaegi_buffer[22] = (uint8_t)(SEN66_pm10p0[4]>>8); + Tx_bunbaegi_buffer[23] = (uint8_t)(SEN66_pm10p0[4]); + Tx_bunbaegi_buffer[24] = (uint8_t)(SEN66_humidity_value[4]>>8); + Tx_bunbaegi_buffer[25] = (uint8_t)(SEN66_humidity_value[4]); + Tx_bunbaegi_buffer[26] = (uint8_t)(SEN66_temperature_value[4]>>8); + Tx_bunbaegi_buffer[27] = (uint8_t)(SEN66_temperature_value[4]); + Tx_bunbaegi_buffer[28] = (uint8_t)(SEN66_CO2_value[4]>>8); + Tx_bunbaegi_buffer[29] = (uint8_t)(SEN66_CO2_value[4]); + Tx_bunbaegi_buffer[30] = (uint8_t)(SEN66_VOC_value[4]>>8);; + Tx_bunbaegi_buffer[31] = (uint8_t)(SEN66_VOC_value[4]); + + Tx_bunbaegi_buffer[32] = 0; + } + else if(Polling_VSP_Mode == 0x12) //air qurity + { + Tx_bunbaegi_buffer[4] = 0x12; //VSP_MODE +// room3 + Tx_bunbaegi_buffer[5] = (uint8_t)(SEN66_pm10p0[5]>>8); + Tx_bunbaegi_buffer[6] = (uint8_t)(SEN66_pm10p0[5]); + Tx_bunbaegi_buffer[7] = (uint8_t)(SEN66_humidity_value[5]>>8); + Tx_bunbaegi_buffer[8] = (uint8_t)(SEN66_humidity_value[5]); + Tx_bunbaegi_buffer[9] = (uint8_t)(SEN66_temperature_value[5]>>8); + Tx_bunbaegi_buffer[10] = (uint8_t)(SEN66_temperature_value[5]); + Tx_bunbaegi_buffer[11] = (uint8_t)(SEN66_CO2_value[5]>>8); + Tx_bunbaegi_buffer[12] = (uint8_t)(SEN66_CO2_value[5]); + Tx_bunbaegi_buffer[13] = (uint8_t)(SEN66_VOC_value[5]>>8);; + Tx_bunbaegi_buffer[14] = (uint8_t)(SEN66_VOC_value[5]); + + Tx_bunbaegi_buffer[15] = 0; + Tx_bunbaegi_buffer[16] = 0; + Tx_bunbaegi_buffer[17] = 0; + Tx_bunbaegi_buffer[18] = 0; + Tx_bunbaegi_buffer[19] = 0; + Tx_bunbaegi_buffer[20] = 0; + Tx_bunbaegi_buffer[21] = 0; +//room4 + Tx_bunbaegi_buffer[22] = (uint8_t)(SEN66_pm10p0[6]>>8); + Tx_bunbaegi_buffer[23] = (uint8_t)(SEN66_pm10p0[6]); + Tx_bunbaegi_buffer[24] = (uint8_t)(SEN66_humidity_value[6]>>8); + Tx_bunbaegi_buffer[25] = (uint8_t)(SEN66_humidity_value[6]); + Tx_bunbaegi_buffer[26] = (uint8_t)(SEN66_temperature_value[6]>>8); + Tx_bunbaegi_buffer[27] = (uint8_t)(SEN66_temperature_value[6]); + Tx_bunbaegi_buffer[28] = (uint8_t)(SEN66_CO2_value[6]>>8); + Tx_bunbaegi_buffer[29] = (uint8_t)(SEN66_CO2_value[6]); + Tx_bunbaegi_buffer[30] = (uint8_t)(SEN66_VOC_value[6]>>8);; + Tx_bunbaegi_buffer[31] = (uint8_t)(SEN66_VOC_value[6]); + + Tx_bunbaegi_buffer[32] = 0; + } + else //normal + { + id_2 = 1; //living room + + Tx_bunbaegi_buffer[4] = 0x00; //VSP_MODE + Tx_bunbaegi_buffer[5] = Diffuser_Power[id_2]; //Power Mode + Tx_bunbaegi_buffer[6] = Diffuser_Run_Mode[id_2]; //Run Mode + Tx_bunbaegi_buffer[7] = Diffuser_Fan_Speed[id_2]; //Fan Speed + + if(Command_request_type & TYPE_POWER)Tx_bunbaegi_buffer[5] |= 0x80; + if(Command_request_type & TYPE_MODE)Tx_bunbaegi_buffer[6] |= 0x80; + if(Command_request_type & TYPE_FAN_SPEED)Tx_bunbaegi_buffer[7] |= 0x80; + Command_request_type = 0; + + Tx_bunbaegi_buffer[8] = 0; //reservation time + Tx_bunbaegi_buffer[9] = UV_OnOff; //Heater/UV + Tx_bunbaegi_buffer[10] = 0; //Filter Reset + Tx_bunbaegi_buffer[11] = 0; //RPM Start + Tx_bunbaegi_buffer[12] = 0; //RPM Stop + + Tx_bunbaegi_buffer[13] = (uint8_t)(SEN66_pm2p5[id_2]>>8); + Tx_bunbaegi_buffer[14] = (uint8_t)(SEN66_pm2p5[id_2]); + Tx_bunbaegi_buffer[15] = (uint8_t)(SEN66_pm10p0[id_2]>>8); + Tx_bunbaegi_buffer[16] = (uint8_t)(SEN66_pm10p0[id_2]); + Tx_bunbaegi_buffer[17] = (uint8_t)(SEN66_humidity_value[id_2]>>8); + Tx_bunbaegi_buffer[18] = (uint8_t)(SEN66_humidity_value[id_2]); + Tx_bunbaegi_buffer[19] = (uint8_t)(SEN66_temperature_value[id_2]>>8); + Tx_bunbaegi_buffer[20] = (uint8_t)(SEN66_temperature_value[id_2]); + Tx_bunbaegi_buffer[21] = (uint8_t)(SEN66_CO2_value[id_2]>>8); + Tx_bunbaegi_buffer[22] = (uint8_t)(SEN66_CO2_value[id_2]); + + Tx_bunbaegi_buffer[23] = 0; + Tx_bunbaegi_buffer[24] = 0;//(uint8_t)(Energy_Consumption>>8); + Tx_bunbaegi_buffer[25] = 0;//(uint8_t)(Energy_Consumption); + Tx_bunbaegi_buffer[26] = 0; + + Tx_bunbaegi_buffer[27] = (uint8_t)(SEN66_VOC_value[id_2]>>8);; + Tx_bunbaegi_buffer[28] = (uint8_t)(SEN66_VOC_value[id_2]); + + Tx_bunbaegi_buffer[29] = (uint8_t)(Filter_timer_change>>8); + Tx_bunbaegi_buffer[30] = (uint8_t)(Filter_timer_change); + + Tx_bunbaegi_buffer[31] = (uint8_t)(Soja_timer_change>>8); + Tx_bunbaegi_buffer[32] = (uint8_t)(Soja_timer_change); + } + } + else + { + Tx_bunbaegi_buffer[4] = 0x00; //VSP_MODE + Tx_bunbaegi_buffer[5] = Diffuser_Power[id_2]; //Power Mode + Tx_bunbaegi_buffer[6] = Diffuser_Run_Mode[id_2]; //Run Mode + Tx_bunbaegi_buffer[7] = Diffuser_Fan_Speed[id_2]; //Fan Speed + + + Tx_bunbaegi_buffer[8] = 0; //reservation time + Tx_bunbaegi_buffer[9] = 0; //Heater/UV + Tx_bunbaegi_buffer[10] = 0; //Filter Reset + Tx_bunbaegi_buffer[11] = 0; //RPM Start + Tx_bunbaegi_buffer[12] = 0; //RPM Stop + + Tx_bunbaegi_buffer[13] = (uint8_t)(SEN66_pm2p5[id_2]>>8); + Tx_bunbaegi_buffer[14] = (uint8_t)(SEN66_pm2p5[id_2]); + Tx_bunbaegi_buffer[15] = (uint8_t)(SEN66_pm10p0[id_2]>>8); + Tx_bunbaegi_buffer[16] = (uint8_t)(SEN66_pm10p0[id_2]); + Tx_bunbaegi_buffer[17] = (uint8_t)(SEN66_humidity_value[id_2]>>8); + Tx_bunbaegi_buffer[18] = (uint8_t)(SEN66_humidity_value[id_2]); + Tx_bunbaegi_buffer[19] = (uint8_t)(SEN66_temperature_value[id_2]>>8); + Tx_bunbaegi_buffer[20] = (uint8_t)(SEN66_temperature_value[id_2]); + Tx_bunbaegi_buffer[21] = (uint8_t)(SEN66_CO2_value[id_2]>>8); + Tx_bunbaegi_buffer[22] = (uint8_t)(SEN66_CO2_value[id_2]); + + Tx_bunbaegi_buffer[23] = 0; + Tx_bunbaegi_buffer[24] = 0; + Tx_bunbaegi_buffer[25] = 0; + Tx_bunbaegi_buffer[26] = 0; + + Tx_bunbaegi_buffer[27] = (uint8_t)(SEN66_VOC_value[id_2]>>8);; + Tx_bunbaegi_buffer[28] = (uint8_t)(SEN66_VOC_value[id_2]); + + Tx_bunbaegi_buffer[29] = (uint8_t)(Filter_timer_change>>8); + Tx_bunbaegi_buffer[30] = (uint8_t)(Filter_timer_change); + + Tx_bunbaegi_buffer[31] = (uint8_t)(Soja_timer_change>>8); + Tx_bunbaegi_buffer[32] = (uint8_t)(Soja_timer_change); + } + + Tx_bunbaegi_buffer[33] = (uint8_t)(Err_Code>>8); //Error Code + Tx_bunbaegi_buffer[34] = (uint8_t)(Err_Code&0x00FF); //Error Code + + Tx_bunbaegi_buffer[35] = 0; + Tx_bunbaegi_buffer[36] = 0; + + icrc = CRC16(Tx_bunbaegi_buffer, 37); + Tx_bunbaegi_buffer[37] = (uint8_t)(icrc>>8); //CRC16 + Tx_bunbaegi_buffer[38] = (uint8_t)(icrc & 0x00FF); //CRC16 + + BUNBAGI_485_DIR = 1; + SCUART_Write(SC1, Tx_bunbaegi_buffer, 39); + while ( !(SC1->TRSR & SC_TRSR_TX_EMPTY_F_Msk) ); + delay_us(200); + BUNBAGI_485_DIR = 0; + } + } + else //////BunBaeGi Polling + { + Tx_bunbaegi_buffer[4] = 0x00; //VSP_MODE + Tx_bunbaegi_buffer[5] = Diffuser_Power[id_2]; //Power Mode + Tx_bunbaegi_buffer[6] = Diffuser_Run_Mode[id_2]; //Run Mode + Tx_bunbaegi_buffer[7] = Diffuser_Fan_Speed[id_2]; //Fan Speed + + if(Diffuser_Run_Mode[1] == 0x02) // auto mode + { + Tx_bunbaegi_buffer[8] = Light_Bright[id_2]; //LED + + Tx_bunbaegi_buffer[9] = Diffuser_Air_quality[id_2]; //Air Quality + Tx_bunbaegi_buffer[10] = Diffuser_Dmp_Ang_SA[id_2]; //Damper Angle - SA + Tx_bunbaegi_buffer[11] = Diffuser_Dmp_Ang_RA[id_2]; //Damper Angle - EA + Tx_bunbaegi_buffer[12] = (uint8_t)(urpm1>>8); //SA RPM + Tx_bunbaegi_buffer[13] = (uint8_t)(urpm1); //SA RPM + Tx_bunbaegi_buffer[14] = (uint8_t)(urpm2>>8); //EA RPM + Tx_bunbaegi_buffer[15] = (uint8_t)(urpm2); //EA RPM + Tx_bunbaegi_buffer[16] = 0; //SA Reset + Tx_bunbaegi_buffer[17] = 0; //EA Reset + Tx_bunbaegi_buffer[18] = 0; //Reserve Hour + Tx_bunbaegi_buffer[19] = 0; //Blank + Tx_bunbaegi_buffer[20] = 0; //Blank + Tx_bunbaegi_buffer[21] = 0; //Blank + Tx_bunbaegi_buffer[22] = 0; //Blank + Tx_bunbaegi_buffer[23] = 0; //Version + Tx_bunbaegi_buffer[24] = 0; //Version + Tx_bunbaegi_buffer[25] = (uint8_t)(Err_Code>>8); //Error Code + Tx_bunbaegi_buffer[26] = (uint8_t)(Err_Code&0x00FF); //Error Code + } + else + { + Tx_bunbaegi_buffer[8] = Light_Bright[id_2]; //LED + + Tx_bunbaegi_buffer[9] = Diffuser_Air_quality[id_2]; //Air Quality + Tx_bunbaegi_buffer[10] = Diffuser_Dmp_Ang_SA[id_2]; //Damper Angle - SA + Tx_bunbaegi_buffer[11] = Diffuser_Dmp_Ang_RA[id_2]; //Damper Angle - EA + Tx_bunbaegi_buffer[12] = 0; //SA RPM + Tx_bunbaegi_buffer[13] = 0; //SA RPM + Tx_bunbaegi_buffer[14] = 0; //EA RPM + Tx_bunbaegi_buffer[15] = 0; //EA RPM + Tx_bunbaegi_buffer[16] = 0; //SA Reset + Tx_bunbaegi_buffer[17] = 0; //EA Reset + Tx_bunbaegi_buffer[18] = 0; //Reserve Hour + Tx_bunbaegi_buffer[19] = 0; //Blank + Tx_bunbaegi_buffer[20] = 0; //Blank + Tx_bunbaegi_buffer[21] = 0; //Blank + Tx_bunbaegi_buffer[22] = 0; //Blank + Tx_bunbaegi_buffer[23] = 0; //Version + Tx_bunbaegi_buffer[24] = 0; //Version + Tx_bunbaegi_buffer[25] = (uint8_t)(Err_Code>>8); //Error Code + Tx_bunbaegi_buffer[26] = (uint8_t)(Err_Code&0x00FF); //Error Code + } + icrc = CRC16(Tx_bunbaegi_buffer, 27); + Tx_bunbaegi_buffer[27] = (uint8_t)(icrc>>8); //CRC16 + Tx_bunbaegi_buffer[28] = (uint8_t)(icrc & 0x00FF); //CRC16 + + BUNBAGI_485_DIR = 1; + SCUART_Write(SC1, Tx_bunbaegi_buffer, 29); + while ( !(SC1->TRSR & SC_TRSR_TX_EMPTY_F_Msk) ); + delay_us(200); + BUNBAGI_485_DIR = 0; + } + + if(tx_sel == 1) // TX -> SA + { + if(sa_sel++ >= 4) + { + tx_sel = 2; + sa_sel = 1; + } + } + else if(tx_sel == 2) + { + if(ea_sel++ >= 4) + { + ea_sel = 1; + tx_sel = 3; + } + } + else + { + sa_sel = 1; + ea_sel = 1; + tx_sel = 1; + } + +} + +void Diffuser_parsing(void) +{ + uint8_t id = 0; + + if(Rx_bunbaegi_buffer[2]==0x02) //EA + { + id = Rx_bunbaegi_buffer[3]; + + + SEN66_pm10p0[id] = ((uint16_t)Rx_bunbaegi_buffer[12]<<8 | (uint16_t)Rx_bunbaegi_buffer[13]); + SEN66_pm4p0[id] = ((uint16_t)Rx_bunbaegi_buffer[14]<<8 | (uint16_t)Rx_bunbaegi_buffer[15]); + SEN66_pm2p5[id] = ((uint16_t)Rx_bunbaegi_buffer[16]<<8 | (uint16_t)Rx_bunbaegi_buffer[17]); + SEN66_pm1p0[id] = ((uint16_t)Rx_bunbaegi_buffer[18]<<8 | (uint16_t)Rx_bunbaegi_buffer[19]); + SEN66_humidity_value[id] = ((uint16_t)Rx_bunbaegi_buffer[20]<<8 | (uint16_t)Rx_bunbaegi_buffer[21]); + SEN66_temperature_value[id] = ((uint16_t)Rx_bunbaegi_buffer[22]<<8 | (uint16_t)Rx_bunbaegi_buffer[23]); + SEN66_VOC_value[id] = ((uint16_t)Rx_bunbaegi_buffer[24]<<8 | (uint16_t)Rx_bunbaegi_buffer[25]); + SEN66_NOx_value[id] = ((uint16_t)Rx_bunbaegi_buffer[26]<<8 | (uint16_t)Rx_bunbaegi_buffer[27]); + SEN66_CO2_value[id] = ((uint16_t)Rx_bunbaegi_buffer[28]<<8 | (uint16_t)Rx_bunbaegi_buffer[29]); + /* + bunbaegi_Err_Code = ((uint16_t)Rx_bunbaegi_buffer[33]<<8 | (uint16_t)Rx_bunbaegi_buffer[34]); + + if(bunbaegi_Err_Code == 0x0100) + { + if(id == 0) + { + Err_Code |= ERROR_SENSOR_MODULE_LIVING; + } + else if(id == 1) + { + Err_Code |= ERROR_SENSOR_MODULE_ROOM1; + } + else if(id == 2) + { + Err_Code |= ERROR_SENSOR_MODULE_ROOM2; + } + else if(id == 3) + { + Err_Code |= ERROR_SENSOR_MODULE_ROOM3; + } + } + else + { + if(id == 0) + { + Err_Code &= ~ERROR_SENSOR_MODULE_LIVING; + } + else if(id == 1) + { + Err_Code &= ~ERROR_SENSOR_MODULE_ROOM1; + } + else if(id == 2) + { + Err_Code &= ~ERROR_SENSOR_MODULE_ROOM2; + } + else if(id == 3) + { + Err_Code &= ~ERROR_SENSOR_MODULE_ROOM3; + } + } + */ + } + + memset(Rx_bunbaegi_buffer, 0, sizeof(Rx_bunbaegi_buffer)); +} + + +void EachRoomCon_parsing(void) +{ + uint8_t id = 0; + + id = Rx_bunbaegi_buffer[3]; + Diffuser_VSP_Mode = Rx_bunbaegi_buffer[4]; + + if(Diffuser_VSP_Mode == 0x10) //setting + { + switch(Rx_bunbaegi_buffer[5]) // vsp_select + { + case 1: + s_FAN1_VEN_1_DAN = Rx_bunbaegi_buffer[6]; + s_FAN2_VEN_1_DAN = Rx_bunbaegi_buffer[7]; + s_FAN1_VEN_2_DAN = Rx_bunbaegi_buffer[8]; + s_FAN2_VEN_2_DAN = Rx_bunbaegi_buffer[9]; + s_FAN1_VEN_3_DAN = Rx_bunbaegi_buffer[10]; + s_FAN2_VEN_3_DAN = Rx_bunbaegi_buffer[11]; + + Test_RPM_Vent_Reference[1] = ((uint16_t)Rx_bunbaegi_buffer[18]<<8) + ((uint16_t)Rx_bunbaegi_buffer[19]); + Test_RPM_Vent_Delta[1] = ((uint16_t)Rx_bunbaegi_buffer[20]<<8) + ((uint16_t)Rx_bunbaegi_buffer[21]); + Test_RPM_Vent_Reference[2] = ((uint16_t)Rx_bunbaegi_buffer[22]<<8) + ((uint16_t)Rx_bunbaegi_buffer[23]); + Test_RPM_Vent_Delta[2] = ((uint16_t)Rx_bunbaegi_buffer[24]<<8) + ((uint16_t)Rx_bunbaegi_buffer[25]); + break; + case 2: + s_FAN1_AIR_1_DAN = Rx_bunbaegi_buffer[6]; + s_FAN2_AIR_1_DAN = Rx_bunbaegi_buffer[7]; + s_FAN1_AIR_2_DAN = Rx_bunbaegi_buffer[8]; + s_FAN2_AIR_2_DAN = Rx_bunbaegi_buffer[9]; + s_FAN1_AIR_3_DAN = Rx_bunbaegi_buffer[10]; + s_FAN2_AIR_3_DAN = Rx_bunbaegi_buffer[11]; + + Test_RPM_Air_Reference[1] = ((uint16_t)Rx_bunbaegi_buffer[18]<<8) + ((uint16_t)Rx_bunbaegi_buffer[19]); + Test_RPM_Air_Delta[1] = ((uint16_t)Rx_bunbaegi_buffer[20]<<8) + ((uint16_t)Rx_bunbaegi_buffer[21]); + Test_RPM_Air_Reference[2] = ((uint16_t)Rx_bunbaegi_buffer[22]<<8) + ((uint16_t)Rx_bunbaegi_buffer[23]); + Test_RPM_Air_Delta[2] = ((uint16_t)Rx_bunbaegi_buffer[24]<<8) + ((uint16_t)Rx_bunbaegi_buffer[25]); + break; + case 3: + s_FAN1_BYPASS_1_DAN = Rx_bunbaegi_buffer[6]; + s_FAN2_BYPASS_1_DAN = Rx_bunbaegi_buffer[7]; + s_FAN1_BYPASS_2_DAN = Rx_bunbaegi_buffer[8]; + s_FAN2_BYPASS_2_DAN = Rx_bunbaegi_buffer[9]; + s_FAN1_BYPASS_3_DAN = Rx_bunbaegi_buffer[10]; + s_FAN2_BYPASS_3_DAN = Rx_bunbaegi_buffer[11]; + + if(Rx_bunbaegi_buffer[36] == 1)EEP_Save_Flag = 1; + break; + default: + break; + } + + Roomcon_Num = Rx_bunbaegi_buffer[30]; + Diffuser_Num = Rx_bunbaegi_buffer[31]; + } + else if(Diffuser_VSP_Mode == 0) //normal + { + if(id == 5) // living room + { +// Com_Err_Flag = 0; +// Roomcon_Com_Count = 0; + + if(Rx_bunbaegi_buffer[5] & 0x80) + { + Diffuser_Power[1] = Rx_bunbaegi_buffer[5] & 0x7f; + Diffuser_Power[2] = Rx_bunbaegi_buffer[5] & 0x7f; + Diffuser_Power[3] = Rx_bunbaegi_buffer[5] & 0x7f; + Diffuser_Power[4] = Rx_bunbaegi_buffer[5] & 0x7f; + Diffuser_Power[5] = Rx_bunbaegi_buffer[5] & 0x7f; + Diffuser_Power[6] = Rx_bunbaegi_buffer[5] & 0x7f; + + Power_On = Rx_bunbaegi_buffer[5] & 0x7f; + } + if(Rx_bunbaegi_buffer[6] & 0x80) + { + Diffuser_Run_Mode[1] = Rx_bunbaegi_buffer[6] & 0x7f; + Diffuser_Run_Mode[2] = Rx_bunbaegi_buffer[6] & 0x7f; + Diffuser_Run_Mode[3] = Rx_bunbaegi_buffer[6] & 0x7f; + Diffuser_Run_Mode[4] = Rx_bunbaegi_buffer[6] & 0x7f; + Diffuser_Run_Mode[5] = Rx_bunbaegi_buffer[6] & 0x7f; + Diffuser_Run_Mode[6] = Rx_bunbaegi_buffer[6] & 0x7f; + + if(Diffuser_Run_Mode[1] == 0x01) Run_Mode = MODE_VENTILATION; + else if(Diffuser_Run_Mode[1] == 0x02) Run_Mode = MODE_AUTO; + else if(Diffuser_Run_Mode[1] == 0x04) Run_Mode = MODE_BYPASS; + else if(Diffuser_Run_Mode[1] == 0x08) Run_Mode = MODE_AIRCLEAN; + else Run_Mode = MODE_VENTILATION; + } + if(Rx_bunbaegi_buffer[7] & 0x80) + { + Diffuser_Fan_Speed[1] = Rx_bunbaegi_buffer[7] & 0x7f; + Diffuser_Fan_Speed[2] = Rx_bunbaegi_buffer[7] & 0x7f; + Diffuser_Fan_Speed[3] = Rx_bunbaegi_buffer[7] & 0x7f; + Diffuser_Fan_Speed[4] = Rx_bunbaegi_buffer[7] & 0x7f; + Diffuser_Fan_Speed[5] = Rx_bunbaegi_buffer[7] & 0x7f; + Diffuser_Fan_Speed[6] = Rx_bunbaegi_buffer[7] & 0x7f; + + Fan_Mode = Rx_bunbaegi_buffer[7] & 0x7f; + } + + if(Rx_bunbaegi_buffer[8] & 0x80) + { + Set_Reserve_timer_sec = (uint32_t)(Rx_bunbaegi_buffer[7] & 0x7f)*3600; + } + + if(Rx_bunbaegi_buffer[9]&0x80) + { + Heater_OnOff = Rx_bunbaegi_buffer[9]&0x01; + + //UV_OnOff = (Rx_bunbaegi_buffer[9]>>4)&0x01; + } + + if(Rx_bunbaegi_buffer[10] == 0x01)Filter_Reset_Flag |= 1; + +// if(Rx_bunbaegi_buffer[23] & 0x80) +// { + if(Rx_bunbaegi_buffer[23] & 0x01){Diffuser_Power[2] = 1;}else{Diffuser_Power[2] = 0;} + if(Rx_bunbaegi_buffer[23] & 0x02){Diffuser_Power[3] = 1;}else{Diffuser_Power[3] = 0;} + if(Rx_bunbaegi_buffer[23] & 0x04){Diffuser_Power[4] = 1;}else{Diffuser_Power[4] = 0;} + if(Rx_bunbaegi_buffer[23] & 0x08){Diffuser_Power[5] = 1;}else{Diffuser_Power[5] = 0;} +// } + + + } + else if(id == 0) //wrong id + { + } + else // id 2,3,4,5 room 1 ~3 + { + if(Rx_bunbaegi_buffer[5] & 0x80) + { + Diffuser_Power[id] = Rx_bunbaegi_buffer[5] & 0x7f; + } + if(Rx_bunbaegi_buffer[6] & 0x80) + { + Diffuser_Run_Mode[id] = Rx_bunbaegi_buffer[6] & 0x7f; + } + if(Rx_bunbaegi_buffer[7] & 0x80) + { + Diffuser_Fan_Speed[id] = Rx_bunbaegi_buffer[7] & 0x7f; + } + } + } + else + { + ; + } + +} + +void SC1_IRQHandler(void) +{ + uint8_t data; + + data = SCUART_READ(SC1); + + rx_bunbaegi_check(data); + Rx_roomcon_TimeOut = 50; + + return; +} + +void InCom_process(void) +{ + if(Rx_bunbaegi_complete == 1) + { + Rx_bunbaegi_complete = 0; + + if(Packet_Type == 0x01)//Diffuser + { + Diffuser_parsing(); + //Display_Com_Err_Count = 0; + //Err_Code &= ~ERROR_COM_DISPLAY; + } + else if(Packet_Type == 0x02)//RoomCon + { + EachRoomCon_parsing(); + //Sensor_Com_Err_Count = 0; + //Err_Code &= ~ERROR_COM_SENSOR; + } + } + else if(InCom_polling_timer == 0) + { + InCom_polling_timer = 100; + + Bunbaegi_Polling(); + /*if(Sensor_Com_Err_Count++ >= 20) + { + Sensor_Com_Err_Count = 20; + Err_Code |= ERROR_COM_SENSOR; + }*/ + + } +} + +uint8_t Debug_TxBuff[250]; +uint8_t Debug_Tx_Cycle = 0; + + + + + +uint16_t m_CO2_Level_1 = 600; +uint16_t m_CO2_Level_2 = 700; +uint16_t m_CO2_Level_3 = 800; +uint16_t m_CO2_Level_4 = 900; + +uint16_t m_VOC_Level_1 = 250; +uint16_t m_VOC_Level_2 = 300; +uint16_t m_VOC_Level_3 = 350; +uint16_t m_VOC_Level_4 = 400; + +uint16_t m_PM2_5_Level_1 = 15; +uint16_t m_PM2_5_Level_2 = 30; +uint16_t m_PM2_5_Level_3 = 50; +uint16_t m_PM2_5_Level_4 = 70; + +uint8_t Ext_Run_Mode = 0; +uint8_t Ext_Select_Room = 0, Pre_Ext_Select_Room = 0; + +uint8_t Tx_485_buff[100]; +uint32_t Damper_Status_Display = 0; +uint8_t Force_Damper_Mode = 0; + +uint8_t Force_Damper_run = 0; +extern uint16_t Target_Step_Count[7]; diff --git a/program/User/My_define.h b/program/User/My_define.h new file mode 100644 index 0000000..6c2ca9e --- /dev/null +++ b/program/User/My_define.h @@ -0,0 +1,495 @@ + + + + +void delay_ms(uint32_t ms); +void delay_us(uint32_t us); +void PowerDownFunction(void); +void GPIO_Init(void); +void PWM_Init(void); +void Timer0_Init(void); +void Timer1_Init(void); +void SYS_Init(void); +void UART0_Init(void); +void UART1_Init(void); +void SC0_Init(); +void SC1_Init(); +void ADC_Init(void); + +void com_home_network_process(void); +void com_display_process(void); +void com_roomcon_process(void); +void roomcon_parsing(void); +void display_parsing(void); +void tx_home_network_data(void); +void RJ_Com_Err_Check(void); + + +uint16_t CRC16(uint8_t *puchMsg, uint16_t usDataLen); /* My_bunbaeggi.c 정의 (My_Homenet.c 공용) */ +void com_bunbaegi_process(void); +void bunbaegi_parsing(void); +void InCom_process(void); + + +void BLDC1_Duty_Change(uint32_t BLDC1_duty); // 0 ~ 10000 +void BLDC2_Duty_Change(uint32_t BLDC2_duty); // 0 ~ 10000 + + +void init_process(void); +void ADC_Sensing(void); +void EEP_Save_process(void); +void Heater_process(void); +void Reservation_process(void); +void Filter_process(void); +uint8_t Filter_Reset_Process(void); +void Exception_mode_process(void); + +uint16_t Aeverage_calculator(uint16_t val, uint16_t * array_val); +void Reserve_Time_Update(uint8_t rtime); +void Power_off_process(uint8_t set); + +void Step_process(void); +uint8_t Step_motor_init(void); +void Fan_Error_Check(void); +void Fan_Speed_process(void); // 100ms +void Bldc_check(void); + +void PWM_out_process(void); +void Step_M1_Stop(); +void Step_M2_Stop(); +void Step_M3_Stop(); +void Step_M4_Stop(); +void Step_M5_Stop(); +void Step_M6_Stop(); +void Fan_Speed_Setting(uint8_t r_mode, uint8_t f_speed); + +void Pre_Mode_Control(void); + +void UV_process(void); + +uint8_t Air_Quality_process(void); +void Filter_RPM_Check(void); +void Filter_Rpm_Auto_Cal_Process(void); + +extern volatile uint8_t Rx_display_complete, Rx_homenet_complete, Rx_roomcon_complete, Rx_debug_complete; +extern volatile uint8_t Tx_display_flag, Tx_homenet_flag, Tx_roomcon_flag, Tx_debug_flag; + +extern uint8_t Tx_homenet_buffer[60],Tx_display_buffer[25],Tx_roomcon232_buffer[25],Tx_debug_buffer[60]; +extern uint8_t Rx_homenet_buffer[60],Rx_display_buffer[25],Rx_roomcon232_buffer[25],Rx_debug_buffer[20]; + +extern uint8_t Uart_Rx0,Uart_Rx1,Uart_Rx2, Uart_Rx3 ; +extern uint8_t Rx_homenet_TimeOut, Rx_roomcon_TimeOut, Rx_debug_TimeOut; + +extern uint8_t Test_Fan1_Speed, Test_Fan2_Speed; +extern uint8_t Test_Fan1_Ven_1_dan, Test_Fan1_Ven_2_dan, Test_Fan1_Ven_3_dan, Test_Fan1_Ven_4_dan, \ + Test_Fan1_Air_1_dan, Test_Fan1_Air_2_dan, Test_Fan1_Air_3_dan, Test_Fan1_Air_4_dan,\ + Test_Fan1_Bypass_1_dan, Test_Fan1_Bypass_2_dan, Test_Fan1_Bypass_3_dan, Test_Fan1_Bypass_4_dan; +extern uint8_t Test_Fan2_Ven_1_dan, Test_Fan2_Ven_2_dan, Test_Fan2_Ven_3_dan, Test_Fan2_Ven_4_dan,\ + Test_Fan2_Air_1_dan, Test_Fan2_Air_2_dan, Test_Fan2_Air_3_dan , Test_Fan2_Air_4_dan,\ + Test_Fan2_Bypass_1_dan, Test_Fan2_Bypass_2_dan, Test_Fan2_Bypass_3_dan, Test_Fan2_Bypass_4_dan; + +extern volatile uint16_t Filter_timer_clean; +extern volatile uint16_t Filter_timer_change; +extern volatile uint16_t Soja_timer_change; + +extern volatile uint8_t Run_Mode, Auto_Mode, Fan_Mode; +extern uint8_t Power_On; + +extern uint16_t SEN66_pm1p0[7], SEN66_pm2p5[7], SEN66_pm4p0[7], SEN66_pm10p0[7]; +extern int16_t SEN66_humidity_value[7]; +extern int16_t SEN66_temperature_value[7]; +extern int16_t SEN66_VOC_value[7]; +extern int16_t SEN66_NOx_value[7]; +extern uint16_t SEN66_CO2_value[7]; + +extern uint8_t Diffuser_VSP_Mode; +extern uint8_t Diffuser_Power[7]; +extern uint8_t Diffuser_Run_Mode[7]; +extern uint8_t Diffuser_Fan_Speed[7]; +extern uint8_t Diffuser_Dmp_Ang_SA[7],Memory_Diffuser_Dmp_Ang_SA[7]; //Damper Angle +extern uint8_t Diffuser_Dmp_Ang_RA[7],Memory_Diffuser_Dmp_Ang_RA[7]; //Damper Angle +extern uint8_t Diffuser_Air_quality[7],Memory_Diffuser_Air_quality[7]; +extern uint8_t Diffuser_Damper_Manual[7]; /* 대시보드 수동 댐퍼 오버라이드(각실 1~4) */ +extern uint8_t Diffuser_Led_Manual[7]; /* 대시보드 수동 LED 오버라이드(각실 1~4) */ +extern uint16_t Reserve_Remain_Sec; /* (꺼짐)예약 잔여초 (0=예약없음) */ + + +extern volatile uint8_t Vsp_Mode[5]; +extern volatile uint8_t Pre_Vsp_Mode; + +extern uint16_t Test_RPM_Vent_Reference[5]; +extern uint16_t Test_RPM_Vent_Delta[5]; +extern uint16_t Test_RPM_Air_Reference[5]; +extern uint16_t Test_RPM_Air_Delta[5]; + +extern uint16_t RPM_Vent_Reference[5]; +extern uint16_t RPM_Vent_Delta[5]; +extern uint16_t RPM_Air_Reference[5]; +extern uint16_t RPM_Air_Delta[5]; + +#define ST_LED PA10 + +#define TEMP1_ADC PA0 +#define TEMP2_ADC PA1 + +#define VOLUM1_ADC PA2 +#define VOLUM2_ADC PA3 + +#define CURRENT_VOL PA4 + +#define P_SW PA11 +#define BLDC_PW PB7 +#define UV_PW PA5 + +#define P_UV PF2 + +#define HOOD_485_TX PB1 +#define HOOD_485_RX PB0 +#define HOOD_485_DIR PB2 + +#define HOMENET_485_TX PB5 +#define HOMENET_485_RX PB4 +#define HOMENET_485_DIR PB6 + +#define ROOMCON_TX PA8 +#define ROOMCON_RX PA9 + +#define BUNBAGI_485_TX2 PC0 +#define BUNBAGI_485_RX2 PC1 +#define BUNBAGI_485_DIR PC7 + +#define BLDC_SA_PWM PB11 +#define BLDC_SA_FG_IN PE5 +#define BLDC_EA_PWM PA12 +#define BLDC_EA_FG_IN PA13 + + +#define REG_STEP_M1_A PB12 +#define REG_STEP_M1_B PB13 +#define REG_STEP_M1_NA PB14 +#define REG_STEP_M1_NB PB8 + +#define REG_STEP_M2_A PB15 +#define REG_STEP_M2_B PC14 +#define REG_STEP_M2_NA PC15 +#define REG_STEP_M2_NB PC6 + +#define REG_STEP_M3_A PA6 +#define REG_STEP_M3_B PA14 +#define REG_STEP_M3_NA PA15 +#define REG_STEP_M3_NB PC8 + +#define REG_STEP_M4_A PC9 +#define REG_STEP_M4_B PC10 +#define REG_STEP_M4_NA PC11 +#define REG_STEP_M4_NB PB9 + +#define REG_STEP_M5_A PB10 +#define REG_STEP_M5_B PC2 +#define REG_STEP_M5_NA PC3 +#define REG_STEP_M5_NB PD15 + +#define REG_STEP_M6_A PD14 +#define REG_STEP_M6_B PD7 +#define REG_STEP_M6_NA PD6 +#define REG_STEP_M6_NB PB3 + + + +#define DAMPER_EA 1 +#define DAMPER_OA 2 +#define DAMPER_BYPASS 3 +#define DAMPER_SA 4 +#define DAMPER_RA 5 // 3???í¼ +#define DAMPER_AIR 6 + +//--------------------------------------------------------------- + + + +#define ERROR_FILTER_CLEAN 0x01 +#define ERROR_FILTER_CHANGE 0x02 +#define ERROR_SOJA_CHANGE 0x04 +#define ERROR_TEMP_SENSOR 0x08 + +#define ERROR_SA_FAN 0x80 +#define ERROR_EA_FAN 0x20 + +#define ERROR_PROTECT 0x10 //2020.9.2 +#define ERROR_SOMETIME 0x40 //2020.9.10 + + + +#define RX_DATA_MODE_NORMAL 0 +#define RX_DATA_MODE_EVENT 0x01 +#define RX_DATA_MODE_RESTART1 0x02 +#define RX_DATA_MODE_RESTART2 0x12 +#define RX_DATA_MODE_VSP 0x03 +#define RX_DATA_MODE_EXIT 0x04 +#define RX_DATA_FILTER_INFO 0x05 //(룸콘 -> 환기장치) +#define RX_DATA_SENSOR_INFO 0x06 //(환기장치 -> 룸콘) +#define RX_DATA_CONTROLL 0x07 //(환기장치 -> 룸콘) +#define RX_DATA_HOOD_INFO 0x0A //(main -> room) // // add 2022.1.25 +#define RX_DATA_CONTROLL_INFO 0x80 //(룸콘 -> 환기장치) +#define RX_DATA_RPM_INFO 0x81 //(환기장치 -> 룸콘) // 2021.5.31 +#define RX_DATA_ERROR_CLEAR 0x22 //2021.5.31 + +//----------------------------------------------------------------- +#define SPEC_VERSION1_INFO 0x01 +#define SPEC_VERSION2_INFO 0x00 +#define SPEC_DEVICE_TYPE_INFO 0x04//0x10 // C1 = 0x01, C2 = 0x02, E = 0x03, EBSN = 0x04, EBN = 0x05, EF = 0x06, A = 0x07, EF2=0x08, EGI=0x09, C4=0x10 +#define SPEC_CMH_INFO 0x03 // 50=1, 70=2, 100=3, 120=4, 150=5, 200=6, 250=7 + +// 1 : 일반 히터O - 환기/자동 +// 2 : 바이패스 히터O - 환기/자동/바이패스 +// 3 : 공청 히터O - 환기/자동/공청/바이패스 +// 4 : 일반 히터X - 환기/자동 +// 5 : 바이패스 히터X - 환기/자동/바이패스 +// 6 : 공청 히터X - 환기/자동/공청/바이패스 +// 0x10 | 대림사양 +// 0x20 | UV 사용 +#define SPEC_MODE_INFO 0x16 + +// 연동없음 = 0, 삼성SDS=1, 씨브이넷=2, 아이콘트롤=3, 코맥스=4, 코콤=5, 현대통신=6, | 세익=0x10, 신동테크=0x20, 한국하니웰=0x30, 한성시스코=0x40 +#define SPEC_HOMENET_INFO 0x00 // +#define SPEC_HOOD_INFO 0x01 // + + + + +////////////////////////////////////////////////////////////// + +#if(((SPEC_MODE_INFO&0x0F) ==0x03)||((SPEC_MODE_INFO&0x0F) ==0x06)) + +// airclean mode O +#define MODE_VENTILATION 0 +#define MODE_AUTO 1 +#define MODE_AIRCLEAN 2 +#define MODE_BYPASS 3 +#define MODE_FAN_TEST 4 + + +#else + +// airclean mode X +#define MODE_VENTILATION 0 +#define MODE_AUTO 1 +#define MODE_BYPASS 2 +#define MODE_AIRCLEAN 3 // not used +#define MODE_FAN_TEST 4 + + +#endif + +//--------------------------------------------------------------- + +#define MAIN_FW_VERSION 0x01 + + +//--------------------------------------------------------------------- + +#define EEP_ADDR_START 0x01 +#define EEP_ADDR_MODBUS_ID 0x05 + + +#define EEP_FAN1_VEN_1_DAN 10 +#define EEP_FAN1_VEN_2_DAN 11 +#define EEP_FAN1_VEN_3_DAN 12 +#define EEP_FAN1_VEN_4_DAN 13 +#define EEP_FAN1_AIR_1_DAN 14 +#define EEP_FAN1_AIR_2_DAN 15 +#define EEP_FAN1_AIR_3_DAN 16 +#define EEP_FAN1_AIR_4_DAN 17 +#define EEP_FAN1_BYPASS_1_DAN 18 +#define EEP_FAN1_BYPASS_2_DAN 19 +#define EEP_FAN1_BYPASS_3_DAN 20 +#define EEP_FAN1_BYPASS_4_DAN 21 + +#define EEP_FAN2_VEN_1_DAN 22 +#define EEP_FAN2_VEN_2_DAN 23 +#define EEP_FAN2_VEN_3_DAN 24 +#define EEP_FAN2_VEN_4_DAN 25 +#define EEP_FAN2_AIR_1_DAN 26 +#define EEP_FAN2_AIR_2_DAN 27 +#define EEP_FAN2_AIR_3_DAN 28 +#define EEP_FAN2_AIR_4_DAN 29 +#define EEP_FAN2_BYPASS_1_DAN 30 +#define EEP_FAN2_BYPASS_2_DAN 31 +#define EEP_FAN2_BYPASS_3_DAN 32 +#define EEP_FAN2_BYPASS_4_DAN 33 + +#define EEP_FILTER_CLEAN_HOUR_H 34 +#define EEP_FILTER_CLEAN_HOUR_L 35 +#define EEP_FILTER_CHANGE_HOUR_H 36 +#define EEP_FILTER_CHANGE_HOUR_L 37 +#define EEP_SOJA_CHANGE_HOUR_H 38 +#define EEP_SOJA_CHANGE_HOUR_L 39 + +#define EEP_BLACKOUT_POWER_ON 40 +#define EEP_BLACKOUT_RUN_MODE 41 +#define EEP_BLACKOUT_FAN_MODE 42 + +/* 260520 히스테리시스 프리셋(임계+데드밴드) 영속화 영역 43~127 + - 구 m_*_Level (45~68) 영역 폐기·재사용. 1프레임=4B, 페이지 127엔트리 한계 내(약 123) */ +#define EEP_HYST_PRESET 43 /* 1B : Hyst_Preset 0~2 (유효성 마커 겸용) */ +#define EEP_HYST_DB_BASE 44 /* 12B u8 : Co2_Db[3],Pm25_Db[3],Pm10_Db[3],Voc_Db[3] */ +#define EEP_THR_CO2_BASE 56 /* 24B u16: Co2_Thr[3][4] */ +#define EEP_THR_VOC_BASE 80 /* 24B u16: Voc_Thr[3][4] */ +#define EEP_THR_PM25_BASE 104 /* 12B u8 : Pm25_Thr[3][4] */ +#define EEP_THR_PM10_BASE 116 /* 12B u8 : Pm10_Thr[3][4] (116~127) */ + +#define EEP_SIZE 128 + + +//--------------------------------------------------- + +#define COMMAND_REQUEST_FILTER_INFO 0x05 +#define COMMAND_REQUEST_SENSOR_INFO 0x06 +#define COMMAND_CONTROLL 0x07 // mode / speed / reservaion + +#define TYPE_POWER 0x40 +#define TYPE_MODE 0x01 +#define TYPE_FAN_SPEED 0x02 +#define TYPE_RESERVATION 0x04 +#define TYPE_FILTER_INFO 0x10 +#define TYPE_SENSOR_INFO 0x20 +#define TYPE_HOOD_STATE 0x40 // add 2022.1.25 +#define TYPE_SEND_FLAG 0x80 + + + +extern volatile uint8_t Roomcon_connect_mode; +extern volatile uint32_t Set_Reserve_timer_sec; +extern volatile uint8_t Set_Run_Mode, Set_Fan_Mode; +extern uint32_t urpm1, urpm2; +extern uint8_t EEP_Save_Flag; + +extern uint8_t Sometime_Mode; + +extern uint8_t BlackOut_Power_On; +extern uint8_t BlackOut_Run_Mode; +extern uint8_t BlackOut_Fan_Mode; + +extern uint8_t Command_request_type; +/* PC대시보드 제어 → 룸컨(RJ2) 상태 푸시 래치. bunbaegi 의 Command_request_type=0 클리어와 무관하게 + * 유지되어 룸컨 누락 방지. TYPE_POWER(0x40)=TYPE_HOOD_STATE 충돌 때문에 모드/풍량 비트만 사용. */ +extern volatile uint8_t Homenet_RJ_Request; + + +uint16_t Diffuser_Damper_process(uint8_t mode);//100ms +uint8_t Air_Quality_damper_process(void); +uint8_t Air_Quality_color_process(void); + +extern volatile uint16_t CO2_Histeresys; + +extern volatile uint8_t Err_Code; +extern uint8_t Target_Fan1_Speed, Target_Fan2_Speed; + +extern volatile uint32_t Reserve_timer_sec; + +extern uint8_t s_FAN1_VEN_1_DAN; +extern uint8_t s_FAN1_VEN_2_DAN; +extern uint8_t s_FAN1_VEN_3_DAN; +extern uint8_t s_FAN1_VEN_4_DAN; +extern uint8_t s_FAN1_AIR_1_DAN; +extern uint8_t s_FAN1_AIR_2_DAN; +extern uint8_t s_FAN1_AIR_3_DAN; +extern uint8_t s_FAN1_AIR_4_DAN; +extern uint8_t s_FAN1_BYPASS_1_DAN; +extern uint8_t s_FAN1_BYPASS_2_DAN; +extern uint8_t s_FAN1_BYPASS_3_DAN; +extern uint8_t s_FAN1_BYPASS_4_DAN; + +extern uint8_t s_FAN2_VEN_1_DAN; +extern uint8_t s_FAN2_VEN_2_DAN; +extern uint8_t s_FAN2_VEN_3_DAN; +extern uint8_t s_FAN2_VEN_4_DAN; +extern uint8_t s_FAN2_AIR_1_DAN; +extern uint8_t s_FAN2_AIR_2_DAN; +extern uint8_t s_FAN2_AIR_3_DAN; +extern uint8_t s_FAN2_AIR_4_DAN; +extern uint8_t s_FAN2_BYPASS_1_DAN; +extern uint8_t s_FAN2_BYPASS_2_DAN; +extern uint8_t s_FAN2_BYPASS_3_DAN; +extern uint8_t s_FAN2_BYPASS_4_DAN; + + +extern signed int In_Temperature; +extern signed int Out_Temperature; +extern uint8_t Heater_OnOff, UV_OnOff; +extern uint16_t com_roomcon_delay; +extern uint8_t Filter_Reset_Flag; + +extern uint8_t RJ_Vsp_Mode; + +extern volatile uint32_t Reserve_timer_sec; +extern volatile uint8_t Reserve_hour, Pre_Reserve_hour; + +extern uint16_t m_CO2_Level_1; +extern uint16_t m_CO2_Level_2; +extern uint16_t m_CO2_Level_3,m_CO2_Level_4; + +extern uint16_t m_VOC_Level_1; +extern uint16_t m_VOC_Level_2; +extern uint16_t m_VOC_Level_3,m_VOC_Level_4; + +extern uint16_t m_PM2_5_Level_1; +extern uint16_t m_PM2_5_Level_2; +extern uint16_t m_PM2_5_Level_3,m_PM2_5_Level_4; + +extern uint32_t Damper_Status_Display; +extern uint8_t Force_Damper_Mode; +extern uint8_t Force_Damper_run; +extern uint8_t Focus_Mode; +extern uint16_t Focus_Mode_RunTime; +extern uint8_t ROOM_air_volume[7]; + +/* 260520 사양 자동 동작로직 (집중/분산) - My_system.c */ +extern uint16_t Co2_Thr[3][4]; +extern uint16_t Pm25_Thr[3][4]; +extern uint16_t Pm10_Thr[3][4]; +extern uint16_t Voc_Thr[3][4]; +extern uint16_t Co2_Db[3]; +extern uint16_t Pm25_Db[3]; +extern uint16_t Pm10_Db[3]; +extern uint16_t Voc_Db[3]; +extern uint8_t Hyst_Preset; /* 0 ECO / 1 NORMAL / 2 TURBO */ +extern uint8_t Room_Level[7]; /* 실별 오염단계 0~4 */ +extern uint8_t Load_Score; /* 부하 총점 0~16 */ +extern uint8_t Auto_P_max; +extern uint8_t Auto_dP; +extern uint8_t Auto_Concentrate; /* 0 분산 / 1 집중 */ + + +uint8_t Hood_process(void); +void Hood_RS485_process(void); + +extern uint16_t Hood_Warming_up_Timer; +extern uint8_t Tx_Yeundong_Delay; + +extern uint8_t Yuendong_Enable; +extern uint8_t Yeungong_Status; +extern uint8_t Hood_Power_On; +extern uint8_t Hood_Fan_Mode; +extern uint8_t Hood_Control; + +extern uint8_t Ext_Run_Mode, Pre_Ext_Run_Mode, Ext_Select_Room, Pre_Ext_Select_Room; +extern uint8_t Hood_Status; +extern uint8_t Hood_Yeundong_flag; +extern uint16_t Ext_Run_Mode_Off_Delay; +extern uint8_t Memory_Hood_Status; +extern uint8_t My_Memory_Run_Mode, My_Memory_Fan_Mode; +extern uint8_t Hood_YeunDong_Enable; +extern uint16_t Hood_Conn_Timeout; /* 후드 485 통신연결 생존 카운터(ms) */ + +extern uint8_t HREV_Hood_Control; + +/* HOMENET(ErvDashboard) 바이너리 프로토콜 - My_Uart.c */ +void Homenet_Rx_Byte(uint8_t b); +void Homenet_Process(void); +void Homenet_Send_Status(void); +void Homenet_Build_Status(uint8_t *p); +extern uint8_t Homenet_Reset_State; + +extern uint8_t Total_Air_Volume, Pre_Total_Air_Volume; +extern uint8_t Light_Bright[6]; \ No newline at end of file diff --git a/program/User/My_system.c b/program/User/My_system.c new file mode 100644 index 0000000..1e94451 --- /dev/null +++ b/program/User/My_system.c @@ -0,0 +1,1245 @@ +#include +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" +#include "EEPROM_Emulate.h" + + +#include "My_define.h" + + + + +void delay_us(uint32_t us) +{ + CLK_SysTickDelay(us); +} + + +void delay_ms(uint32_t ms) +{ + while(ms--) + { + delay_us(1000); + } +} + + +void UART0_Init()//hood +{ + /*---------------------------------------------------------------------------------------------------------*/ + /* Init UART */ + /*---------------------------------------------------------------------------------------------------------*/ + SYS_ResetModule(UART0_RST); + UART_Open(UART0, 9600); + + + UART_EnableInt(UART0, UART_IER_RDA_IE_Msk); + NVIC_EnableIRQ(UART0_IRQn); +} + + +void UART1_Init() +{ + /*---------------------------------------------------------------------------------------------------------*/ + /* Init UART */ + /*---------------------------------------------------------------------------------------------------------*/ + SYS_ResetModule(UART1_RST); + UART_Open(UART1, 115200); // HOMENET_485 : ErvDashboard 바이너리 프로토콜 (115200 N81) + + UART_EnableInt(UART1, UART_IER_RDA_IE_Msk); + NVIC_EnableIRQ(UART1_IRQn); +} + +void SC0_Init() // to roomcon +{ + SCUART_Open(SC0, 1200); + // Enable smartcard receive interrupt + SCUART_ENABLE_INT(SC0, SC_IER_RDA_IE_Msk); + NVIC_EnableIRQ(SC0_IRQn); +} + + +void SC1_Init() // to display +{ + SCUART_Open(SC1, 115200); + // Enable smartcard receive interrupt + SCUART_ENABLE_INT(SC1, SC_IER_RDA_IE_Msk); + NVIC_EnableIRQ(SC1_IRQn); +} + + + + +void PowerDownFunction(void) +{ +; +} + +volatile uint32_t Bldc1_signal = 0, Bldc2_signal = 0; + +void GPABC_IRQHandler(void) +{ + uint32_t reg; + + if(GPIO_GET_INT_FLAG(PA, BIT13)) + { + GPIO_CLR_INT_FLAG(PA, BIT13); + CLK->WK_INTSTS = 1; /* clear interrupt status */ + Bldc2_signal++; + } + else + { + reg = PA->ISRC; PA->ISRC = reg; + reg = PB->ISRC; PB->ISRC = reg; + reg = PC->ISRC; PC->ISRC = reg; + } +} +void GPDEF_IRQHandler(void) +{ + uint32_t reg; + + if(GPIO_GET_INT_FLAG(PE, BIT5)) + { + GPIO_CLR_INT_FLAG(PE, BIT5); + CLK->WK_INTSTS = 1; /* clear interrupt status */ + Bldc1_signal++; + } + else + { + reg = PD->ISRC; PD->ISRC = reg; + reg = PE->ISRC; PE->ISRC = reg; + reg = PF->ISRC; PF->ISRC = reg; + } +} + + + +volatile uint16_t Process_1000ms = 0, Process_333ms = 0,Process_100ms = 0, Process_10ms = 2,Process_5ms = 0; +uint16_t com_roomcon_delay = 0; +uint8_t Rx_homenet_TimeOut, Tx_homenet_TimeOut; +uint16_t InCom_polling_timer = 0; + +uint16_t Hood_polling_timer = 0; +uint8_t rx_hood_485_TimeOut = 0; +uint16_t Hood_Conn_Timeout = 0; /* 후드 통신연결 생존 카운터(ms). 유효 응답 수신 시 재충전, 0이면 미연결 */ + +void TMR0_IRQHandler(void) +{ + if(rx_hood_485_TimeOut)rx_hood_485_TimeOut--; + if(Hood_polling_timer)Hood_polling_timer--; + if(Hood_Conn_Timeout)Hood_Conn_Timeout--; + + if(InCom_polling_timer)InCom_polling_timer--; + if(Tx_homenet_TimeOut)Tx_homenet_TimeOut--; + if(Rx_homenet_TimeOut)Rx_homenet_TimeOut--; + if(Rx_roomcon_TimeOut)Rx_roomcon_TimeOut--; + + if(com_roomcon_delay)com_roomcon_delay--; + + if(Process_1000ms)Process_1000ms--; + if(Process_333ms)Process_333ms--; + if(Process_100ms)Process_100ms--; + if(Process_10ms)Process_10ms--; + if(Process_5ms)Process_5ms--; + + // clear timer interrupt flag + TIMER_ClearIntFlag(TIMER0); +} + +// TIMER_ClearWakeupFlag(TIMER0); +void Timer0_Init(void) +{ + TIMER_Open(TIMER0, TIMER_PERIODIC_MODE, 1000); // 1ms -> HZ + + // Enable timer interrupt + TIMER_EnableInt(TIMER0); + NVIC_EnableIRQ(TMR0_IRQn); + + + // Start Timer 0 + TIMER_Start(TIMER0); +} + + +void TMR1_IRQHandler(void) +{ + Step_process(); + + // clear timer interrupt flag + TIMER_ClearIntFlag(TIMER1); +} + +void Timer1_Init(void) +{ + TIMER_Open(TIMER1, TIMER_PERIODIC_MODE, 1000); // 2ms -> HZ + + // Enable timer interrupt + TIMER_EnableInt(TIMER1); + NVIC_EnableIRQ(TMR1_IRQn); + + + // Start Timer 0 + TIMER_Start(TIMER1); +} + + +void BLDC1_Duty_Change(uint32_t BLDC1_duty) // 0 ~ 10000 +{ + PWM_ConfigOutputChannel(PWM1, 0, 1000, BLDC1_duty); // BLDC1 +} +void BLDC2_Duty_Change(uint32_t BLDC2_duty) // 0 ~ 10000 +{ + PWM_ConfigOutputChannel(PWM0, 0, 1000, BLDC2_duty); // BLDC2 +} +void PWM_Init(void) +{ + // PWM0 frequency is 300Hz, duty 50% + PWM_ConfigOutputChannel(PWM0, 0, 1000, 10000); // BLDC2 + PWM_ConfigOutputChannel(PWM1, 0, 1000, 10000); // BLDC1 + + + // Enable output of all PWM channels + PWM_EnableOutput(PWM0, 1<<0); // ch0 + PWM_EnableOutput(PWM1, 1<<0); // + + // Start + PWM_Start(PWM0, 1<<0); // pwm0_ch0 + PWM_Start(PWM1, 1<<0); + +} + +volatile uint8_t ADC_Complete = 0; +void ADC_IRQHandler(void) +{ + uint32_t u32Flag; + + // Get ADC conversion finish interrupt flag + u32Flag = ADC_GET_INT_FLAG(ADC, ADC_ADF_INT); + + if(u32Flag & ADC_ADF_INT) + { + ADC_Complete = 1; + } + ADC_CLR_INT_FLAG(ADC, u32Flag); + +} + +void ADC_Init(void) +{ + + // Enable channel 1 + ADC_Open(ADC, ADC_INPUT_MODE_SINGLE_END, ADC_OPERATION_MODE_SINGLE_CYCLE, ADC_CH_0_MASK|ADC_CH_1_MASK|ADC_CH_2_MASK|ADC_CH_3_MASK|ADC_CH_4_MASK); + + // Set reference voltage to AVDD + ADC_SET_REF_VOLTAGE(ADC, ADC_REFSEL_POWER); + + + // Power on ADC + ADC_POWER_ON(ADC); + + // Enable ADC ADC_IF interrupt + ADC_EnableInt(ADC, ADC_ADF_INT); + NVIC_EnableIRQ(ADC_IRQn); + + + ADC_START_CONV(ADC); + +} + + +void GPIO_Init(void) +{ + GPIO_SetMode(PA, BIT13, GPIO_PMD_INPUT); // BLDC2_FG + GPIO_ENABLE_PULL_UP(PA, BIT13); + GPIO_EnableInt(PA, 13, GPIO_INT_FALLING); + + GPIO_SetMode(PA, BIT11, GPIO_PMD_INPUT); // SW + GPIO_SetMode(PE, BIT5, GPIO_PMD_INPUT); // BLDC1_FG + GPIO_ENABLE_PULL_UP(PE, BIT5); + GPIO_EnableInt(PE, 5, GPIO_INT_FALLING); + + GPIO_SetMode(PC, BIT7, GPIO_PMD_OUTPUT); // + BUNBAGI_485_DIR = 0; + + GPIO_SetMode(PB, BIT6, GPIO_PMD_OUTPUT); // + HOMENET_485_DIR = 0; + + GPIO_SetMode(PB, BIT2, GPIO_PMD_OUTPUT); // + HOOD_485_DIR = 0; + + GPIO_SetMode(PB, BIT7, GPIO_PMD_OUTPUT); // BLDC_PW + BLDC_PW = 1; // OFF + + GPIO_SetMode(PA, BIT5, GPIO_PMD_OUTPUT); // ROOM_PW + UV_PW = 1; + + GPIO_SetMode(PA, BIT10, GPIO_PMD_OUTPUT); // STATUS LED + ST_LED = 1; + + GPIO_SetMode(PF, BIT2, GPIO_PMD_OUTPUT); // UV + P_UV = 0; + + GPIO_SetMode(PA, BIT15|BIT14|BIT6, GPIO_PMD_OUTPUT); // STEP + GPIO_SetMode(PB, BIT3|BIT9|BIT10|BIT12|BIT13|BIT14|BIT15|BIT8, GPIO_PMD_OUTPUT); // STEP + GPIO_SetMode(PC, BIT8|BIT9|BIT10|BIT11|BIT2|BIT3|BIT14|BIT15|BIT6, GPIO_PMD_OUTPUT); // STEP + GPIO_SetMode(PD, BIT15|BIT14|BIT7|BIT6, GPIO_PMD_OUTPUT); // STEP + + + NVIC_EnableIRQ(GPABC_IRQn); + NVIC_EnableIRQ(GPDEF_IRQn); + + /* Enable interrupt de-bounce function and select de-bounce sampling cycle time */ + GPIO_SET_DEBOUNCE_TIME(GPIO_DBCLKSRC_HCLK, GPIO_DBCLKSEL_1); + GPIO_ENABLE_DEBOUNCE(PA, BIT12); + GPIO_ENABLE_DEBOUNCE(PE, BIT5); + + +} + + +void SYS_Init(void) +{ + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable clock source */ + CLK_EnableXtalRC(CLK_PWRCTL_LIRC_EN_Msk|CLK_PWRCTL_HIRC_EN_Msk); + + /* Waiting for clock source ready */ + CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk|CLK_CLKSTATUS_HIRC_STB_Msk); + + /* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */ + /* Set HCLK clock */ + CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_HCLK_CLK_DIVIDER(1)); + + /* Enable IP clock */ + CLK_EnableModuleClock(GPIO_MODULE); + CLK_EnableModuleClock(ADC_MODULE); +// CLK_EnableModuleClock(I2C0_MODULE); +// CLK_EnableModuleClock(I2C1_MODULE); +// CLK_EnableModuleClock(PWM0_CH23_MODULE); + CLK_EnableModuleClock(PWM0_CH01_MODULE); + CLK_EnableModuleClock(PWM1_CH01_MODULE); + CLK_EnableModuleClock(ISP_MODULE); + CLK_EnableModuleClock(SC0_MODULE); + CLK_EnableModuleClock(SC1_MODULE); + CLK_EnableModuleClock(SRAM_MODULE); + CLK_EnableModuleClock(TICK_MODULE); + CLK_EnableModuleClock(TMR0_MODULE); + CLK_EnableModuleClock(TMR1_MODULE); + CLK_EnableModuleClock(UART0_MODULE); + CLK_EnableModuleClock(UART1_MODULE); + CLK_EnableModuleClock(WDT_MODULE); + + /* Set IP clock */ + + CLK_SetModuleClock(ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1)); +// CLK_SetModuleClock(PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HIRC, MODULE_NoMsk); + CLK_SetModuleClock(PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HIRC, MODULE_NoMsk); + CLK_SetModuleClock(PWM1_CH01_MODULE, CLK_CLKSEL2_PWM1_CH01_S_HIRC, MODULE_NoMsk); + CLK_SetModuleClock(SC0_MODULE, CLK_CLKSEL2_SC_S_HIRC, CLK_SC0_CLK_DIVIDER(6)); + CLK_SetModuleClock(SC1_MODULE, CLK_CLKSEL2_SC_S_HIRC, CLK_SC1_CLK_DIVIDER(1)); + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HIRC, MODULE_NoMsk); + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1_S_HIRC, MODULE_NoMsk); + CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_UART_CLK_DIVIDER(1)); + CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_UART_CLK_DIVIDER(1)); + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + + + + //If the defines do not exist in your project, please refer to the corresponding sys.h in the Header folder appended to the tool package. + SYS->PA_H_MFP = SYS_PA_H_MFP_PA12_MFP_PWM0_CH0 | SYS_PA_H_MFP_PA9_MFP_SC0_DAT | SYS_PA_H_MFP_PA8_MFP_SC0_CLK; + SYS->PA_L_MFP = SYS_PA_L_MFP_PA4_MFP_ADC_CH4 | SYS_PA_L_MFP_PA3_MFP_ADC_CH3 | SYS_PA_L_MFP_PA2_MFP_ADC_CH2 | SYS_PA_L_MFP_PA1_MFP_ADC_CH1 | SYS_PA_L_MFP_PA0_MFP_ADC_CH0; + SYS->PB_H_MFP = SYS_PB_H_MFP_PB11_MFP_PWM1_CH0; + SYS->PB_L_MFP = SYS_PB_L_MFP_PB5_MFP_UART1_TX | SYS_PB_L_MFP_PB4_MFP_UART1_RX | SYS_PB_L_MFP_PB1_MFP_UART0_TX | SYS_PB_L_MFP_PB0_MFP_UART0_RX; + SYS->PC_H_MFP = 0x00000000; + SYS->PC_L_MFP = SYS_PC_L_MFP_PC1_MFP_SC1_DAT | SYS_PC_L_MFP_PC0_MFP_SC1_CLK; + SYS->PD_H_MFP = 0x00000000; + SYS->PD_L_MFP = 0x00000000; + SYS->PE_L_MFP = 0x00000000; + SYS->PF_L_MFP = SYS_PF_L_MFP_PF1_MFP_ICE_CLK | SYS_PF_L_MFP_PF0_MFP_ICE_DAT; + + + + /* Lock protected registers */ + SYS_LockReg(); + + return; + +} + + +volatile uint8_t Run_Mode = 0, Auto_Mode = 0, Fan_Mode = 0; +uint8_t Power_On = 0; + + +extern signed int Out_Temperature; +extern uint8_t Fan1_Speed, Fan2_Speed; + +volatile uint32_t Reserve_timer_sec = 0; + +uint16_t Filter_timer_sec = 1800; +volatile uint16_t Filter_timer_clean = 0; +volatile uint16_t Filter_timer_change = 0; +volatile uint16_t Soja_timer_change = 0; + + + + + +void Reservation_process(void) +{ + if(Power_On == 1)// power on - run + { + if(Reserve_timer_sec)Reserve_timer_sec--; + + if(Reserve_timer_sec == 1) + { + Power_off_process(1); + } + + } +} + + +uint16_t UV_OnOff_Timer = 0; +void UV_process(void) // 1sec +{ + if(Roomcon_connect_mode == 0) + { + + UV_OnOff = 0x00; + + if((Power_On == 0)) + { + UV_OnOff_Timer = 0; + return; + } + + if(UV_OnOff_Timer++ >= 3600)UV_OnOff_Timer = 0; + + + if((Run_Mode == MODE_VENTILATION)||(Run_Mode == MODE_AUTO)||(Run_Mode == MODE_AIRCLEAN)) + { +#if(((SPEC_DEVICE_TYPE_INFO&0x0F) == 0x06)||((SPEC_DEVICE_TYPE_INFO&0x0F) == 0x08))//EF1 + if(Run_Mode == MODE_AIRCLEAN) + { + if(UV_OnOff_Timer < 1800) + { + UV_OnOff = 0x10; + } + } +#elif((SPEC_DEVICE_TYPE_INFO&0x0F) == 0x04)//EBSN + if(Fan_Mode >= 2) + { + if(UV_OnOff_Timer < 900) + { + UV_OnOff = 0x10; + } + } +#endif + } + } + + if(Power_On == 1) + { + if(UV_OnOff == 0x10) + { + if(Fan1_Speed != 0) P_UV = 1; + else P_UV = 0; + } + else + { + P_UV = 0; + } + } + else + { + P_UV = 0; + } + +} + +extern volatile uint8_t Err_Code; + +void Filter_process(void) +{ + if(Power_On == 1) + { + if(Filter_timer_sec++ >= 3600) + { + Filter_timer_sec = 0; + + if(Filter_timer_clean++ >= 2000) + { + Filter_timer_clean = 2000; + Err_Code |= ERROR_FILTER_CLEAN; + } + + if(Filter_timer_change++ >= 4000) + { + Filter_timer_change = 4000; + Err_Code |= ERROR_FILTER_CHANGE; + } + + if(Soja_timer_change++ >= 20000) + { + Soja_timer_change = 20000; + Err_Code |= ERROR_SOJA_CHANGE; + } + + EEP_Save_Flag = 1; + } + } + + if(Filter_Reset_Flag == 1) + { + Filter_Reset_Flag = 0; + if(Filter_Reset_Process() == 1)EEP_Save_Flag = 1; + } + +} + +uint8_t Sometime_cycle = 0, Pre_Sometime_cycle = 0; +uint8_t Protect_Mode = 0; + + +uint16_t Sometime_Timer = 0; +uint8_t Sometime_Mode = 0; +uint8_t Sometime_before_speed = 0; +uint8_t Sometime_before_mode = 0; + +uint8_t Kijer_Mode = 0; +uint16_t Kijer_Timer = 0; + +void Exception_mode_process(void) +{ + if(Out_Temperature <= -15) + { + Protect_Mode = 1; + Err_Code |= ERROR_PROTECT; + + Sometime_Mode = 0; + Err_Code &= ~ERROR_SOMETIME; + + } + else if(Out_Temperature >= -13) + { + Protect_Mode = 0; + Err_Code &= ~ERROR_PROTECT; + } + + + + if((Out_Temperature <= -7)&&(Protect_Mode == 0)) + { + if((Power_On == 1)&&(Run_Mode == MODE_AUTO)) + { + if(Sometime_Mode == 0) + { + Sometime_Mode = 1; + Err_Code |= ERROR_SOMETIME; + + Sometime_Timer = 1800; // 30min + + } + } + else + { + Sometime_Mode = 0; + Err_Code &= ~ERROR_SOMETIME; + } + } + + if(Out_Temperature >= -5) + { + if(Sometime_Mode == 1) + { + Sometime_Mode = 0; + Err_Code &= ~ERROR_SOMETIME; + } + } + + if(Protect_Mode == 1) + { + if(Power_On == 0) + { + return; + } + else + { + Run_Mode = MODE_VENTILATION; + Fan_Mode = 0; + Reserve_timer_sec = 0; + + Power_off_process(1); + } + } + else if(Sometime_Mode == 1) + { + if((Power_On == 0)||(Run_Mode != MODE_AUTO)) + { + Sometime_Timer = 0; + Pre_Sometime_cycle = Sometime_cycle = 0; + Sometime_Mode = 0; + Err_Code &= ~ERROR_SOMETIME; + return; + } + + if(Sometime_Timer > 600) // 600 ~ 1800 -- 20min + { + Sometime_cycle = 1; + Sometime_Timer--; + } + else if(Sometime_Timer > 0) // 600 ~ 0 -- 10min + { + Sometime_cycle = 0; + Sometime_Timer--; + } + else + { + Sometime_cycle = 0; + Sometime_Timer = 1800; + } + + if(Sometime_cycle != Pre_Sometime_cycle) + { + if(Sometime_cycle == 1) + { + Run_Mode = MODE_AUTO; + Fan_Mode = 1; + } + else + { + Run_Mode = MODE_AUTO; + Fan_Mode = 0; + } + + Pre_Sometime_cycle = Sometime_cycle; + + } + } + else + { + Pre_Sometime_cycle = Sometime_cycle = 0; + } +} + +//------------------------------------------------ + +typedef struct { + char name; // 변수 이름 (a, b, c, d) + uint8_t value; // 변수 값 +}Var; + +Var vars[4] = { + {'1', 0}, + {'2', 0}, + {'3', 0}, + {'4', 0} +}; + +// 내림차순 정렬 함수 +int compare(const void *x, const void *y) { + Var *a = (Var *)x; + Var *b = (Var *)y; + + // 값이 큰 순서대로 + if (b->value != a->value) + return b->value - a->value; + else + return a->name - b->name; // 값이 같으면 이름 순으로 +} + +//----------------------------------------------- + +uint8_t CO2_quality[7] = {0,}; +uint8_t PM2_5_quality[7] = {0,}; +uint8_t VOC_quality[7] = {0,}; +uint8_t ROOM_air_volume[7] = {0,}; +uint16_t volatile CO2_Histeresys = 50; + +uint16_t Focus_Mode_RunTime = 0; +uint8_t Focus_Mode = 0; +uint8_t Focus_Air_Volume = 0; +uint8_t Focus_Room_Number = 0; + +uint8_t Pre_Ext_Run_Mode = 0; +uint16_t Ext_Run_Mode_Off_Delay = 0; +uint8_t Memory_Hood_Status = 0; + +uint8_t RJ_Memory_Run_Mode = 0, RJ_Memory_Fan_Mode = 0; +uint8_t My_Memory_Run_Mode = 0, My_Memory_Fan_Mode = 0; + +uint8_t Hood_YeunDong_Enable = 0; + +uint8_t Total_CV_Mode_Factot = 0; +uint8_t Total_CVP_Fan_Factor = 0; + +/* ============================================================================ + * 260428 v.Final 자동 동작로직 (집중/분산) - 제어로직_260428.xlsx (정본) + * 실별 4종 센서를 0~4 단계로 변환 -> 실별 최고단계(Level) -> 부하총점(Score)/dP + * - 풍량 단수 : Score 매핑 (0->0, 1~4->1, 5~8->2, 9~12->3, 13~16->4) + * - dP = 정렬 내림차순[0]-[1] (두번째로 높은 단계, 동점 포함) + * - 댐퍼 : P_max==0 전체대기 / dP>=2 집중(P_max 실만) / 그 외 분산(1단계↑ 실만) + * ==========================================================================*/ + +/* 공기질 센서 히스테리시스 — 모드별(0=ECO,1=NORMAL,2=TURBO) 오염단계 상한 임계값. + * [preset][4개 상한] = 0/1/2/3단계(좋음/보통/나쁨/매우나쁨)의 상한, 그 초과는 4단계(최악). + * (변경 가능 : HOMENET 프리셋 값 설정으로 갱신) - 기본값은 사양서 표(260613 10p) */ +uint16_t Co2_Thr[3][4] = {{1000,1300,1600,2000}, {800,1100,1400,1700}, {700,1000,1300,1600}}; +uint16_t Pm25_Thr[3][4] = {{ 20, 38, 60, 86}, { 14, 29, 49, 69}, { 12, 23, 38, 52}}; +uint16_t Pm10_Thr[3][4] = {{ 40, 86, 126, 173}, { 28, 66, 102, 138}, { 24, 53, 78, 104}}; +uint16_t Voc_Thr[3][4] = {{ 171, 195, 308, 438}, {120, 150, 250, 350}, {103, 120, 192, 263}}; + +/* 히스테리시스 데드밴드(하강 시) [preset] : CO2,PM2.5,PM10,VOC */ +uint16_t Co2_Db[3] = { 50, 50, 30}; +uint16_t Pm25_Db[3] = { 2, 2, 2}; +uint16_t Pm10_Db[3] = { 5, 5, 5}; +uint16_t Voc_Db[3] = { 5, 5, 3}; + +uint8_t Hyst_Preset = 1; /* 0 ECO / 1 NORMAL / 2 TURBO */ +uint8_t Room_Level[7] = {0,}; /* 실별 오염단계 0~4 (1=거실 2=침1 3=침2 4=침3) */ +uint8_t Load_Score = 0; /* 부하 총점 0~16 */ +uint8_t Auto_P_max = 0; /* 최고 단계 */ +uint8_t Auto_dP = 0; /* P_max - P_2nd */ +uint8_t Auto_Concentrate = 0; /* 0 분산 / 1 집중 (HOMENET autoState) */ + +/* 센서별 이전 단계(히스테리시스 데드존 유지용) */ +static uint8_t Prev_CO2_Lv[7] = {0,}; +static uint8_t Prev_PM25_Lv[7] = {0,}; +static uint8_t Prev_PM10_Lv[7] = {0,}; +static uint8_t Prev_VOC_Lv[7] = {0,}; + +/* 센서값 -> 0~4 단계. 하강 시 (임계-데드밴드) 이하라야 내려감. 데드존이면 이전 단계 유지 */ +static uint8_t sensor_level(uint16_t v, const uint16_t *T, uint16_t db, uint8_t prev) +{ + uint8_t lv = prev; + if (v <= (uint16_t)(T[0] - db)) lv = 0; + else if ((v > T[0]) && (v <= (uint16_t)(T[1] - db))) lv = 1; + else if ((v > T[1]) && (v <= (uint16_t)(T[2] - db))) lv = 2; + else if ((v > T[2]) && (v <= (uint16_t)(T[3] - db))) lv = 3; + else if (v > T[3]) lv = 4; + return lv; +} + +/* 부하 총점(0~16) -> 풍량 단수(0~4) */ +static uint8_t score_to_stage(uint8_t score) +{ + if (score == 0) return 0; + if (score <= 4) return 1; + if (score <= 8) return 2; + if (score <= 12) return 3; + return 4; +} + +uint8_t Air_Quality_damper_process(void) +{ + uint8_t Tmp_Air_Volume = 0; + uint8_t room_CV_quality = 0, room_CVP_quality = 0; + uint8_t Room_Num = 0; + + + Tmp_Air_Volume = 0; + + if(Force_Damper_Mode == 1) + { + if(Damper_Status_Display & 0x01){Memory_Diffuser_Dmp_Ang_SA[4] = 110;}else{Memory_Diffuser_Dmp_Ang_SA[4] = 0;}; + if(Damper_Status_Display & 0x02){Memory_Diffuser_Dmp_Ang_RA[4] = 110;}else{Memory_Diffuser_Dmp_Ang_RA[4] = 0;}; + if(Damper_Status_Display & 0x04){Memory_Diffuser_Dmp_Ang_SA[3] = 110;}else{Memory_Diffuser_Dmp_Ang_SA[3] = 0;}; + if(Damper_Status_Display & 0x08){Memory_Diffuser_Dmp_Ang_RA[3] = 110;}else{Memory_Diffuser_Dmp_Ang_RA[3] = 0;}; + if(Damper_Status_Display & 0x10){Memory_Diffuser_Dmp_Ang_SA[2] = 110;}else{Memory_Diffuser_Dmp_Ang_SA[2] = 0;}; + if(Damper_Status_Display & 0x20){Memory_Diffuser_Dmp_Ang_RA[2] = 110;}else{Memory_Diffuser_Dmp_Ang_RA[2] = 0;}; + if(Damper_Status_Display & 0x40){Memory_Diffuser_Dmp_Ang_SA[1] = 110;}else{Memory_Diffuser_Dmp_Ang_SA[1] = 0;}; + if(Damper_Status_Display & 0x80){Memory_Diffuser_Dmp_Ang_RA[1] = 110;}else{Memory_Diffuser_Dmp_Ang_RA[1] = 0;}; + + if((Memory_Diffuser_Dmp_Ang_SA[4] != 0)||(Memory_Diffuser_Dmp_Ang_RA[4] != 0))Diffuser_Air_quality[4] = 5; + else Diffuser_Air_quality[4] = 0; + + if((Memory_Diffuser_Dmp_Ang_SA[3] != 0)||(Memory_Diffuser_Dmp_Ang_RA[3] != 0))Diffuser_Air_quality[3] = 5; + else Diffuser_Air_quality[3] = 0; + + if((Memory_Diffuser_Dmp_Ang_SA[2] != 0)||(Memory_Diffuser_Dmp_Ang_RA[2] != 0))Diffuser_Air_quality[2] = 5; + else Diffuser_Air_quality[2] = 0; + + if((Memory_Diffuser_Dmp_Ang_SA[1] != 0)||(Memory_Diffuser_Dmp_Ang_RA[1] != 0))Diffuser_Air_quality[1] = 5; + else Diffuser_Air_quality[1] = 0; + + Tmp_Air_Volume = Set_Fan_Mode; + + Ext_Run_Mode_Off_Delay = 0; + + goto PASS_RETURN; + } + else if((Ext_Run_Mode == 1)&&(Pre_Ext_Run_Mode != 1)) //안심회복 모드 + { + Memory_Diffuser_Dmp_Ang_SA[6] = 110; + Memory_Diffuser_Dmp_Ang_SA[5] = 110; + Memory_Diffuser_Dmp_Ang_SA[4] = 110; + Memory_Diffuser_Dmp_Ang_SA[3] = 110; + Memory_Diffuser_Dmp_Ang_SA[2] = 110; + Memory_Diffuser_Dmp_Ang_SA[1] = 110; + + Memory_Diffuser_Dmp_Ang_RA[6] = 0; + Memory_Diffuser_Dmp_Ang_RA[5] = 0; + Memory_Diffuser_Dmp_Ang_RA[4] = 0; + Memory_Diffuser_Dmp_Ang_RA[3] = 0; + Memory_Diffuser_Dmp_Ang_RA[2] = 0; + Memory_Diffuser_Dmp_Ang_RA[1] = 0; + + Memory_Diffuser_Dmp_Ang_SA[Ext_Select_Room] = 0; + Memory_Diffuser_Dmp_Ang_RA[Ext_Select_Room] = 110; + + Diffuser_Air_quality[6] = 5;//ON + Diffuser_Air_quality[5] = 5;//ON + Diffuser_Air_quality[4] = 5;//ON + Diffuser_Air_quality[3] = 5;//ON + Diffuser_Air_quality[2] = 5;//ON + Diffuser_Air_quality[1] = 5;//ON + + Tmp_Air_Volume = 2;//3;/////////////// 2026.1.8 전경선... + + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + + My_Memory_Run_Mode = Run_Mode; + My_Memory_Fan_Mode = Fan_Mode; + + Set_Run_Mode = MODE_VENTILATION; + Set_Fan_Mode = 2;//3; /////////////// 2026.1.8 전경선... + + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + goto PASS_VOLUME; + } + else if((Ext_Run_Mode == 2)&&(Pre_Ext_Run_Mode != 2)) //쾌적조리 En + { + Hood_YeunDong_Enable = 1; + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + } + else if((Ext_Run_Mode == 3)&&(Pre_Ext_Run_Mode != 3)) //집중청정 모드 + { + Memory_Diffuser_Dmp_Ang_SA[6] = 0; + Memory_Diffuser_Dmp_Ang_SA[5] = 0; + Memory_Diffuser_Dmp_Ang_SA[4] = 0; + Memory_Diffuser_Dmp_Ang_SA[3] = 0; + Memory_Diffuser_Dmp_Ang_SA[2] = 0; + Memory_Diffuser_Dmp_Ang_SA[1] = 0; + + Memory_Diffuser_Dmp_Ang_RA[6] = 0; + Memory_Diffuser_Dmp_Ang_RA[5] = 0; + Memory_Diffuser_Dmp_Ang_RA[4] = 0; + Memory_Diffuser_Dmp_Ang_RA[3] = 0; + Memory_Diffuser_Dmp_Ang_RA[2] = 0; + Memory_Diffuser_Dmp_Ang_RA[1] = 0; + + Memory_Diffuser_Dmp_Ang_SA[Ext_Select_Room] = 110; + Memory_Diffuser_Dmp_Ang_RA[Ext_Select_Room] = 110; + + Diffuser_Air_quality[6] = 0;//OFF + Diffuser_Air_quality[5] = 0;//OFF + Diffuser_Air_quality[4] = 0;//OFF + Diffuser_Air_quality[3] = 0;//OFF + Diffuser_Air_quality[2] = 0;//OFF + Diffuser_Air_quality[1] = 0;//OFF + Diffuser_Air_quality[Ext_Select_Room] = 5;//ON + + Tmp_Air_Volume = 2; + + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + + My_Memory_Run_Mode = Run_Mode; + My_Memory_Fan_Mode = Fan_Mode; + + Set_Run_Mode = MODE_VENTILATION; + Set_Fan_Mode = 2; + + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + goto PASS_VOLUME; + } + else if(Ext_Run_Mode == 4) //스마트 수면 모드 (사양서 8p) : 환기 수동·1단 고정, 실별 CO2 기준 댐퍼 개폐 + { + if(Pre_Ext_Run_Mode != 4) /* 진입 1회 : 모드/풍량 + 초기상태(거실 CLOSE, 침실1~3 OPEN) */ + { + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + + My_Memory_Run_Mode = Run_Mode; + My_Memory_Fan_Mode = Fan_Mode; + + Set_Run_Mode = MODE_VENTILATION; + Set_Fan_Mode = 1; + + Memory_Diffuser_Dmp_Ang_SA[1] = 0; Memory_Diffuser_Dmp_Ang_RA[1] = 0; /* 거실 CLOSE */ + for(Room_Num = 2; Room_Num < 5; Room_Num++) /* 침실1~3 OPEN */ + { Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 110; Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 110; } + Memory_Diffuser_Dmp_Ang_SA[5] = 0; Memory_Diffuser_Dmp_Ang_RA[5] = 0; + Memory_Diffuser_Dmp_Ang_SA[6] = 0; Memory_Diffuser_Dmp_Ang_RA[6] = 0; + + Pre_Ext_Run_Mode = Ext_Run_Mode; + Pre_Ext_Select_Room = Ext_Select_Room; + } + + /* 매 틱 : 실별 CO2 히스테리시스. CO2 >= 1000 OPEN, <= 800 CLOSE, 그 사이(데드존)는 현재 상태 유지 */ + for(Room_Num = 1; Room_Num < 5; Room_Num++) + { + if(SEN66_CO2_value[Room_Num] >= 1000) + { Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 110; Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 110; } + else if(SEN66_CO2_value[Room_Num] <= 800) + { Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 0; Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 0; } + + if((Memory_Diffuser_Dmp_Ang_SA[Room_Num] != 0)||(Memory_Diffuser_Dmp_Ang_RA[Room_Num] != 0)) + Diffuser_Air_quality[Room_Num] = 5;//ON + else + Diffuser_Air_quality[Room_Num] = 0;//OFF + } + + Tmp_Air_Volume = 1; /* 1단 고정 */ + Ext_Run_Mode_Off_Delay = 0; + + goto PASS_VOLUME; + } + else if((Ext_Run_Mode == 0)&&((Pre_Ext_Run_Mode == 1)||(Pre_Ext_Run_Mode == 3)||(Pre_Ext_Run_Mode == 4))) + { + if(Power_On == 1) + { + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + + Set_Run_Mode = My_Memory_Run_Mode; + Set_Fan_Mode = My_Memory_Fan_Mode; + + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + } + Ext_Run_Mode_Off_Delay = 0; + } + else if((Ext_Run_Mode == 0)&&(Pre_Ext_Run_Mode == 2))// 쾌적조리(후드연동) 토글 OFF -> 연동 없음(사양 260613 9p 3.1) + { + Hood_YeunDong_Enable = 0; + /* 메이크업 에어 동작중(후드 가동/롤백 유지)이었으면 본래 운전모드/풍량으로 즉시 복귀(롤백 딜레이 없음) */ + if((Power_On == 1)&&((Hood_Status != 0)||(Hood_Yeundong_flag != 0)||(Hood_Warming_up_Timer != 0))) + { + Set_Run_Mode = My_Memory_Run_Mode; + Set_Fan_Mode = My_Memory_Fan_Mode; + Command_request_type |= (TYPE_MODE|TYPE_FAN_SPEED); + } + Hood_Yeundong_flag = 0; + Hood_Warming_up_Timer = 0; + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + goto PASS_VOLUME; + } + else if((Ext_Run_Mode != 0)&&(Ext_Run_Mode != 2)) + { + Pre_Ext_Run_Mode = Ext_Run_Mode ; + Pre_Ext_Select_Room = Ext_Select_Room; + if(Run_Mode != MODE_AUTO)goto PASS_VOLUME; + } + + Total_CV_Mode_Factot = 0; + Total_CVP_Fan_Factor = 0; + + for(Room_Num = 1; Room_Num < 6; Room_Num++) + { + uint8_t lc, lp25, lp10, lvc, lvl; + + /* 4종 센서 각각 0~4 단계 (모드별 임계 + 하강 히스테리시스) */ + lc = sensor_level(SEN66_CO2_value[Room_Num], Co2_Thr[Hyst_Preset], Co2_Db[Hyst_Preset], Prev_CO2_Lv[Room_Num]); + lp25 = sensor_level(SEN66_pm2p5[Room_Num], Pm25_Thr[Hyst_Preset], Pm25_Db[Hyst_Preset], Prev_PM25_Lv[Room_Num]); + lp10 = sensor_level(SEN66_pm10p0[Room_Num], Pm10_Thr[Hyst_Preset], Pm10_Db[Hyst_Preset], Prev_PM10_Lv[Room_Num]); + lvc = sensor_level((uint16_t)SEN66_VOC_value[Room_Num], Voc_Thr[Hyst_Preset], Voc_Db[Hyst_Preset], Prev_VOC_Lv[Room_Num]); + + Prev_CO2_Lv[Room_Num]=lc; Prev_PM25_Lv[Room_Num]=lp25; Prev_PM10_Lv[Room_Num]=lp10; Prev_VOC_Lv[Room_Num]=lvc; + + /* 실 오염단계 = 4종 중 최고 */ + lvl = lc; + if(lp25 > lvl) lvl = lp25; + if(lp10 > lvl) lvl = lp10; + if(lvc > lvl) lvl = lvc; + + Room_Level[Room_Num] = lvl; + ROOM_air_volume[Room_Num] = lvl; + if(lvl) Total_CV_Mode_Factot = 1; + + /* AUTO 외(수동/바이패스/공청) 및 전원OFF 댐퍼는 여기서 결정. + AUTO 는 집중/분산 판정 후 일괄 처리하므로 여기서 건드리지 않음 */ + if(Power_On != 1) + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 0; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 0; + Diffuser_Air_quality[Room_Num] = 0;//OFF + Diffuser_Damper_Manual[Room_Num] = 0; /* 전원OFF - 수동 댐퍼 해제 */ + } + else if(Run_Mode != MODE_AUTO) + { + /* 환기/공청/바이패스 : 전실 개방. 단, 대시보드 수동 댐퍼(Manual) 실은 위치 유지 */ + if(Diffuser_Damper_Manual[Room_Num] == 0) + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 110; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 110; + } + Diffuser_Air_quality[Room_Num] = 5;//ON + Tmp_Air_Volume = Diffuser_Fan_Speed[1] = Fan_Mode; //manual + } + else /* MODE_AUTO : 자동 제어 - 수동 댐퍼 해제 */ + { + Diffuser_Damper_Manual[Room_Num] = 0; + } + } + + if(Power_On != 1) + { + Focus_Mode = 0; + Focus_Mode_RunTime = 0; + Auto_Concentrate = 0; + Tmp_Air_Volume = 0; + } + + /* ===== 부하 총점(Score) / P_max / dP : 거실+침실3실(1~4) ===== */ + Load_Score = (uint8_t)(Room_Level[1] + Room_Level[2] + Room_Level[3] + Room_Level[4]); + { + uint8_t max1 = 0, max2 = 0, r, v; + /* 260428 v.Final : dP = 정렬 내림차순[0]-[1] (= 두번째로 높은 단계, 동점 포함). + 최고단계 실이 2개 이상 동점이면 max2=max1 -> dP=0 -> 분산. 한 실만 확실히(2↑) 나쁠 때만 집중. + 예) {0,3,3,0}->분산, {0,3,0,0}->집중, {2,2,1,1}->분산, {4,4,4,4}->분산 */ + for(r = 1; r < 5; r++) + { + v = Room_Level[r]; + if(v > max1) { max2 = max1; max1 = v; } /* 1·2위 갱신 */ + else if(v > max2) { max2 = v; } /* 2위만 갱신(동점 포함) */ + } + Auto_P_max = max1; + Auto_dP = (uint8_t)(max1 - max2); + } + + if(Run_Mode == MODE_AUTO) + { + /* 자동 = 환기 기반 */ + if(Auto_Mode != (MODE_VENTILATION+1)) + { + Auto_Mode = MODE_VENTILATION+1; + Command_request_type |= (TYPE_MODE); + } + + /* === 댐퍼 개폐 모드 결정 (대기 / 집중 / 분산) === */ + if(Auto_P_max == 0) /* 대기 : 전 실 OFF */ + { + Auto_Concentrate = 0; + Focus_Mode = 0; + for(Room_Num = 1; Room_Num < 7; Room_Num++) + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 0; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 0; + Diffuser_Air_quality[Room_Num] = 0; + } + } + else if(Auto_dP >= 2) /* 집중 : P_max 실만 개방 */ + { + Auto_Concentrate = 1; + Focus_Mode = 1; + for(Room_Num = 1; Room_Num < 7; Room_Num++) + { + if((Room_Num < 5) && (Room_Level[Room_Num] == Auto_P_max)) + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 110; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 110; + Diffuser_Air_quality[Room_Num] = 5; + } + else + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 0; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 0; + Diffuser_Air_quality[Room_Num] = 0; + } + } + } + else /* 분산 : 1단계 이상 실만 개방 (260428 : 0단계 좋음 실은 닫음) */ + { + Auto_Concentrate = 0; + Focus_Mode = 0; + for(Room_Num = 1; Room_Num < 7; Room_Num++) + { + if((Room_Num < 5) && (Room_Level[Room_Num] >= 1)) + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 110; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 110; + Diffuser_Air_quality[Room_Num] = 5; + } + else + { + Memory_Diffuser_Dmp_Ang_SA[Room_Num] = 0; + Memory_Diffuser_Dmp_Ang_RA[Room_Num] = 0; + Diffuser_Air_quality[Room_Num] = 0; + } + } + } + + /* === 최종 풍량 : 부하 총점 매핑 === */ + Tmp_Air_Volume = score_to_stage(Load_Score); + + if(Tmp_Air_Volume > 4) Tmp_Air_Volume = 4; + + if(Set_Fan_Mode != Tmp_Air_Volume) + { + Set_Fan_Mode = Diffuser_Fan_Speed[1] = Tmp_Air_Volume; + Command_request_type |= (TYPE_FAN_SPEED); + } + + } + else + { + Focus_Mode = 0; + Focus_Mode_RunTime = 0; + + /* 쾌적조리 메이크업 에어(사양 260613 9p) : 후드 가동중(Hood_Status!=0 / 연동플래그) + 전실 급기(SA) 100% 개방, 배기(RA) 닫힘. 풍량은 Hood_process() 가 후드 단수를 + 추종(1->1,2->2,3->3,4->4,5->4)하여 Set_Fan_Mode 로 반영. + 조리 종료 후 잔여 배출(메이크업 유지)은 후드측이 담당 → 후드 OFF 시 즉시 복귀. */ + if((Hood_YeunDong_Enable == 1)&&((Hood_Status != 0)||(Hood_Yeundong_flag == 1))) + { + Memory_Diffuser_Dmp_Ang_SA[1] = 110; + Memory_Diffuser_Dmp_Ang_RA[1] = 0; + + Memory_Diffuser_Dmp_Ang_SA[2] = 110; + Memory_Diffuser_Dmp_Ang_RA[2] = 0; + + Memory_Diffuser_Dmp_Ang_SA[3] = 110; + Memory_Diffuser_Dmp_Ang_RA[3] = 0; + + Memory_Diffuser_Dmp_Ang_SA[4] = 110; + Memory_Diffuser_Dmp_Ang_RA[4] = 0; + + Diffuser_Air_quality[1] = 5;//ON + Diffuser_Air_quality[2] = 5;//ON + Diffuser_Air_quality[3] = 5;//ON + Diffuser_Air_quality[4] = 5;//ON + } + } + + +PASS_VOLUME: + + if(Tmp_Air_Volume > 4)Tmp_Air_Volume = 4; + + if(Focus_Mode_RunTime != 0) + { + if(Tmp_Air_Volume != Focus_Air_Volume) + { + Command_request_type |= (TYPE_FAN_SPEED); + if(Tmp_Air_Volume > Focus_Air_Volume){Set_Fan_Mode = Focus_Air_Volume = Tmp_Air_Volume;} + else {Set_Fan_Mode = Tmp_Air_Volume = Focus_Air_Volume;} + } + } + + if(Ext_Run_Mode == 4) + { + if(Tmp_Air_Volume >= 2)Tmp_Air_Volume -= 1; + + if(Set_Fan_Mode != Tmp_Air_Volume) + { + Set_Fan_Mode = Diffuser_Fan_Speed[1] = Tmp_Air_Volume; + Command_request_type |= (TYPE_FAN_SPEED); + } + } + + /* ===== LED 추종 : 댐퍼 개방→LED ON(9), 닫힘/전원OFF→소등. + 수동 LED(CTRL_LED, Diffuser_Led_Manual)는 모든 모드에서 값 유지, 전원OFF 시에만 해제. ===== */ + for(Room_Num = 1; Room_Num < 5; Room_Num++) + { + if(Power_On != 1) Diffuser_Led_Manual[Room_Num] = 0; /* 전원OFF - 수동 LED 해제 */ + if(Diffuser_Led_Manual[Room_Num]) continue; /* 수동값 유지 */ + if((Power_On == 1) && ((Memory_Diffuser_Dmp_Ang_SA[Room_Num] != 0) || (Memory_Diffuser_Dmp_Ang_RA[Room_Num] != 0))) + Light_Bright[Room_Num] = 9; + else + Light_Bright[Room_Num] = 0; + } + +PASS_RETURN: + return(Tmp_Air_Volume); +} + + + +uint8_t Air_Quality_color_process(void) +{ + uint8_t room_CV_quality = 0, room_PM_quality = 0, total_room_CV_quality = 0, total_room_PM_quality = 0; + uint8_t Room_Num = 0; + + total_room_CV_quality = 0; + total_room_PM_quality = 0; + ///////////////////////////////////////////////// + return(0); + /////////////////////////////////////////////////// + + + + + + for(Room_Num = 1; Room_Num < 7; Room_Num++) + { + room_CV_quality = 0; + room_PM_quality = 0; + + if(SEN66_CO2_value[Room_Num] <= (uint16_t)(m_CO2_Level_1-CO2_Histeresys)) CO2_quality[Room_Num] = 0; // 2025.5.13 himpel + else if((SEN66_CO2_value[Room_Num] > (uint16_t)(m_CO2_Level_1))&&(SEN66_CO2_value[Room_Num] <= (uint16_t)(m_CO2_Level_2-CO2_Histeresys))) CO2_quality[Room_Num] = 0x01; + else if((SEN66_CO2_value[Room_Num] > (uint16_t)(m_CO2_Level_2))&&(SEN66_CO2_value[Room_Num] <= (uint16_t)(m_CO2_Level_3-CO2_Histeresys))) CO2_quality[Room_Num] = 0x02; + else if((SEN66_CO2_value[Room_Num] > (uint16_t)(m_CO2_Level_3))&&(SEN66_CO2_value[Room_Num] <= (uint16_t)(m_CO2_Level_4-CO2_Histeresys))) CO2_quality[Room_Num] = 0x04; + else if(SEN66_CO2_value[Room_Num] > (uint16_t)(m_CO2_Level_4)) CO2_quality[Room_Num] = 0x08; + + if(SEN66_pm2p5[Room_Num] <= m_PM2_5_Level_1) PM2_5_quality[Room_Num] = 0; + else if(SEN66_pm2p5[Room_Num] < m_PM2_5_Level_2) PM2_5_quality[Room_Num] = 0x01; + else if(SEN66_pm2p5[Room_Num] < m_PM2_5_Level_3) PM2_5_quality[Room_Num] = 0x02; + else if(SEN66_pm2p5[Room_Num] < m_PM2_5_Level_4) PM2_5_quality[Room_Num] = 0x04; + else PM2_5_quality[Room_Num] = 0x08; + + if(SEN66_VOC_value[Room_Num] <= m_VOC_Level_1) VOC_quality[Room_Num] = 0; + else if(SEN66_VOC_value[Room_Num] < m_VOC_Level_2) VOC_quality[Room_Num] = 0x01; + else if(SEN66_VOC_value[Room_Num] <= m_VOC_Level_3) VOC_quality[Room_Num] = 0x02; + else if(SEN66_VOC_value[Room_Num] <= m_VOC_Level_4) VOC_quality[Room_Num] = 0x04; + else VOC_quality[Room_Num] = 0x08; + + + room_CV_quality = CO2_quality[Room_Num] | VOC_quality[Room_Num]; + room_PM_quality = PM2_5_quality[Room_Num]; + + if(room_CV_quality == 0) //Quality - Good + { + Diffuser_Air_quality[Room_Num] = Memory_Diffuser_Air_quality[Room_Num] = 0; + } + else if(room_CV_quality < 2) //Quality - Normal + { + Diffuser_Air_quality[Room_Num] = Memory_Diffuser_Air_quality[Room_Num] = 5; + } + else if(room_CV_quality < 4) //Quality - Bad + { + Diffuser_Air_quality[Room_Num] = 5; + } + else if(room_CV_quality < 8) //Quality - Bad Bad + { + Diffuser_Air_quality[Room_Num] = Memory_Diffuser_Air_quality[Room_Num] = 5; + } + else //Quality - Very Bad + { + Diffuser_Air_quality[Room_Num] = Memory_Diffuser_Air_quality[Room_Num] = 5; + } + + total_room_CV_quality |= room_CV_quality; + total_room_PM_quality |= room_PM_quality; + } + + return(0); +} + diff --git a/program/User/main.c b/program/User/main.c new file mode 100644 index 0000000..11d4705 --- /dev/null +++ b/program/User/main.c @@ -0,0 +1,189 @@ +/**************************************************************************//** + * @file main.c + * @version V1.00 + * $Revision: 4 $ + * $Date: 14/09/11 5:23p $ + * @brief Show how to pixel on and off on LCD panel. + * + * @note + * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include +#include +#include "Nano100Series.h" +#include "adc.h" +#include "gpio.h" +#include "pwm.h" +#include "timer.h" +#include "uart.h" +#include "sys.h" +#include "clk.h" +#include "EEPROM_Emulate.h" + + +#include "My_define.h" + +#define __wdt_setting() SYS_UnlockReg(); WDT_Open(WDT_TIMEOUT_2POW14, 0, TRUE, FALSE); SYS_LockReg(); +#define __wdt_reset() SYS_UnlockReg(); WDT_RESET_COUNTER(); SYS_LockReg(); + + +extern volatile uint16_t Process_1000ms , Process_333ms, Process_100ms, Process_10ms, Process_5ms; +extern volatile uint8_t Err_Code; + + + +extern volatile uint8_t Tx_Mode_Event, Tx_Fan_Event, Tx_Reserve_Event; +extern volatile uint8_t Reserve_hour; + +extern volatile uint8_t Roomcon_connect_mode; + +uint32_t Reset_src_value = 0; + +// HERV~~~MAIN +void main(void) +{ +/* + // === 부팅 검증 코드 — 다른 모든 init 보다 먼저 === + { + // 1. SYS 보호 레지스터 unlock — BSP 함수 사용 + SYS_UnlockReg(); + + // 2. GPIO AHB 클럭 강제 활성화 (Nano100: CLK->AHBCLK bit 0 = GPIO_EN) + CLK->AHBCLK |= CLK_AHBCLK_GPIO_EN_Msk; + + // 3. PA10 을 push-pull OUTPUT 으로 강제 설정 (PMD[21:20] = 01) + PA->PMD &= ~(0x3UL << 20); + PA->PMD |= (0x1UL << 20); + + // 4. LED 무조건 토글 — 이게 깜박이면 부팅 자체는 정상 + while(1) { + PA->DOUT ^= (1UL << 10); + for(volatile uint32_t i = 0; i < 200000; i++); + } + } +*/ + + uint8_t Indicate_Error = 0; + + + +__disable_irq(); // NuEclipse(GCC) 포팅: __disable_interrupt() → __disable_irq() (CMSIS 표준) + + SYS_Init(); + + SYS_EnableBOD(SYS_BODCTL_BOD25_RST_EN_Msk, SYS_BODCTL_BOD25_EN_Msk); + + + ADC_Init(); + + GPIO_Init(); + PWM_Init(); + Timer0_Init(); + Timer1_Init(); + + UART0_Init(); // INT1 Hood + UART1_Init(); // to EX1 - homnet + SC0_Init(); // to RJ roomcon + SC1_Init(); // to EX2 --> BUNBAGI + + Init_EEPROM(eep_data_size, eep_page_amount); + Search_Valid_Page(); + +__enable_irq(); // NuEclipse(GCC) 포팅: __enable_interrupt() → __enable_irq() (CMSIS 표준) + + Reset_src_value = SYS_GetResetSrc(); + init_process(); + SYS_ClearResetSrc(Reset_src_value); + + __wdt_setting(); + + while(1) + { + Hood_RS485_process(); // Hood connect - uart0 + //com_display_process(); // display + com_roomcon_process(); // roomcon + InCom_process(); // Bunbaegi + Homenet_Process(); // HOMENET(ErvDashboard) 수신 명령 처리 + REQ_STATUS 응답 + + if(Process_5ms == 0) + { + Process_5ms = 5; + } + + if(Process_10ms == 0) + { + Process_10ms = 3000; + } + + if(Process_100ms == 0) + { + Process_100ms = 100; + Fan_Speed_process(); + Fan_Error_Check(); + Tx_display_flag = 1; + } + if(Process_333ms == 0) + { + Process_333ms = 200; + Hood_process(); + __wdt_reset(); + } + + Indicate_Error = Err_Code; + Indicate_Error &= ~(ERROR_SOMETIME|ERROR_PROTECT|ERROR_FILTER_CHANGE|ERROR_FILTER_CLEAN|ERROR_SOJA_CHANGE); + + if((Indicate_Error)) + { + if(Process_1000ms < 600)ST_LED = 0; + else ST_LED = 1; + } + else + { + if(Process_1000ms < 2)ST_LED = 0; + else ST_LED = 1; + } + + + if(Process_1000ms == 0) + { + Process_1000ms = 999; + + /* (꺼짐)예약 카운트다운 : 0 도달 시 전원 OFF (대시보드 CTRL_RESERVE) */ + if(Reserve_Remain_Sec > 0) + { + Reserve_Remain_Sec--; + if(Reserve_Remain_Sec == 0) + { + Power_On = 0; + Set_Run_Mode = 0; + Set_Fan_Mode = 0; + Command_request_type |= (TYPE_MODE | TYPE_FAN_SPEED); + } + } + + Bldc_check(); + ADC_Sensing(); + + Filter_process(); + + Air_Quality_color_process(); + Total_Air_Volume = Air_Quality_damper_process(); // 260520 사양 자동 동작로직(집중/분산) - 1s 주기 + Homenet_Send_Status(); // HOMENET(ErvDashboard) STATUS(0x81) 1s 주기 송신 + + RJ_Com_Err_Check(); +#if((SPEC_MODE_INFO&0x20) == 0x20) // UV 옵션 + UV_process(); // 1sec +#endif + + } + + if(EEP_Save_Flag == 1) + { + EEP_Save_Flag = 0; + EEP_Save_process(); + } + } +} diff --git a/program/User/pwm_duty10000.c b/program/User/pwm_duty10000.c new file mode 100644 index 0000000..4bd3cbf --- /dev/null +++ b/program/User/pwm_duty10000.c @@ -0,0 +1,536 @@ +/**************************************************************************//** + * @file PWM.c + * @version V1.00 + * $Revision: 14 $ + * $Date: 14/09/04 11:58a $ + * @brief NANO100 series PWM driver source file + * + * @note + * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "Nano100Series.h" + +/** @addtogroup NANO100_Device_Driver NANO100 Device Driver + @{ +*/ + +/** @addtogroup NANO100_PWM_Driver PWM Driver + @{ +*/ + + +/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions + @{ +*/ + +/** + * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigOutputChannel (PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32DutyCycle) +{ + uint32_t i; + uint32_t u32ClkSrc; + uint32_t u32PWM_Clock = SystemCoreClock; + uint8_t u8Divider = 1, u8Prescale = 0xFF; + uint16_t u16CNR = 0xFFFF; + + if(pwm == PWM0) + u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2)); + + else + u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2)); + + switch (u32ClkSrc) + { + case 0: + u32PWM_Clock = __HXT; + break; + case 1: + u32PWM_Clock = __LXT; + break; + case 2: + u32PWM_Clock = SystemCoreClock; + break; + case 3: + u32PWM_Clock = __HIRC12M; + break; + } + + for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16 + { + i = (u32PWM_Clock / u32Frequency) / u8Divider; + // If target value is larger than CNR * prescale, need to use a larger divider + if(i > (0x10000 * 0x100)) + continue; + + // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF + u8Prescale = (i + 0xFFFF)/ 0x10000; + + // u8Prescale must at least be 2, otherwise the output stop + if(u8Prescale < 3) + u8Prescale = 2; + + i /= u8Prescale; + + if(i <= 0x10000) + { + if(i == 1) + u16CNR = 1; // Too fast, and PWM cannot generate expected frequency... + else + u16CNR = i; + break; + } + + } + // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register + i = u32PWM_Clock / (u8Prescale * u8Divider * u16CNR); + + u8Prescale -= 1; + u16CNR -= 1; + // convert to real register value + if(u8Divider == 1) + u8Divider = 4; + else if (u8Divider == 2) + u8Divider = 0; + else if (u8Divider == 4) + u8Divider = 1; + else if (u8Divider == 8) + u8Divider = 2; + else // 16 + u8Divider = 3; + + // every two channels share a prescaler + while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk); + pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8)); + pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum)); + pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8)); + while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)); + if(u32DutyCycle == 0) + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; + else + { + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 10000 - 1) << PWM_DUTY_CM_Pos); + } + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR; + + return(i); +} + +/** + * @brief This function config PWM capture and get the nearest unit time + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec Unit time of counter + * @param[in] u32CaptureEdge Condition to latch the counter + * @return Nearest unit time in nano second + * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm, + uint32_t u32ChannelNum, + uint32_t u32UnitTimeNsec, + uint32_t u32CaptureEdge) +{ + uint32_t i; + uint32_t u32ClkSrc; + uint32_t u32PWM_Clock = SystemCoreClock; + uint8_t u8Divider = 1, u8Prescale = 0xFF; + uint16_t u16CNR = 0xFFFF; + + if(pwm == PWM0) + u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2)); + else + u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2)); + + switch (u32ClkSrc) + { + case 0: + u32PWM_Clock = __HXT; + break; + case 1: + u32PWM_Clock = __LXT; + break; + case 2: + u32PWM_Clock = SystemCoreClock; + break; + case 3: + u32PWM_Clock = __HIRC12M; + break; + } + + for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16 + { + i = ((long long)(u32PWM_Clock / u8Divider) * u32UnitTimeNsec) / 1000000000; + + // If target value is larger than 0xFF, need to use a larger divider + if(i > (0xFF)) + continue; + + u8Prescale = i; + + // u8Prescale must at least be 2, otherwise the output stop + if(u8Prescale < 3) + u8Prescale = 2; + + break; + } + + // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register + i = (long long) (u8Prescale * u8Divider) * 1000000000 / u32PWM_Clock; + + u8Prescale -= 1; + u16CNR -= 1; + // convert to real register value + if(u8Divider == 1) + u8Divider = 4; + else if (u8Divider == 2) + u8Divider = 0; + else if (u8Divider == 4) + u8Divider = 1; + else if (u8Divider == 8) + u8Divider = 2; + else // 16 + u8Divider = 3; + + // every two channels share a prescaler + while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk); + pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8)); + pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum)); + pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8)); + while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)); + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR; + + return(i); +} + +/** + * @brief This function start PWM module + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + */ +void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint8_t i; + uint32_t u32Mask = 0; + + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + u32Mask |= (PWM_CTL_CH0EN_Msk << (i * 8)); + } + + pwm->CTL |= u32Mask; +} + +/** + * @brief This function stop PWM module + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + */ +void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0; i < PWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1 << i)) + { + *(__IO uint32_t *) (&pwm->DUTY0 + 3 * i) &= ~PWM_DUTY_CN_Msk; + } + } + +} + +/** + * @brief This function stop PWM generation immediately by clear channel enable bit + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + */ +void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + pwm->CTL &= ~(PWM_CTL_CH0EN_Msk << (i * 8)); + } +} + +/** + * @brief This function enables PWM capture of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + */ +void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint8_t i; + uint32_t u32Mask = 0; + + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + { + u32Mask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8)); + } + } + + pwm->CAPCTL |= u32Mask; +} + +/** + * @brief This function disables PWM capture of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + */ +void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint8_t i; + uint32_t u32CTLMask = 0; + uint32_t u32CAPCTLMask = 0; + + for (i = 0; i < PWM_CHANNEL_NUM; i++) + { + if ( u32ChannelMask & (1 << i)) + { + u32CTLMask |= (PWM_CTL_CH0EN_Msk << (i * 8)); + u32CAPCTLMask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8)); + } + } + + pwm->CTL &= ~u32CTLMask; + pwm->CAPCTL &= ~u32CAPCTLMask; +} + +/** + * @brief This function enables PWM output generation of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + */ +void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask) +{ + pwm->OE |= u32ChannelMask; +} + +/** + * @brief This function disables PWM output generation of selected channels + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + */ +void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask) +{ + pwm->OE &= ~u32ChannelMask; +} + +/** + * @brief This function enable Dead zone of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no + * dead zone. + * @return None + */ +void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + // every two channels shares the same setting + u32ChannelNum >>= 1; + // set duration + pwm->PRES = (pwm->PRES & ~(PWM_PRES_DZ01_Msk << (8 * u32ChannelNum))) | ((u32Duration << PWM_PRES_DZ01_Pos ) << (8 * u32ChannelNum)); + // enable dead zone + pwm->CTL |= (PWM_CTL_DZEN01_Msk << u32ChannelNum); +} + +/** + * @brief This function disable Dead zone of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + */ +void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum) +{ + // every two channels shares the same setting + u32ChannelNum >>= 1; + // enable dead zone + pwm->CTL &= ~(PWM_CTL_DZEN01_Msk << u32ChannelNum); +} + +/** + * @brief This function enable capture interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Capture interrupt type. It could be either + * - \ref PWM_RISING_LATCH_INT_ENABLE + * - \ref PWM_FALLING_LATCH_INT_ENABLE + * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE + * @return None + */ +void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + // enable capture interrupt + pwm->CAPINTEN |= (u32Edge << (u32ChannelNum * 8)); +} + +/** + * @brief This function disable capture interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Capture interrupt type. It could be either + * - \ref PWM_RISING_LATCH_INT_ENABLE + * - \ref PWM_FALLING_LATCH_INT_ENABLE + * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE + * @return None + */ +void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + // disable capture interrupt + pwm->CAPINTEN &= ~(u32Edge << (u32ChannelNum * 8)); +} + +/** + * @brief This function clear capture interrupt flag of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Capture interrupt type. It could be either + * - \ref PWM_RISING_LATCH_INT_FLAG + * - \ref PWM_FALLING_LATCH_INT_FLAG + * - \ref PWM_RISING_FALLING_LATCH_INT_FLAG + * @return None + */ +void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + // disable capture interrupt flag + pwm->CAPINTSTS = (u32Edge + 1) << (u32ChannelNum * 8); +} + +/** + * @brief This function get capture interrupt flag of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Capture interrupt flag of specified channel + * @retval 0 Capture interrupt did not occurred + * @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred + * @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred + * @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred + */ +uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum) +{ + return ((pwm->CAPINTSTS >> (u32ChannelNum * 8)) & (PWM_RISING_FALLING_LATCH_INT_FLAG)); +} + +/** + * @brief This function enable period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType This parameter is not used + * @return None + * @note All channels share the same period interrupt type setting. + */ +void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + // enable period interrupt + pwm->INTEN |= (PWM_INTEN_TMIE0_Msk << u32ChannelNum); +} + +/** + * @brief This function disable period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + */ +void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum) +{ + pwm->INTEN &= ~(PWM_INTEN_TMIE0_Msk << u32ChannelNum); +} + +/** + * @brief This function clear period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + */ +void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum) +{ + // write 1 clear + pwm->INTSTS = (PWM_INTSTS_TMINT0_Msk << u32ChannelNum); +} + +/** + * @brief This function get period interrupt of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occurred + * @retval 1 Period interrupt occurred + */ +uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum) +{ + return ((pwm->INTSTS & (PWM_INTSTS_TMINT0_Msk << u32ChannelNum)) ? 1 : 0); +} + +/** + * @brief This function enable capture PDMA of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2 + * @param[in] u32RisingFirst Order of captured data transferred by PDMA. It could be either + * - \ref PWM_CAP_PDMA_RFORDER_R + * - \ref PWM_CAP_PDMA_RFORDER_F + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref PWM_RISING_LATCH_PDMA_ENABLE + * - \ref PWM_FALLING_LATCH_PDMA_ENABLE + * - \ref PWM_RISING_FALLING_LATCH_PDMA_ENABLE + * @return None + */ +void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + if (u32ChannelNum == 0) + pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD0_Msk | PWM_CAPCTL_CH0RFORDER_Msk)) | u32Mode | u32RisingFirst | PWM_CAPCTL_CH0PDMAEN_Msk; + else + pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD2_Msk | PWM_CAPCTL_CH2RFORDER_Msk)) | (u32Mode << 16)| (u32RisingFirst << 16)| PWM_CAPCTL_CH2PDMAEN_Msk; +} + +/** + * @brief This function disable capture PDMA of selected channel + * @param[in] pwm The base address of PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2 + * @return None + */ +void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum) +{ + if (u32ChannelNum == 0) + pwm->CAPCTL &= ~PWM_CAPCTL_CH0PDMAEN_Msk; + else + pwm->CAPCTL &= ~PWM_CAPCTL_CH2PDMAEN_Msk; +} + +/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group NANO100_PWM_Driver */ + +/*@}*/ /* end of group NANO100_Device_Driver */ + +/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/ diff --git a/program/User/typedefs.h b/program/User/typedefs.h new file mode 100644 index 0000000..e9e74fa --- /dev/null +++ b/program/User/typedefs.h @@ -0,0 +1,73 @@ +//============================================================================= +// S E N S I R I O N AG, Laubisruetistr. 50, CH-8712 Staefa, Switzerland +//============================================================================= +// Project : SHT3x Sample Code (V1.1) +// File : typedefs.h (V1.1) +// Author : RFU +// Date : 6-Mai-2015 +// Controller: STM32F100RB +// IDE : Vision V5.12.0.0 +// Compiler : Armcc +// Brief : Definitions of typedefs for good readability and portability. +//============================================================================= + + +//-- Defines ------------------------------------------------------------------ +//Processor endian system +//#define BIG ENDIAN //e.g. Motorola (not tested at this time) +#define LITTLE_ENDIAN //e.g. PIC, 8051, NEC V850 +//============================================================================= +// basic types: making the size of types clear +//============================================================================= +typedef unsigned char u8t; ///< range: 0 .. 255 +typedef signed char i8t; ///< range: -128 .. +127 + +typedef unsigned short u16t; ///< range: 0 .. 65535 +typedef signed short i16t; ///< range: -32768 .. +32767 + +typedef unsigned long u32t; ///< range: 0 .. 4'294'967'295 +typedef signed long i32t; ///< range: -2'147'483'648 .. +2'147'483'647 + +typedef float ft; ///< range: +-1.18E-38 .. +-3.39E+38 +typedef double dt; ///< range: .. +-1.79E+308 + +typedef enum{ + bFALSE = 0, + bTRUE = 1 +}bt; + +typedef union { + u16t u16; // element specifier for accessing whole u16 + i16t i16; // element specifier for accessing whole i16 + struct { + #ifdef LITTLE_ENDIAN // Byte-order is little endian + u8t u8L; // element specifier for accessing low u8 + u8t u8H; // element specifier for accessing high u8 + #else // Byte-order is big endian + u8t u8H; // element specifier for accessing low u8 + u8t u8L; // element specifier for accessing high u8 + #endif + } s16; // element spec. for acc. struct with low or high u8 +} nt16; + +typedef union { + u32t u32; // element specifier for accessing whole u32 + i32t i32; // element specifier for accessing whole i32 + struct { + #ifdef LITTLE_ENDIAN // Byte-order is little endian + u16t u16L; // element specifier for accessing low u16 + u16t u16H; // element specifier for accessing high u16 + #else // Byte-order is big endian + u16t u16H; // element specifier for accessing low u16 + u16t u16L; // element specifier for accessing high u16 + #endif + } s32; // element spec. for acc. struct with low or high u16 +} nt32; + +typedef enum{ + NO_ERROR = 0x00, // no error + ACK_ERROR = 0x01, // no acknowledgment error + CHECKSUM_ERROR = 0x02, // checksum mismatch error + TIMEOUT_ERROR = 0x04, // timeout error + PARM_ERROR = 0x80, // parameter out of range error +}etError; \ No newline at end of file diff --git a/program/build.sh b/program/build.sh new file mode 100644 index 0000000..c9b773b --- /dev/null +++ b/program/build.sh @@ -0,0 +1,154 @@ +#!/usr/bin/env bash +# NuEclipse/IAR 없이 Nuvoton NANO100 (Cortex-M0) 펌웨어 빌드 / 플래시 / 디버그. +# 이 프로젝트는 자체 Makefile (ARM-GCC) 을 사용하며, 본 스크립트는 PATH 설정 + +# make 래퍼 + openocd(Nu-Link) 플래시/디버그 진입점입니다. +# (참조: Nova/program/Main/build.sh 를 HERV 구조에 맞게 적응) +# +# 사용법: +# bash build.sh : 빌드 (기본 = rebuild, clean 후 전체 빌드 → 모든 컴파일 과정 표시) +# bash build.sh all : 증분 빌드 (변경된 파일만, 빠름) +# bash build.sh clean : clean +# bash build.sh rebuild : clean 후 재빌드 (기본과 동일) +# bash build.sh size : 메모리 사용량 출력 +# bash build.sh flash : Nu-Link(openocd) 로 내부 flash 쓰기 (ELF) +# bash build.sh erase : 칩 erase +# bash build.sh gdbserver : OpenOCD GDB server 시작 (포어그라운드, port 3333) +# bash build.sh debug : GDB 클라이언트 띄움 (gdbserver 별도 실행 필요) +# 환경: Windows + Git Bash / msys64 bash / VS Code Bash terminal. + +set -e + +# 출력이 너무 빨리 지나가거나 창이 바로 닫히지 않도록, 종료 시 키 입력 대기. +# 성공/실패(빌드 에러로 set -e 종료) 모두 멈춰서 결과를 확인할 수 있음. +# 단, 터미널이 아닌 경우(파이프/자동화)에는 멈추지 않음. +pause_on_exit() { + local code=$? + if [ -t 0 ]; then + echo "" + if [ "$code" -eq 0 ]; then + echo "=== 완료 (exit $code) ===" + else + echo "=== 실패 (exit $code) ===" + fi + read -n 1 -s -r -p "아무 키나 누르면 종료합니다..." + echo "" + fi +} +trap pause_on_exit EXIT + +# 프로젝트 디렉터리 (이 스크립트 위치 기준). +PROJ_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +BUILD_DIR="$PROJ_DIR/build" + +# Makefile 의 PROJECT 값에서 산출물 이름 추출 (예: HERV). +PROJECT="$(sed -n 's/^PROJECT[[:space:]]*:=[[:space:]]*//p' "$PROJ_DIR/Makefile" | head -1)" +ELF="$BUILD_DIR/$PROJECT.elf" + +# 툴체인 경로 (필요시 자기 환경에 맞게 수정). +ARM_GCC_BIN="/c/Program Files (x86)/Arm/GNU Toolchain mingw-w64-i686-arm-none-eabi/bin" +MSYS_BIN="/c/msys64/usr/bin" +# 디버그/플래시: OpenOCD-Nuvoton 포크 (Nu-Link/Nu-Link-Pro 정식 지원). +OPENOCD_BIN="/c/Nuvoton/OpenOCD/bin" + +export PATH="$ARM_GCC_BIN:$MSYS_BIN:$OPENOCD_BIN:$PATH" + +# 공통 함수: 빌드 툴 가용성. +check_build_tools() { + if ! command -v arm-none-eabi-gcc >/dev/null; then + echo "ERROR: arm-none-eabi-gcc not found. PATH 에 ARM toolchain 확인 (예상: $ARM_GCC_BIN)." + exit 1 + fi + if ! command -v make >/dev/null; then + echo "ERROR: make not found. msys64 설치 확인 (예상: $MSYS_BIN/make.exe)." + exit 1 + fi +} + +check_openocd() { + if ! command -v openocd >/dev/null; then + echo "ERROR: openocd not found. PATH 에 openocd 확인 (예상: $OPENOCD_BIN)." + echo " Nu-Link 사용 시 OpenOCD-Nuvoton 포크가 필요할 수 있습니다." + exit 1 + fi +} + +# 빌드: make 래퍼 (Makefile 이 elf/hex/bin/size 까지 생성). 인자로 타겟 전달 (기본 all). +do_build() { + check_build_tools + cd "$PROJ_DIR" + local target="${1:-all}" + echo "=== Building: make -j8 $target ===" + make -j8 "$target" +} + +# 플래시 (내부 flash, Nu-Link/openocd). Makefile flash 타겟 사용. +do_flash() { + check_build_tools + check_openocd + if [ ! -f "$ELF" ]; then + echo "ELF 가 없습니다. 먼저 빌드: bash build.sh" + exit 1 + fi + cd "$PROJ_DIR" + echo "=== Flashing internal flash via Nu-Link (openocd) ===" + echo "Image: $ELF" + make flash +} + +# 칩 erase. +do_erase() { + check_openocd + cd "$PROJ_DIR" + echo "=== Chip erase via Nu-Link (openocd) ===" + make erase +} + +# GDB server 시작 (OpenOCD, foreground; 별도 터미널에서 gdb 클라이언트 연결). +do_gdbserver() { + check_openocd + cd "$PROJ_DIR" + echo "=== OpenOCD GDB Server (port 3333) — Ctrl+C 종료 ===" + make debug-server +} + +# GDB 클라이언트 (인터랙티브 디버그) — OpenOCD gdbserver 가 이미 실행 중이어야 함. +do_debug() { + check_build_tools + if [ ! -f "$ELF" ]; then + echo "ELF 가 없습니다. 먼저 빌드: bash build.sh" + exit 1 + fi + local port="${1:-3333}" + echo "=== GDB client (OpenOCD gdbserver 가 port $port 에서 떠 있어야 함) ===" + arm-none-eabi-gdb \ + -ex "target extended-remote localhost:$port" \ + -ex "monitor reset halt" \ + -ex "load" \ + -ex "monitor reset halt" \ + "$ELF" +} + +# 서브커맨드 디스패치. (기본 = rebuild: clean 후 전체 빌드라 모든 컴파일 과정이 보임) +CMD="${1:-rebuild}" +case "$CMD" in + all|clean|rebuild|size|"") + do_build "$CMD" + ;; + flash) + do_flash + ;; + erase) + do_erase + ;; + gdbserver) + do_gdbserver "${2:-3333}" + ;; + debug) + do_debug "${2:-3333}" + ;; + *) + echo "Unknown command: $CMD" + echo "Usage: bash build.sh [all|clean|rebuild|size|flash|erase|gdbserver|debug]" + exit 1 + ;; +esac diff --git a/program/openocd.cfg b/program/openocd.cfg new file mode 100644 index 0000000..034d5d9 --- /dev/null +++ b/program/openocd.cfg @@ -0,0 +1,25 @@ +# ============================================================================= +# OpenOCD config - Nuvoton NANO100SE3BN + Nu-Link +# +# 전제: OpenOCD-Nuvoton (https://github.com/OpenNuvoton/OpenOCD-Nuvoton) 사용 +# 표준 OpenOCD 는 Nu-Link 어댑터 미지원 +# ============================================================================= + +# Nu-Link 디버거 (USB) +source [find interface/nulink.cfg] + +# 타깃: Cortex-M0 코어 + Nuvoton 플래시 +# Nuvoton OpenOCD 포크에 따라 이름이 다를 수 있음: +# - target/numicroM0.cfg (대부분의 버전) +# - target/nuc100.cfg +# - target/nano100.cfg +# 실제 설치된 OpenOCD share/openocd/scripts/target/ 폴더 확인 후 수정 +source [find target/numicroM0.cfg] + +# 어댑터 속도 (kHz). 안정성 문제 있으면 낮추세요. +# OpenOCD 0.11+ 는 "adapter speed", 0.10 (Nuvoton fork) 은 "adapter_khz" 사용. +if {[info commands adapter] != ""} { + adapter speed 1000 +} else { + adapter_khz 1000 +} diff --git a/개발사양서/각실제어시스템_개발사양서_DL_동작로직_260613.pptx b/개발사양서/각실제어시스템_개발사양서_DL_동작로직_260613.pptx new file mode 100644 index 0000000..3b4d608 Binary files /dev/null and b/개발사양서/각실제어시스템_개발사양서_DL_동작로직_260613.pptx differ diff --git a/기능검토결과서/DL/휴벤ECO_DL사양_기능검사결과_260325.xlsx b/기능검토결과서/DL/휴벤ECO_DL사양_기능검사결과_260325.xlsx new file mode 100644 index 0000000..7ae8eec Binary files /dev/null and b/기능검토결과서/DL/휴벤ECO_DL사양_기능검사결과_260325.xlsx differ diff --git a/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_251228.xlsx b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_251228.xlsx new file mode 100644 index 0000000..70d13f2 Binary files /dev/null and b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_251228.xlsx differ diff --git a/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260130.xlsx b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260130.xlsx new file mode 100644 index 0000000..c1dfb13 Binary files /dev/null and b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260130.xlsx differ diff --git a/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260203.xlsx b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260203.xlsx new file mode 100644 index 0000000..089dcd2 Binary files /dev/null and b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260203.xlsx differ diff --git a/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260204.xlsx b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260204.xlsx new file mode 100644 index 0000000..92e63f9 Binary files /dev/null and b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260204.xlsx differ diff --git a/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260206.xlsx b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260206.xlsx new file mode 100644 index 0000000..fa60d5c Binary files /dev/null and b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260206.xlsx differ diff --git a/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260408.xlsx b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260408.xlsx new file mode 100644 index 0000000..3677830 Binary files /dev/null and b/기능검토결과서/힘펠/각실제어시스템_힘펠사양_기능검사결과_260408.xlsx differ diff --git a/기능검토결과서/힘펠/전동디퓨저_기능검사결과_260408.xlsx b/기능검토결과서/힘펠/전동디퓨저_기능검사결과_260408.xlsx new file mode 100644 index 0000000..c3b139b Binary files /dev/null and b/기능검토결과서/힘펠/전동디퓨저_기능검사결과_260408.xlsx differ diff --git a/승인원/RJ2_룸컨_REV1.3_20240808(승인원).pdf b/승인원/RJ2_룸컨_REV1.3_20240808(승인원).pdf new file mode 100644 index 0000000..ad9b005 Binary files /dev/null and b/승인원/RJ2_룸컨_REV1.3_20240808(승인원).pdf differ diff --git a/승인원/분배기_REV1.0_20260212(승인원).pdf b/승인원/분배기_REV1.0_20260212(승인원).pdf new file mode 100644 index 0000000..f1a82d4 Binary files /dev/null and b/승인원/분배기_REV1.0_20260212(승인원).pdf differ diff --git a/승인원/휴벤eco_MAIN_REV2.0_2026.01.29(승인원).pdf b/승인원/휴벤eco_MAIN_REV2.0_2026.01.29(승인원).pdf new file mode 100644 index 0000000..b24d64f Binary files /dev/null and b/승인원/휴벤eco_MAIN_REV2.0_2026.01.29(승인원).pdf differ