chore: HERV 통합 저장소 재초기화 커밋
손상된 .git 히스토리(missing tree)로 재초기화 후 작업트리 전체 커밋. .claude/ 만 제외(로컬 에이전트 설정). 구 저장소 백업(.git_corrupt_backup/) 포함. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
jeon
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/**************************************************************************//**
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* @file EEPROM_Emulate.h
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* @brief Flash-based EEPROM emulation library for Nuvoton Nano100B series.
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*
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* @note
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* NEW IMPLEMENTATION - reverse-engineered from caller-side API only.
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* NOT BINARY COMPATIBLE with the original (factory) EEPROM_Emulate library.
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* If a board already has data written by the original library, this version
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* will treat that data as invalid and reset all settings to default (0xFF).
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*
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* Public API kept identical to the original so the application code compiles
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* without changes:
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* - Init_EEPROM(data_size, page_amount)
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* - Search_Valid_Page()
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* - Read_Data(index, *data) -> 0=OK, non-zero=error
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* - Write_Data(index, value) -> 0=OK, non-zero=error
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*
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* Implementation summary:
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* - Uses the last 1KB of APROM (2 flash pages, 512 bytes each).
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* - Append-only entry log inside each page (wear-leveled).
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* - Each entry is one 32-bit word: [TAG][index][~index][value].
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* - When active page is full, contents are compacted into the other page.
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* - RAM mirror of the data array for fast Read_Data().
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*
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******************************************************************************/
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#ifndef __EEPROM_EMULATE_H__
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#define __EEPROM_EMULATE_H__
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*--------------------------------------------------------------------------*/
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/* Configuration */
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/*--------------------------------------------------------------------------*/
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/* Maximum number of bytes the EEPROM can hold.
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* Must be >= the largest index your application uses (EEP_SIZE in My_define.h).
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* Current application uses EEP_SIZE = 69, so 128 leaves headroom. */
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#define EEP_DATA_SIZE 128u
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/* Number of flash pages used for the emulation (must be >= 2). */
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#define EEP_PAGE_COUNT 2u
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/* Flash page size on Nano100B series (do not change). */
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#define EEP_FLASH_PAGE_SIZE 0x200u /* 512 bytes */
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/* Base address of the EEPROM region inside APROM.
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* Default: last 1 KB of a 64 KB APROM (NANO100SE3BN has 64 KB).
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*
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* IMPORTANT - Linker script must guarantee that application code never
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* occupies this region. With the default linker script provided by Nuvoton
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* BSP this is fine as long as your firmware is < 63 KB. Verify with the
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* map file after build.
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*
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* If your part has a different APROM size, change this:
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* - 32 KB part : 0x7C00
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* - 64 KB part : 0xFC00 (default)
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* - 128 KB part: 0x1FC00
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*/
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#define EEP_FLASH_BASE 0xFC00u
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/*--------------------------------------------------------------------------*/
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/* Compatibility: variables expected by the application's main.c */
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/* Init_EEPROM(eep_data_size, eep_page_amount); */
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/*--------------------------------------------------------------------------*/
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extern const uint32_t eep_data_size;
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extern const uint32_t eep_page_amount;
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/*--------------------------------------------------------------------------*/
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/* Public API */
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/*--------------------------------------------------------------------------*/
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/**
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* @brief Initialize the EEPROM emulation layer.
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* @param data_size Logical size in bytes (clamped to EEP_DATA_SIZE).
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* @param page_amount Number of physical pages to use (currently fixed = 2).
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*
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* Must be called once before any Read/Write/Search call.
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* Enables FMC and unlocks protected registers.
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*/
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void Init_EEPROM(uint32_t data_size, uint32_t page_amount);
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/**
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* @brief Locate the active flash page and load its contents into the RAM
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* mirror. If no valid page is found, formats page 0 and starts fresh.
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*
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* Must be called once after Init_EEPROM(). After this call, Read_Data()
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* returns the latest committed value for each index.
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*/
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void Search_Valid_Page(void);
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/**
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* @brief Read one byte from the EEPROM mirror.
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* @param index Index into the data array (0 .. EEP_DATA_SIZE-1).
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* @param data Output pointer. Receives 0xFF if the byte was never written.
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* @return 0 on success, non-zero on parameter error.
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*/
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uint32_t Read_Data(uint8_t index, uint8_t *data);
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/**
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* @brief Write one byte to the EEPROM (RAM mirror + flash).
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* @param index Index into the data array (0 .. EEP_DATA_SIZE-1).
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* @param data Value to store.
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* @return 0 on success, non-zero on parameter error.
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*
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* If the active flash page becomes full, contents are automatically
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* compacted into the other page.
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*
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* If the value is unchanged, no flash write is performed (saves wear).
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*/
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uint32_t Write_Data(uint8_t index, uint8_t data);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EEPROM_EMULATE_H__ */
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@@ -0,0 +1,368 @@
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/**************************************************************************//**
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* @file adc.h
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* @version V1.00
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* $Revision: 10 $
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* $Date: 15/06/30 2:50p $
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* @brief NANO100 series ADC driver header file
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __ADC_H__
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#define __ADC_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_ADC_Driver ADC Driver
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@{
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*/
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/** @addtogroup NANO100_ADC_EXPORTED_CONSTANTS ADC Exported Constants
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@{
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*/
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#define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask */
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#define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask */
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#define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask */
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#define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask */
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#define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask */
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#define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask */
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#define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask */
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#define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask */
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#define ADC_CH_8_MASK (1UL << 8) /*!< ADC channel 8 mask */
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#define ADC_CH_9_MASK (1UL << 9) /*!< ADC channel 9 mask */
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#define ADC_CH_10_MASK (1UL << 10) /*!< ADC channel 10 mask */
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#define ADC_CH_11_MASK (1UL << 11) /*!< ADC channel 11 mask */
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#define ADC_CH_12_MASK (1UL << 12) /*!< ADC channel 12 mask */
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#define ADC_CH_13_MASK (1UL << 13) /*!< ADC channel 13 mask */
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#define ADC_CH_14_MASK (1UL << 14) /*!< ADC channel 14 mask */
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#define ADC_CH_15_MASK (1UL << 15) /*!< ADC channel 15 mask */
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#define ADC_CH_16_MASK (1UL << 16) /*!< ADC channel 16 mask */
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#define ADC_CH_17_MASK (1UL << 17) /*!< ADC channel 17 mask */
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#define ADC_CHEN_Msk (0x3FFFF) /*!< ADC channel 0 ~ 17 mask */
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#define ADC_PDMADATA_AD_PDMA_Msk (0xFFF) /*!< ADC PDMA current transfer data */
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#define ADC_CMP_LESS_THAN (0UL) /*!< ADC compare condition less than */
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#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR_CMPCOND_Msk) /*!< ADC compare condition greater or equal to */
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#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC (P3.2) pin */
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#define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) /*!< External pin low level trigger ADC */
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#define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) /*!< External pin high level trigger ADC */
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#define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) /*!< External pin falling edge trigger ADC */
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#define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) /*!< External pin rising edge trigger ADC */
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#define ADC_ADF_INT (ADC_SR_ADF_Msk) /*!< ADC convert complete interrupt */
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#define ADC_CMP0_INT (ADC_SR_CMPF0_Msk) /*!< ADC comparator 0 interrupt */
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#define ADC_CMP1_INT (ADC_SR_CMPF1_Msk) /*!< ADC comparator 1 interrupt */
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#define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CR_DIFF_Pos) /*!< ADC input mode set to single end */
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#define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CR_DIFF_Pos) /*!< ADC input mode set to differential */
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#define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to single conversion */
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#define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to single cycle scan */
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#define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to continuous scan */
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#define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CR_DIFF_Pos) /*!< ADC differential mode output format with unsigned */
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#define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CR_DIFF_Pos) /*!< ADC differential mode output format with 2's complement */
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#define ADC_RESSEL_6_BIT (0UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 6 bit */
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#define ADC_RESSEL_8_BIT (1UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 8 bit */
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#define ADC_RESSEL_10_BIT (2UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 10 bit */
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#define ADC_RESSEL_12_BIT (3UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 12 bit */
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#define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to power */
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#define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to Int_VREF */
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#define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to VREF */
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/*@}*/ /* end of group NANO100_ADC_EXPORTED_CONSTANTS */
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/** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
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@{
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*/
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/**
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* @brief Get the latest ADC conversion data
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Channel number
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* @return Latest ADC conversion data
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* \hideinitializer
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*/
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#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_RSLT_Msk)
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/**
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* @brief Return the user-specified interrupt flags
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* - \ref ADC_ADF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return User specified interrupt flags
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* \hideinitializer
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*/
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#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->SR & (u32Mask))
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/**
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* @brief This macro clear the selected interrupt status bits
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* - \ref ADC_ADF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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* \hideinitializer
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*/
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#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->SR = (ADC->SR & ~(ADC_SR_ADF_Msk | \
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ADC_SR_CMPF0_Msk | \
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ADC_SR_CMPF1_Msk)) | (u32Mask))
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/**
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* @brief Get the busy state of ADC
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* @param[in] adc Base address of ADC module
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* @return busy state of ADC
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* @retval 0 ADC is not busy
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* @retval 1 ADC is busy
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* \hideinitializer
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*/
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#define ADC_IS_BUSY(adc) (ADC->SR & ADC_SR_BUSY_Msk ? 1 : 0)
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/**
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* @brief Check if the ADC conversion data is over written or not
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Currently not used
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* @return Over run state of ADC data
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* @retval 0 ADC data is not overrun
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* @retval 1 ADC data us overrun
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* \hideinitializer
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*/
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#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_OVERRUN_Msk ? 1 : 0)
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/**
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* @brief Check if the ADC conversion data is valid or not
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Currently not used
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* @return Valid state of ADC data
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* @retval 0 ADC data is not valid
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* @retval 1 ADC data us valid
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* \hideinitializer
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*/
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#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_VALID_Msk ? 1 : 0)
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/**
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* @brief Power down ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_POWER_DOWN(adc) (ADC->CR &= ~ADC_CR_ADEN_Msk)
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/**
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* @brief Power on ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_POWER_ON(adc) \
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do { \
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ADC->CR |= ADC_CR_ADEN_Msk; \
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while ((!(ADC->SR & ADC_SR_INITRDY_Msk)) || (!(ADC->PWRCTL & ADC_PWRCTL_PWUPRDY_Msk))); \
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} while(0)
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/**
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* @brief Configure the comparator 0 and enable it
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
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* @param[in] u32Condition Specifies the compare condition
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* - \ref ADC_CMP_LESS_THAN
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* - \ref ADC_CMP_GREATER_OR_EQUAL_TO
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* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
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* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
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* @return None
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* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
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* Means ADC will assert comparator 0 flag if channel 5 conversion result is
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* greater or equal to 0x800 for 10 times continuously.
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* \hideinitializer
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*/
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#define ADC_ENABLE_CMP0(adc, \
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u32ChNum, \
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u32Condition, \
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u32Data, \
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u32MatchCount) (ADC->CMPR0 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \
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(u32Condition) | \
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((u32Data) << ADC_CMPR_CMPD_Pos) | \
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(((u32MatchCount) - 1) << ADC_CMPR_CMPMATCNT_Pos) |\
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ADC_CMPR_CMPEN_Msk)
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/**
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* @brief Disable comparator 0
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_DISABLE_CMP0(adc) (ADC->CMPR0 = 0)
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/**
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* @brief Configure the comparator 1 and enable it
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
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* @param[in] u32Condition Specifies the compare condition
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* - \ref ADC_CMP_LESS_THAN
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* - \ref ADC_CMP_GREATER_OR_EQUAL_TO
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* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
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* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
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* @return None
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* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
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* Means ADC will assert comparator 1 flag if channel 5 conversion result is
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* greater or equal to 0x800 for 10 times continuously.
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* \hideinitializer
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*/
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#define ADC_ENABLE_CMP1(adc, \
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u32ChNum, \
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u32Condition, \
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u32Data, \
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u32MatchCount) (ADC->CMPR1 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \
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(u32Condition) | \
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((u32Data) << ADC_CMPR_CMPD_Pos) | \
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((u32MatchCount - 1) << ADC_CMPR_CMPMATCNT_Pos) |\
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ADC_CMPR_CMPEN_Msk)
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/**
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* @brief Disable comparator 1
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_DISABLE_CMP1(adc) (ADC->CMPR1 = 0)
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/**
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* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* \hideinitializer
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*/
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#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_Msk) | (u32Mask))
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/**
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* @brief Start the A/D conversion.
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
|
||||
*/
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#define ADC_START_CONV(adc) (ADC->CR |= ADC_CR_ADST_Msk)
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/**
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* @brief Stop the A/D conversion.
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* @param[in] adc Base address of ADC module
|
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* @return None
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||||
* \hideinitializer
|
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*/
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#define ADC_STOP_CONV(adc) (ADC->CR &= ~ADC_CR_ADST_Msk)
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/**
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* @brief Set the output format in differential input mode.
|
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* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Format Differential input mode output format. Valid values are:
|
||||
* - \ref ADC_DMODE_OUT_FORMAT_UNSIGNED
|
||||
* - \ref ADC_DMODE_OUT_FORMAT_2COMPLEMENT
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_DMOF(adc, u32Format) (ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32Format)
|
||||
|
||||
/**
|
||||
* @brief Set the resolution of conversion result.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Resolution The resolution of conversion result. Valid values are:
|
||||
* - \ref ADC_RESSEL_6_BIT
|
||||
* - \ref ADC_RESSEL_8_BIT
|
||||
* - \ref ADC_RESSEL_10_BIT
|
||||
* - \ref ADC_RESSEL_12_BIT
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_RESOLUTION(adc, u32Resolution) (ADC->CR = (ADC->CR & ~ADC_CR_RESSEL_Msk) | u32Resolution)
|
||||
|
||||
/**
|
||||
* @brief Set the reference voltage selection.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Ref The reference voltage selection. Valid values are:
|
||||
* - \ref ADC_REFSEL_POWER
|
||||
* - \ref ADC_REFSEL_INT_VREF
|
||||
* - \ref ADC_REFSEL_VREF
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk) | u32Ref)
|
||||
|
||||
/**
|
||||
* @brief Set power down mode.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Mode The power down mode. 0: power down mode, 2: standby mode
|
||||
* @param[in] u32CalEn Do calibration when power up.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_POWERDOWN_MODE(adc, u32Mode, u32CalEn) \
|
||||
ADC->PWRCTL = (ADC->PWRCTL & ~(ADC_PWRCTL_PWDMOD_Msk | ADC_PWRCTL_PWDCALEN_Msk)) \
|
||||
| (u32Mode << ADC_PWRCTL_PWDMOD_Pos) | (u32CalEn << ADC_PWRCTL_PWDCALEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Enable PDMA transfer.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_PDMA(adc) (ADC->CR |= ADC_CR_PTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable PDMA transfer.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_PDMA(adc) (ADC->CR &= ~ADC_CR_PTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get PDMA current transfer data
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return PDMA current transfer data
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMADATA_AD_PDMA_Msk)
|
||||
|
||||
void ADC_Open(ADC_T *adc,
|
||||
uint32_t u32InputMode,
|
||||
uint32_t u32OpMode,
|
||||
uint32_t u32ChMask);
|
||||
void ADC_Close(ADC_T *adc);
|
||||
void ADC_EnableHWTrigger(ADC_T *adc,
|
||||
uint32_t u32Source,
|
||||
uint32_t u32Param);
|
||||
void ADC_DisableHWTrigger(ADC_T *adc);
|
||||
void ADC_EnableTimerTrigger(ADC_T *adc,
|
||||
uint32_t u32Source,
|
||||
uint32_t u32PDMACnt);
|
||||
void ADC_DisableTimerTrigger(ADC_T *adc);
|
||||
void ADC_SetExtraSampleTime(ADC_T *adc,
|
||||
uint32_t u32ChNum,
|
||||
uint32_t u32SampleTime);
|
||||
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
|
||||
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_ADC_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__ADC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,368 @@
|
||||
/**************************************************************************//**
|
||||
* @file clk.h
|
||||
* @version V1.00
|
||||
* $Revision: 20 $
|
||||
* $Date: 15/07/08 10:00a $
|
||||
* @brief Nano100 series CLK driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CLK_H__
|
||||
#define __CLK_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_CLK_Driver CLK Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_CLK_EXPORTED_CONSTANTS CLK Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
#define FREQ_128MHZ 128000000
|
||||
#define FREQ_120MHZ 120000000
|
||||
#define FREQ_48MHZ 48000000
|
||||
#define FREQ_42MHZ 42000000
|
||||
#define FREQ_32MHZ 32000000
|
||||
#define FREQ_24MHZ 24000000
|
||||
#define FREQ_12MHZ 12000000
|
||||
|
||||
/********************* Bit definition of PWRCTL register **********************/
|
||||
#define CLK_PWRCTL_HXT_EN (0x1UL<<CLK_PWRCTL_HXT_EN_Pos) /*!<Enable high speed crystal */
|
||||
#define CLK_PWRCTL_LXT_EN (0x1UL<<CLK_PWRCTL_LXT_EN_Pos) /*!<Enable low speed crystal */
|
||||
#define CLK_PWRCTL_HIRC_EN (0x1UL<<CLK_PWRCTL_HIRC_EN_Pos) /*!<Enable internal high speed oscillator */
|
||||
#define CLK_PWRCTL_LIRC_EN (0x1UL<<CLK_PWRCTL_LIRC_EN_Pos) /*!<Enable internal low speed oscillator */
|
||||
#define CLK_PWRCTL_DELY_EN (0x1UL<<CLK_PWRCTL_WK_DLY_Pos) /*!<Enable the wake-up delay counter */
|
||||
#define CLK_PWRCTL_WAKEINT_EN (0x1UL<<CLK_PWRCTL_PD_WK_IE_Pos) /*!<Enable the wake-up interrupt */
|
||||
#define CLK_PWRCTL_PWRDOWN_EN (0x1UL<<CLK_PWRCTL_PD_EN_Pos) /*!<Power down enable bit */
|
||||
#define CLK_PWRCTL_HXT_SELXT (0x1UL<<CLK_PWRCTL_HXT_SELXT_Pos) /*!<High frequency crystal loop back path Enabled */
|
||||
#define CLK_PWRCTL_HXT_GAIN (0x1UL<<CLK_PWRCTL_HXT_GAIN_Pos) /*!<High frequency crystal Gain control Enabled */
|
||||
#define CLK_PWRCTL_LXT_SCNT (0x1UL<<CLK_PWRCTL_LXT_SCNT_Pos) /*!<Delay 8192 LXT before LXT output */
|
||||
|
||||
|
||||
/********************* Bit definition of AHBCLK register **********************/
|
||||
#define CLK_AHBCLK_GPIO_EN (0x1UL<<CLK_AHBCLK_GPIO_EN_Pos) /*!<GPIO clock enable */
|
||||
#define CLK_AHBCLK_DMA_EN (0x1UL<<CLK_AHBCLK_DMA_EN_Pos) /*!<DMA clock enable */
|
||||
#define CLK_AHBCLK_ISP_EN (0x1UL<<CLK_AHBCLK_ISP_EN_Pos) /*!<Flash ISP controller clock enable */
|
||||
#define CLK_AHBCLK_EBI_EN (0x1UL<<CLK_AHBCLK_EBI_EN_Pos) /*!<EBI clock enable */
|
||||
#define CLK_AHBCLK_SRAM_EN (0x1UL<<CLK_AHBCLK_SRAM_EN_Pos) /*!<SRAM Controller Clock Enable */
|
||||
#define CLK_AHBCLK_TICK_EN (0x1UL<<CLK_AHBCLK_TICK_EN_Pos) /*!<System Tick Clock Enable */
|
||||
|
||||
/********************* Bit definition of APBCLK register **********************/
|
||||
#define CLK_APBCLK_WDT_EN (0x1UL<<CLK_APBCLK_WDT_EN_Pos) /*!<Watchdog clock enable */
|
||||
#define CLK_APBCLK_RTC_EN (0x1UL<<CLK_APBCLK_RTC_EN_Pos) /*!<RTC clock enable */
|
||||
#define CLK_APBCLK_TMR0_EN (0x1UL<<CLK_APBCLK_TMR0_EN_Pos) /*!<Timer 0 clock enable */
|
||||
#define CLK_APBCLK_TMR1_EN (0x1UL<<CLK_APBCLK_TMR1_EN_Pos) /*!<Timer 1 clock enable */
|
||||
#define CLK_APBCLK_TMR2_EN (0x1UL<<CLK_APBCLK_TMR2_EN_Pos) /*!<Timer 2 clock enable */
|
||||
#define CLK_APBCLK_TMR3_EN (0x1UL<<CLK_APBCLK_TMR3_EN_Pos) /*!<Timer 3 clock enable */
|
||||
#define CLK_APBCLK_FDIV_EN (0x1UL<<CLK_APBCLK_FDIV_EN_Pos) /*!<Frequency Divider Output clock enable */
|
||||
#define CLK_APBCLK_SC2_EN (0x1UL<<CLK_APBCLK_SC2_EN_Pos) /*!<SmartCard 2 Clock Enable Control */
|
||||
#define CLK_APBCLK_I2C0_EN (0x1UL<<CLK_APBCLK_I2C0_EN_Pos) /*!<I2C 0 clock enable */
|
||||
#define CLK_APBCLK_I2C1_EN (0x1UL<<CLK_APBCLK_I2C1_EN_Pos) /*!<I2C 1 clock enable */
|
||||
#define CLK_APBCLK_SPI0_EN (0x1UL<<CLK_APBCLK_SPI0_EN_Pos) /*!<SPI 0 clock enable */
|
||||
#define CLK_APBCLK_SPI1_EN (0x1UL<<CLK_APBCLK_SPI1_EN_Pos) /*!<SPI 1 clock enable */
|
||||
#define CLK_APBCLK_SPI2_EN (0x1UL<<CLK_APBCLK_SPI2_EN_Pos) /*!<SPI 2 clock enable */
|
||||
#define CLK_APBCLK_UART0_EN (0x1UL<<CLK_APBCLK_UART0_EN_Pos) /*!<UART 0 clock enable */
|
||||
#define CLK_APBCLK_UART1_EN (0x1UL<<CLK_APBCLK_UART1_EN_Pos) /*!<UART 1 clock enable */
|
||||
#define CLK_APBCLK_PWM0_CH01_EN (0x1UL<<CLK_APBCLK_PWM0_CH01_EN_Pos) /*!<PWM0 Channel 0 and Channel 1 Clock Enable Control */
|
||||
#define CLK_APBCLK_PWM0_CH23_EN (0x1UL<<CLK_APBCLK_PWM0_CH23_EN_Pos) /*!<PWM0 Channel 2 and Channel 3 Clock Enable Control */
|
||||
#define CLK_APBCLK_PWM1_CH01_EN (0x1UL<<CLK_APBCLK_PWM1_CH01_EN_Pos) /*!<PWM1 Channel 0 and Channel 1 Clock Enable Control */
|
||||
#define CLK_APBCLK_PWM1_CH23_EN (0x1UL<<CLK_APBCLK_PWM1_CH23_EN_Pos) /*!<PWM1 Channel 2 and Channel 3 Clock Enable Control */
|
||||
#define CLK_APBCLK_DAC_EN (0x1UL<<CLK_APBCLK_DAC_EN_Pos) /*!<DAC Clock Enable Control */
|
||||
#define CLK_APBCLK_LCD_EN (0x1UL<<CLK_APBCLK_LCD_EN_Pos) /*!<LCD Clock Enable Control */
|
||||
#define CLK_APBCLK_USBD_EN (0x1UL<<CLK_APBCLK_USBD_EN_Pos) /*!<USB device clock enable */
|
||||
#define CLK_APBCLK_ADC_EN (0x1UL<<CLK_APBCLK_ADC_EN_Pos) /*!<ADC clock enable */
|
||||
#define CLK_APBCLK_I2S_EN (0x1UL<<CLK_APBCLK_I2S_EN_Pos) /*!<I2S clock enable */
|
||||
#define CLK_APBCLK_SC0_EN (0x1UL<<CLK_APBCLK_SC0_EN_Pos) /*!<SmartCard 0 Clock Enable Control */
|
||||
#define CLK_APBCLK_SC1_EN (0x1UL<<CLK_APBCLK_SC1_EN_Pos) /*!<SmartCard 1 Clock Enable Control */
|
||||
|
||||
/********************* Bit definition of CLKSTATUS register **********************/
|
||||
#define CLK_CLKSTATUS_HXT_STB (0x1UL<<CLK_CLKSTATUS_HXT_STB_Pos) /*!<External high speed crystal clock source stable flag */
|
||||
#define CLK_CLKSTATUS_LXT_STB (0x1UL<<CLK_CLKSTATUS_LXT_STB_Pos) /*!<External low speed crystal clock source stable flag */
|
||||
#define CLK_CLKSTATUS_PLL_STB (0x1UL<<CLK_CLKSTATUS_PLL_STB_Pos) /*!<Internal PLL clock source stable flag */
|
||||
#define CLK_CLKSTATUS_LIRC_STB (0x1UL<<CLK_CLKSTATUS_LIRC_STB_Pos) /*!<Internal low speed oscillator clock source stable flag */
|
||||
#define CLK_CLKSTATUS_HIRC_STB (0x1UL<<CLK_CLKSTATUS_HIRC_STB_Pos) /*!<Internal high speed oscillator clock source stable flag */
|
||||
#define CLK_CLKSTATUS_CLK_SW_FAIL (0x1UL<<CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!<Clock switch fail flag */
|
||||
|
||||
|
||||
/********************* Bit definition of CLKSEL0 register **********************/
|
||||
#define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from high speed crystal */
|
||||
#define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from low speed crystal */
|
||||
#define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from PLL */
|
||||
#define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from low speed oscillator */
|
||||
#define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from high speed oscillator */
|
||||
|
||||
/********************* Bit definition of CLKSEL1 register **********************/
|
||||
#define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) /*!<Select LCD clock source from low speed crystal */
|
||||
|
||||
#define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from low speed oscillator */
|
||||
#define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from external trigger */
|
||||
#define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from low speed oscillator */
|
||||
#define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from external trigger */
|
||||
#define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from HCLK */
|
||||
#define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from HCLK */
|
||||
#define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from high speed crystal */
|
||||
#define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from low speed crystal */
|
||||
#define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from PLL */
|
||||
#define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from high speed crystal */
|
||||
#define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from low speed crystal */
|
||||
#define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from PLL */
|
||||
#define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from high speed oscillator */
|
||||
|
||||
/********************* Bit definition of CLKSEL2 register **********************/
|
||||
#define CLK_CLKSEL2_SPI2_S_PLL (0x0UL<<CLK_CLKSEL2_SPI2_S_Pos) /*!<Select SPI2 clock source from PLL */
|
||||
#define CLK_CLKSEL2_SPI2_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI2_S_Pos) /*!<Select SPI2 clock source from HCLK */
|
||||
|
||||
#define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) /*!<Select SPI1 clock source from PLL */
|
||||
#define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) /*!<Select SPI1 clock source from HCLK */
|
||||
|
||||
#define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) /*!<Select SPI0 clock source from PLL */
|
||||
#define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) /*!<Select SPI0 clock source from HCLK */
|
||||
|
||||
#define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select SmartCard clock source from HXT */
|
||||
#define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select smartCard clock source from PLL */
|
||||
#define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select SmartCard clock source from HIRC */
|
||||
|
||||
#define CLK_CLKSEL2_I2S_S_HXT (0x0UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from HXT */
|
||||
#define CLK_CLKSEL2_I2S_S_PLL (0x1UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from PLL */
|
||||
#define CLK_CLKSEL2_I2S_S_HIRC (0x2UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from HIRC */
|
||||
|
||||
#define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from low speed oscillator */
|
||||
#define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from external trigger */
|
||||
#define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from low speed oscillator */
|
||||
#define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from external trigger */
|
||||
#define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL2_PWM1_CH01_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL2_PWM1_CH01_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL2_PWM1_CH01_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from HCLK */
|
||||
#define CLK_CLKSEL2_PWM1_CH01_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL2_PWM1_CH23_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from high speed crystal */
|
||||
#define CLK_CLKSEL2_PWM1_CH23_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from low speed crystal */
|
||||
#define CLK_CLKSEL2_PWM1_CH23_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from HCLK */
|
||||
#define CLK_CLKSEL2_PWM1_CH23_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from high speed oscillator */
|
||||
|
||||
#define CLK_CLKSEL2_FRQDIV_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HXT */
|
||||
#define CLK_CLKSEL2_FRQDIV_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from LXT */
|
||||
#define CLK_CLKSEL2_FRQDIV_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HCLK */
|
||||
#define CLK_CLKSEL2_FRQDIV_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HIRC */
|
||||
|
||||
/********************* Bit definition of CLKDIV0 register **********************/
|
||||
#define CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
|
||||
#define CLK_USB_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_USB_N_Pos) & CLK_CLKDIV0_USB_N_Msk) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
|
||||
#define CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) /*!< CLKDIV0 Setting for UART clock divider. It could be 1~16 */
|
||||
#define CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) /*!< CLKDIV0 Setting for ADC clock divider. It could be 1~256 */
|
||||
#define CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) /*!< CLKDIV0 Setting for SmartCard0 clock divider. It could be 1~16 */
|
||||
#define CLK_I2S_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_I2S_N_Pos) & CLK_CLKDIV0_I2S_N_Msk) /*!< CLKDIV0 Setting for I2S clock divider. It could be 1~16 */
|
||||
|
||||
/********************* Bit definition of CLKDIV1 register **********************/
|
||||
#define CLK_SC2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC2_N_Pos ) & CLK_CLKDIV1_SC2_N_Msk) /*!< CLKDIV1 Setting for SmartCard2 clock divider. It could be 1~16 */
|
||||
#define CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) /*!< CLKDIV1 Setting for SmartCard1 clock divider. It could be 1~16 */
|
||||
|
||||
/********************* Bit definition of SysTick register **********************/
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK (1) /*!< Setting systick clock source as external HCLK */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) /*!< Setting systick clock source as external HCLK/8 */
|
||||
|
||||
/********************* Bit definition of PLLCTL register **********************/
|
||||
#define CLK_PLLCTL_OUT_DV (0x1UL<<CLK_PLLCTL_OUT_DV_Pos) /*!<PLL Output Divider Control */
|
||||
#define CLK_PLLCTL_PD (0x1UL<<CLK_PLLCTL_PD_Pos) /*!<PLL Power down mode */
|
||||
#define CLK_PLLCTL_PLL_SRC_HIRC (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos) /*!<PLL clock source from high speed oscillator */
|
||||
#define CLK_PLLCTL_PLL_SRC_HXT (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos) /*!<PLL clock source from high speed crystal */
|
||||
|
||||
#define CLK_PLLCTL_NR_2 0x000 /*!< For PLL input divider is 2 */
|
||||
#define CLK_PLLCTL_NR_4 0x100 /*!< For PLL input divider is 4 */
|
||||
#define CLK_PLLCTL_NR_8 0x200 /*!< For PLL input divider is 8 */
|
||||
#define CLK_PLLCTL_NR_16 0x300 /*!< For PLL input divider is 16 */
|
||||
#define CLK_PLLCON_NF(x) ((x)-32) /*!< x must be constant and 32 <= x <= 95.) */
|
||||
|
||||
#define CLK_PLLCON_NO_1 0x0000UL /*!< For PLL output divider is 1 */
|
||||
#define CLK_PLLCON_NO_2 0x1000UL /*!< For PLL output divider is 2 */
|
||||
|
||||
#if (__HXT == 12000000)
|
||||
#define CLK_PLLCTL_120MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) /*!< Predefined PLLCTL setting for 120MHz PLL output with 12MHz X'tal */
|
||||
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 96MHz PLL output with 12MHz X'tal */
|
||||
#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz X'tal */
|
||||
#define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz X'tal */
|
||||
#define CLK_PLLCTL_42MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 42MHz PLL output with 12MHz X'tal */
|
||||
#else
|
||||
# error "The PLL pre-definitions are only valid when external crystal is 12MHz"
|
||||
#endif
|
||||
#define CLK_PLLCTL_120MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) /*!< Predefined PLLCTL setting for 120MHz PLL output with 12MHz IRC */
|
||||
#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 96MHz PLL output with 12MHz IRC */
|
||||
#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz IRC */
|
||||
#define CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz IRC */
|
||||
#define CLK_PLLCTL_42MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 42MHz PLL output with 12MHz IRC */
|
||||
|
||||
/********************* Bit definition of FRQDIV register **********************/
|
||||
#define CLK_FRQDIV_EN (0x1UL<<CLK_FRQDIV_FDIV_EN_Pos) /*!<Frequency divider enable bit */
|
||||
|
||||
/********************* Bit definition of WK_INTSTS register **********************/
|
||||
#define CLK_WK_INTSTS_IS (0x1UL<<CLK_WK_INTSTS_PD_WK_IS_Pos) /*!<Wake-up Interrupt Status in chip Power-down Mode */
|
||||
|
||||
/********************* Bit definition of MCLKO register **********************/
|
||||
#define CLK_MCLKO_MCLK_SEL_ISP_CLK (0x00<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output ISP_CLK */
|
||||
#define CLK_MCLKO_MCLK_SEL_HIRC (0x01<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HIRC clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_HXT (0x02<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HXT clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_LXT (0x03<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LXT clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_LIRC (0x04<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LIRC clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_PLLO (0x05<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PLL input */
|
||||
#define CLK_MCLKO_MCLK_SEL_PLLI (0x06<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PLL input */
|
||||
#define CLK_MCLKO_MCLK_SEL_SYSTICK (0x07<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output system tick */
|
||||
#define CLK_MCLKO_MCLK_SEL_HCLK (0x08<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HCLK clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_PCLK (0x0A<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PCLK clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_TMR0 (0x20<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR0 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_TMR1 (0x21<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR1 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_UART0 (0x22<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output UART0 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_USB (0x23<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output USB clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_ADC (0x24<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output ADC clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_WDT (0x25<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output WDT clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_PWM0CH01 (0x26<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM0CH01 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_PWM0CH23 (0x27<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM0CH23 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_LCD (0x29<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LCD clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_TMR2 (0x38<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR2 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_TMR3 (0x39<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR3 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_UART1 (0x3A<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output UART1 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_PWM1CH01 (0x3B<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM1CH01 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_PWM1CH23 (0x3C<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM1CH23 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_I2S (0x3D<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output I2S clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_SC0 (0x3E<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output SC0 clock */
|
||||
#define CLK_MCLKO_MCLK_SEL_SC1 (0x3F<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output SC1 clock */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* MODULE constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define MODULE_APBCLK(x) ((x >>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
|
||||
#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
|
||||
#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
|
||||
#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
|
||||
#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
|
||||
#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
|
||||
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
|
||||
#define NA MODULE_NoMsk /*!< Not Available */
|
||||
|
||||
#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK */
|
||||
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2*/
|
||||
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) /*!< CLKSEL mask offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
|
||||
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV */
|
||||
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
|
||||
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
|
||||
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */
|
||||
/*-------------------------------------------------------------------------------------------------------------------------------*/
|
||||
/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5) */
|
||||
/*-------------------------------------------------------------------------------------------------------------------------------*/
|
||||
#define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) /*!< TICK Module */
|
||||
#define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) /*!< SRAM Module */
|
||||
#define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) /*!< EBI Module */
|
||||
#define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) /*!< ISP Module */
|
||||
#define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) /*!< DMA Module */
|
||||
#define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) /*!< GPIO Module */
|
||||
|
||||
#define SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) /*!< SmartCard2 Module */
|
||||
#define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) /*!< SmartCard1 Module */
|
||||
#define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) /*!< SmartCard0 Module */
|
||||
#define I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) /*!< I2S Module */
|
||||
#define ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) /*!< ADC Module */
|
||||
#define USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) /*!< USBD Module */
|
||||
#define PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) /*!< PWM1 Channel2 and Channel3 Module */
|
||||
#define PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) /*!< PWM1 Channel0 and Channel1 Module */
|
||||
#define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) /*!< PWM0 Channel2 and Channel3 Module */
|
||||
#define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) /*!< PWM0 Channel0 and Channel1 Module */
|
||||
#define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) /*!< UART1 Module */
|
||||
#define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) /*!< UART0 Module */
|
||||
#define SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) /*!< SPI0 Module */
|
||||
#define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) /*!< SPI1 Module */
|
||||
#define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) /*!< SPI0 Module */
|
||||
#define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) /*!< I2C1 Module */
|
||||
#define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) /*!< I2C0 Module */
|
||||
#define FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) /*!< Frequency Divider0 Output Module */
|
||||
#define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) /*!< Timer3 Module */
|
||||
#define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) /*!< Timer2 Module */
|
||||
#define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) /*!< Timer1 Module */
|
||||
#define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) /*!< Timer0 Module */
|
||||
#define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) /*!< Real-Time-Clock Module */
|
||||
#define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) /*!< Watchdog Timer Module */
|
||||
#define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) /*!< LCD Module */
|
||||
#define DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) /*!< DAC Module */
|
||||
/*@}*/ /* end of group NANO100_CLK_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
|
||||
@{
|
||||
*/
|
||||
void CLK_DisableCKO(void);
|
||||
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
void CLK_PowerDown(void);
|
||||
void CLK_Idle(void);
|
||||
uint32_t CLK_GetHXTFreq(void);
|
||||
uint32_t CLK_GetLXTFreq(void);
|
||||
uint32_t CLK_GetHCLKFreq(void);
|
||||
uint32_t CLK_GetCPUFreq(void);
|
||||
uint32_t CLK_GetPLLClockFreq(void);
|
||||
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
|
||||
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
void CLK_EnableXtalRC(uint32_t u32ClkMask);
|
||||
void CLK_DisableXtalRC(uint32_t u32ClkMask);
|
||||
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
|
||||
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
|
||||
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
|
||||
void CLK_DisablePLL(void);
|
||||
int32_t CLK_SysTickDelay(uint32_t us);
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
||||
void CLK_DisableSysTick(void);
|
||||
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
|
||||
|
||||
/*@}*/ /* end of group NANO100_CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_CLK_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__CLK_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,159 @@
|
||||
/**************************************************************************//**
|
||||
* @file crc.h
|
||||
* @version V1.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 15/06/10 4:50p $
|
||||
* @brief Nano100 series CRC driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CRC_H__
|
||||
#define __CRC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_CRC_Driver CRC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_CRC_EXPORTED_CONSTANTS CRC Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CRC Polynomial Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CCITT 0x00000000UL /*!<CRC Polynomial Mode - CCITT */
|
||||
#define CRC_8 0x40000000UL /*!<CRC Polynomial Mode - CRC8 */
|
||||
#define CRC_16 0x80000000UL /*!<CRC Polynomial Mode - CRC16 */
|
||||
#define CRC_32 0xC0000000UL /*!<CRC Polynomial Mode - CRC32 */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Checksum, Write data Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CHECKSUM_COM 0x08000000UL /*!<CRC Checksum Complement */
|
||||
#define CRC_CHECKSUM_RVS 0x02000000UL /*!<CRC Checksum Reverse */
|
||||
#define CRC_WDATA_COM 0x04000000UL /*!<CRC Write Data Complement */
|
||||
#define CRC_WDATA_RVS 0x01000000UL /*!<CRC Write Data Reverse */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CPU Write Data Length Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CPU_WDATA_8 0x00000000UL /*!<CRC 8-bit CPU Write Data */
|
||||
#define CRC_CPU_WDATA_16 0x10000000UL /*!<CRC 16-bit CPU Write Data */
|
||||
#define CRC_CPU_WDATA_32 0x20000000UL /*!<CRC 32-bit CPU Write Data */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_CRC_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup NANO100_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable CRC Interrupt
|
||||
*
|
||||
* @param[in] u32Mask Interrupt mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro enable the interrupts.
|
||||
*/
|
||||
#define CRC_ENABLE_INT(u32Mask) (PDMACRC->DMAIER |= (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Disable CRC Interrupt
|
||||
*
|
||||
* @param[in] u32Mask Interrupt mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro disable the interrupts.
|
||||
*/
|
||||
#define CRC_DISABLE_INT(u32Mask) (PDMACRC->DMAIER &= ~(u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Get CRC Interrupt Flag
|
||||
*
|
||||
* @param[in] None
|
||||
*
|
||||
* @return Interrupt Flag
|
||||
*
|
||||
* @details This macro gets the interrupt flag.
|
||||
*/
|
||||
#define CRC_GET_INT_FLAG() ((uint32_t)(PDMACRC->DMAISR))
|
||||
|
||||
/**
|
||||
* @brief Clear CRC Interrupt Flag
|
||||
*
|
||||
* @param[in] u32Mask Interrupt mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clear the interrupt flag.
|
||||
*/
|
||||
#define CRC_CLR_INT_FLAG(u32Mask) (PDMACRC->DMAISR |= (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Set CRC seed value
|
||||
*
|
||||
* @param[in] u32Seed Seed value
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set seed value.
|
||||
*/
|
||||
#define CRC_SET_SEED(u32Seed) { PDMACRC->SEED = (u32Seed); PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk; }
|
||||
|
||||
/**
|
||||
* @brief Get CRC Seed value
|
||||
*
|
||||
* @param[in] None
|
||||
*
|
||||
* @return Seed Value
|
||||
*
|
||||
* @details This macro gets the seed value.
|
||||
*/
|
||||
#define CRC_GET_SEED() ((uint32_t)(PDMACRC->SEED))
|
||||
|
||||
/**
|
||||
* @brief CRC write data
|
||||
*
|
||||
* @param[in] u32Data write data
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro write CRC data.
|
||||
*/
|
||||
#define CRC_WRITE_DATA(u32Data) (PDMACRC->WDATA = (u32Data))
|
||||
|
||||
|
||||
/*********************************************************************/
|
||||
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
|
||||
void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount);
|
||||
uint32_t CRC_GetChecksum(void);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_CRC_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__CRC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,180 @@
|
||||
/**************************************************************************//**
|
||||
* @file dac.h
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 14/09/08 12:31p $
|
||||
* @brief NANO100 series DAC driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __DAC_H__
|
||||
#define __DAC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_DAC_Driver DAC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup NANO100_DAC_EXPORTED_CONSTANTS DAC Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define DAC_WRITE_DAT_TRIGGER (0UL << DAC_CTL_DACLSEL_Pos) ///< Write DACx_DAT trigger \hideinitializer
|
||||
#define DAC_PDMA_TRIGGER (1UL << DAC_CTL_DACLSEL_Pos) ///< PDMA trigger \hideinitializer
|
||||
#define DAC_TIMER0_TRIGGER (2UL << DAC_CTL_DACLSEL_Pos) ///< Timer 0 trigger \hideinitializer
|
||||
#define DAC_TIMER1_TRIGGER (3UL << DAC_CTL_DACLSEL_Pos) ///< Timer 1 trigger \hideinitializer
|
||||
#define DAC_TIMER2_TRIGGER (4UL << DAC_CTL_DACLSEL_Pos) ///< Timer 2 trigger \hideinitializer
|
||||
#define DAC_TIMER3_TRIGGER (5UL << DAC_CTL_DACLSEL_Pos) ///< Timer 3 trigger \hideinitializer
|
||||
|
||||
#define DAC_REFSEL_POWER (0UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to power \hideinitializer
|
||||
#define DAC_REFSEL_INT_VREF (1UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to Int_VREF \hideinitializer
|
||||
#define DAC_REFSEL_VREF (2UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to VREF \hideinitializer
|
||||
|
||||
/*@}*/ /* end of group NANO100_DAC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
|
||||
/** @addtogroup NANO100_DAC_EXPORTED_FUNCTIONS DAC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write data for conversion.
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @param[in] u32Ch DAC channel number, could be 0 or 1
|
||||
* @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_WRITE_DATA(dac, u32Ch, u32Data) do {\
|
||||
if(u32Ch) {\
|
||||
DAC->DATA1 = u32Data;\
|
||||
} else {\
|
||||
DAC->DATA0 = u32Data;\
|
||||
}\
|
||||
}while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable DAC group mode
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_ENABLE_GROUP_MODE(dac) (DAC->COMCTL |= DAC_COMCTL_DAC01GRP_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable DAC group mode
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_DISABLE_GROUP_MODE(dac) (DAC->COMCTL &= ~DAC_COMCTL_DAC01GRP_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get the busy state of DAC.
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @param[in] u32Ch DAC channel number, could be 0 or 1
|
||||
* @return If DAC is able to convert or not.
|
||||
* @retval 0 DAC is in idle state.
|
||||
* @retval 1 DAC is in busy state, or DAC is not in ready state.
|
||||
* @details If this macro returns 1, DAC is \b not in ready state. Ether DAC is busy or not in ready state.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_IS_BUSY(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_BUSY_Msk ? 1 : 0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the interrupt flag of specified channel.
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @param[in] u32Ch DAC channel number, could be 0 or 1
|
||||
* @return Returns the interrupt flag of selected channel.
|
||||
* @retval 0 DAC interrupt flag is not set.
|
||||
* @retval 1 DAC interrupt flag is set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_GET_INT_FLAG(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_DACIFG_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro clear the interrupt status bit of specified channel.
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @param[in] u32Ch DAC channel number, could be 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_CLR_INT_FLAG(dac, u32Ch) do {\
|
||||
if(u32Ch)\
|
||||
DAC->STS1 = DAC_STS_DACIFG_Msk;\
|
||||
else\
|
||||
DAC->STS0 = DAC_STS_DACIFG_Msk;\
|
||||
}while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the DAC reference voltage. This setting affects both DAC channel
|
||||
* @param[in] dac Base address of DAC module
|
||||
* @param[in] u32Ref The reference voltage selection. Valid values are:
|
||||
* - \ref DAC_REFSEL_POWER
|
||||
* - \ref DAC_REFSEL_INT_VREF
|
||||
* - \ref DAC_REFSEL_VREF
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_SET_REF_VOLTAGE(dac, u32Ref) (DAC->COMCTL = ((DAC->COMCTL) & ~DAC_COMCTL_REFSEL_Msk) | u32Ref)
|
||||
|
||||
/**
|
||||
* @brief This macro enable the interrupt of specified channel.
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @param[in] u32Ch DAC channel number, could be 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_ENABLE_INT(dac, u32Ch) do {\
|
||||
if(u32Ch)\
|
||||
DAC->CTL1 |= DAC_CTL_DACIE_Msk;\
|
||||
else\
|
||||
DAC->CTL0 |= DAC_CTL_DACIE_Msk;\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro disable the interrupt of specified channel.
|
||||
* @param[in] dac Base address of DAC module.
|
||||
* @param[in] u32Ch DAC channel number, could be 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define DAC_DISABLE_INT(dac, u32Ch) do {\
|
||||
if(u32Ch)\
|
||||
DAC->CTL1 &= ~DAC_CTL_DACIE_Msk;\
|
||||
else\
|
||||
DAC->CTL0 &= ~DAC_CTL_DACIE_Msk;\
|
||||
}while(0)
|
||||
|
||||
void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
|
||||
void DAC_Close(DAC_T *dac, uint32_t u32Ch);
|
||||
int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
|
||||
|
||||
/*@}*/ /* end of group NANO100_DAC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_DAC_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__DAC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,151 @@
|
||||
/**************************************************************************//**
|
||||
* @file ebi.h
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 14/09/30 4:21p $
|
||||
* @brief Nano100 Series Flash Memory Controller Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __EBI_H__
|
||||
#define __EBI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_EBI_Driver EBI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup NANO100_EBI_EXPORTED_CONSTANTS EBI Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define Base Address */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_BASE_ADDR 0x60000000 /*!< EBI base address */
|
||||
#define EBI_MAX_SIZE 0x20000 /*!< Maximum size of EBI bank */
|
||||
#define EBI_TIMEOUT_COUNT 0x10000 /*!< Time-out value */
|
||||
|
||||
/* Constants for EBI data bus width */
|
||||
#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
|
||||
#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* EBI MCLK divider */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_MCLKDIV_1 0 /*!< MCLK divided by 1 */
|
||||
#define EBI_MCLKDIV_2 1 /*!< MCLK divided by 2 */
|
||||
#define EBI_MCLKDIV_4 2 /*!< MCLK divided by 4 */
|
||||
#define EBI_MCLKDIV_8 3 /*!< MCLK divided by 8 */
|
||||
#define EBI_MCLKDIV_16 4 /*!< MCLK divided by 16 */
|
||||
#define EBI_MCLKDIV_32 5 /*!< MCLK divided by 32 */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* EBI timing setting */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_TIMING_FASTEST 0x0 /*!< EBI timing is the fastest */
|
||||
#define EBI_TIMING_VERYFAST 0x1 /*!< EBI timing is the very fast */
|
||||
#define EBI_TIMING_FAST 0x2 /*!< EBI timing is the fast */
|
||||
#define EBI_TIMING_NORMAL 0x3 /*!< EBI timing is the normal */
|
||||
#define EBI_TIMING_SLOW 0x4 /*!< EBI timing is the slow */
|
||||
#define EBI_TIMING_VERYSLOW 0x5 /*!< EBI timing is the very slow */
|
||||
#define EBI_TIMING_SLOWEST 0x6 /*!< EBI timing is the slowest */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_EBI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* EBI access macros */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Read one byte data from EBI.
|
||||
* @param[in] Addr EBI offset address.
|
||||
* @return Byte data read from EBI.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define EBI_READ_DATA8(Addr) *((volatile unsigned char *)(EBI_BASE_ADDR+Addr))
|
||||
|
||||
/**
|
||||
* @brief Write one byte data to EBI.
|
||||
* @param[in] Addr EBI offset address.
|
||||
* @param[in] Data Byte data to be written.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define EBI_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI_BASE_ADDR+Addr))=Data
|
||||
|
||||
/**
|
||||
* @brief Read a half-word data from EBI.
|
||||
* @param[in] Addr EBI offset address.
|
||||
* @return Half-word data read from EBI.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define EBI_READ_DATA16(Addr) *((volatile unsigned short *)(EBI_BASE_ADDR+Addr))
|
||||
|
||||
/**
|
||||
* @brief Write a half-word data to EBI.
|
||||
* @param[in] Addr EBI offset address.
|
||||
* @param[in] Data Half-word data to be written.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define EBI_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI_BASE_ADDR+Addr))=Data
|
||||
|
||||
/**
|
||||
* @brief Read a word data from EBI.
|
||||
* @param[in] Addr EBI offset address.
|
||||
* @return Word data read from EBI.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define EBI_READ_DATA32(Addr) *((volatile unsigned int *)(EBI_BASE_ADDR+Addr))
|
||||
|
||||
/**
|
||||
* @brief Write a word data to EBI.
|
||||
* @param[in] Addr EBI offset address.
|
||||
* @param[in] Data Word data to be written.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define EBI_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI_BASE_ADDR+Addr))=Data
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Functions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
|
||||
void EBI_Close(uint8_t u32Bank);
|
||||
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_EBI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_EBI_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __EBI_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,207 @@
|
||||
/**************************************************************************//**
|
||||
* @file fmc.h
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 15/06/12 2:11p $
|
||||
* @brief Nano100B Series Flash Memory Controller Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __FMC_H__
|
||||
#define __FMC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_FMC_Driver FMC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup NANO100_FMC_EXPORTED_CONSTANTS FMC Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define Base Address */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
|
||||
#define FMC_APROM_END 0x0001EC00UL /*!< APROM End Address */
|
||||
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
|
||||
#define FMC_LDROM_END 0x00101000UL /*!< LDROM End Address */
|
||||
#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration Address */
|
||||
|
||||
#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 bytes) */
|
||||
#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 Kbytes) */
|
||||
|
||||
#define FMC_TIMEOUT_READ ((SystemCoreClock/10)*2) /*!< Read command time-out 100 ms \hideinitializer */
|
||||
#define FMC_TIMEOUT_WRITE ((SystemCoreClock/10)*2) /*!< Write command time-out 100 ms \hideinitializer */
|
||||
#define FMC_TIMEOUT_ERASE ((SystemCoreClock/10)*4) /*!< Erase command time-out 200 ms \hideinitializer */
|
||||
#define FMC_TIMEOUT_CHKSUM (SystemCoreClock*2) /*!< Get checksum command time-out 2 s \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ISPCMD constant definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read flash word */
|
||||
#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Write flash word */
|
||||
#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
|
||||
#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
|
||||
#define FMC_ISPCMD_READ_PID 0x0C /*!< ISP Command: Read Product ID */
|
||||
#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
|
||||
#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Vector Page Remap */
|
||||
|
||||
#define IS_BOOT_FROM_APROM 0 /*!< Is booting from APROM */
|
||||
#define IS_BOOT_FROM_LDROM 1 /*!< Is booting from LDROM */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_FMC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macros */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief This macro selects booting from APROM.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_SET_APROM_BOOT() (FMC->ISPCON &= ~FMC_ISPCON_BS_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro selects booting from LDROM.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_SET_LDROM_BOOT() (FMC->ISPCON |= FMC_ISPCON_BS_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enables APROM update function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCON |= FMC_ISPCON_APUEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro disables APROM update function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enables User Configuration update function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro disables User Configuration update function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enables LDROM update function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro disables LDROM update function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enables ISP function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_ENABLE_ISP() (FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro disables ISP function.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_DISABLE_ISP() (FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro gets ISP fail flag value.
|
||||
* @param None
|
||||
* @return ISP fail flag value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_GET_FAIL_FLAG() ((FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro clears ISP fail flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define FMC_CLR_FAIL_FLAG() (FMC->ISPCON |= FMC_ISPCON_ISPFF_Msk)
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Functions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
extern void FMC_Close(void);
|
||||
extern int32_t FMC_Erase(uint32_t u32PageAddr);
|
||||
extern int32_t FMC_GetBootSource(void);
|
||||
extern void FMC_Open(void);
|
||||
extern uint32_t FMC_Read(uint32_t u32Addr);
|
||||
extern uint32_t FMC_ReadCID(void);
|
||||
extern uint32_t FMC_ReadPID(void);
|
||||
extern uint32_t FMC_ReadUCID(uint32_t u32Index);
|
||||
extern uint32_t FMC_ReadUID(uint32_t u32Index);
|
||||
extern uint32_t FMC_ReadDataFlashBaseAddr(void);
|
||||
extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
|
||||
extern uint32_t FMC_GetVectorPageAddr(void);
|
||||
extern int32_t FMC_Write(uint32_t u32Addr, uint32_t u32Data);
|
||||
extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
|
||||
extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_FMC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_FMC_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __FMC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,444 @@
|
||||
/**************************************************************************//**
|
||||
* @file gpio.h
|
||||
* @version V1.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 14/12/01 10:30a $
|
||||
* @brief Nano100 series GPIO driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_GPIO_Driver GPIO Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PMD Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_PMD_INPUT 0x0UL /*!< Input Mode */
|
||||
#define GPIO_PMD_OUTPUT 0x1UL /*!< Output Mode */
|
||||
#define GPIO_PMD_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* GPIO Interrupt Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
|
||||
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
|
||||
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
|
||||
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
|
||||
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* IMD Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */
|
||||
#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* DBNCECON Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_ICLK_ON 0x00000020UL /*!< DBNCECON setting for all IO pins edge detection circuit is always active after reset */
|
||||
#define GPIO_ICLK_OFF 0x00000000UL /*!< DBNCECON setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
|
||||
|
||||
#define GPIO_DBCLKSRC_IRC10K 0x00000010UL /*!< DBNCECON setting for de-bounce counter clock source is the internal 10 kHz */
|
||||
#define GPIO_DBCLKSRC_HCLK 0x00000000UL /*!< DBNCECON setting for de-bounce counter clock source is the internal HCLK */
|
||||
|
||||
#define GPIO_DBCLKSEL_1 0x00000000UL /*!< DBNCECON setting for sampling cycle = 1 clocks */
|
||||
#define GPIO_DBCLKSEL_2 0x00000001UL /*!< DBNCECON setting for sampling cycle = 2 clocks */
|
||||
#define GPIO_DBCLKSEL_4 0x00000002UL /*!< DBNCECON setting for sampling cycle = 4 clocks */
|
||||
#define GPIO_DBCLKSEL_8 0x00000003UL /*!< DBNCECON setting for sampling cycle = 8 clocks */
|
||||
#define GPIO_DBCLKSEL_16 0x00000004UL /*!< DBNCECON setting for sampling cycle = 16 clocks */
|
||||
#define GPIO_DBCLKSEL_32 0x00000005UL /*!< DBNCECON setting for sampling cycle = 32 clocks */
|
||||
#define GPIO_DBCLKSEL_64 0x00000006UL /*!< DBNCECON setting for sampling cycle = 64 clocks */
|
||||
#define GPIO_DBCLKSEL_128 0x00000007UL /*!< DBNCECON setting for sampling cycle = 128 clocks */
|
||||
#define GPIO_DBCLKSEL_256 0x00000008UL /*!< DBNCECON setting for sampling cycle = 256 clocks */
|
||||
#define GPIO_DBCLKSEL_512 0x00000009UL /*!< DBNCECON setting for sampling cycle = 512 clocks */
|
||||
#define GPIO_DBCLKSEL_1024 0x0000000AUL /*!< DBNCECON setting for sampling cycle = 1024 clocks */
|
||||
#define GPIO_DBCLKSEL_2048 0x0000000BUL /*!< DBNCECON setting for sampling cycle = 2048 clocks */
|
||||
#define GPIO_DBCLKSEL_4096 0x0000000CUL /*!< DBNCECON setting for sampling cycle = 4096 clocks */
|
||||
#define GPIO_DBCLKSEL_8192 0x0000000DUL /*!< DBNCECON setting for sampling cycle = 8192 clocks */
|
||||
#define GPIO_DBCLKSEL_16384 0x0000000EUL /*!< DBNCECON setting for sampling cycle = 16384 clocks */
|
||||
#define GPIO_DBCLKSEL_32768 0x0000000FUL /*!< DBNCECON setting for sampling cycle = 32768 clocks */
|
||||
|
||||
/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
|
||||
* Example 1:
|
||||
*
|
||||
* PA0 = 1;
|
||||
*
|
||||
* It is used to set PA0 to high;
|
||||
*
|
||||
* Example 2:
|
||||
*
|
||||
* if (PA0)
|
||||
* PA0 = 0;
|
||||
*
|
||||
* If PA0 pin status is high, then set PA0 data output to low.
|
||||
*/
|
||||
#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
|
||||
#define PA0 GPIO_PIN_ADDR(0, 0) /*!< Specify PA0 Pin Data Input/Output */
|
||||
#define PA1 GPIO_PIN_ADDR(0, 1) /*!< Specify PA1 Pin Data Input/Output */
|
||||
#define PA2 GPIO_PIN_ADDR(0, 2) /*!< Specify PA2 Pin Data Input/Output */
|
||||
#define PA3 GPIO_PIN_ADDR(0, 3) /*!< Specify PA3 Pin Data Input/Output */
|
||||
#define PA4 GPIO_PIN_ADDR(0, 4) /*!< Specify PA4 Pin Data Input/Output */
|
||||
#define PA5 GPIO_PIN_ADDR(0, 5) /*!< Specify PA5 Pin Data Input/Output */
|
||||
#define PA6 GPIO_PIN_ADDR(0, 6) /*!< Specify PA6 Pin Data Input/Output */
|
||||
#define PA7 GPIO_PIN_ADDR(0, 7) /*!< Specify PA7 Pin Data Input/Output */
|
||||
#define PA8 GPIO_PIN_ADDR(0, 8) /*!< Specify PA8 Pin Data Input/Output */
|
||||
#define PA9 GPIO_PIN_ADDR(0, 9) /*!< Specify PA9 Pin Data Input/Output */
|
||||
#define PA10 GPIO_PIN_ADDR(0, 10) /*!< Specify PA10 Pin Data Input/Output */
|
||||
#define PA11 GPIO_PIN_ADDR(0, 11) /*!< Specify PA11 Pin Data Input/Output */
|
||||
#define PA12 GPIO_PIN_ADDR(0, 12) /*!< Specify PA12 Pin Data Input/Output */
|
||||
#define PA13 GPIO_PIN_ADDR(0, 13) /*!< Specify PA13 Pin Data Input/Output */
|
||||
#define PA14 GPIO_PIN_ADDR(0, 14) /*!< Specify PA14 Pin Data Input/Output */
|
||||
#define PA15 GPIO_PIN_ADDR(0, 15) /*!< Specify PA15 Pin Data Input/Output */
|
||||
|
||||
#define PB0 GPIO_PIN_ADDR(1, 0) /*!< Specify PB0 Pin Data Input/Output */
|
||||
#define PB1 GPIO_PIN_ADDR(1, 1) /*!< Specify PB1 Pin Data Input/Output */
|
||||
#define PB2 GPIO_PIN_ADDR(1, 2) /*!< Specify PB2 Pin Data Input/Output */
|
||||
#define PB3 GPIO_PIN_ADDR(1, 3) /*!< Specify PB3 Pin Data Input/Output */
|
||||
#define PB4 GPIO_PIN_ADDR(1, 4) /*!< Specify PB4 Pin Data Input/Output */
|
||||
#define PB5 GPIO_PIN_ADDR(1, 5) /*!< Specify PB5 Pin Data Input/Output */
|
||||
#define PB6 GPIO_PIN_ADDR(1, 6) /*!< Specify PB6 Pin Data Input/Output */
|
||||
#define PB7 GPIO_PIN_ADDR(1, 7) /*!< Specify PB7 Pin Data Input/Output */
|
||||
#define PB8 GPIO_PIN_ADDR(1, 8) /*!< Specify PB8 Pin Data Input/Output */
|
||||
#define PB9 GPIO_PIN_ADDR(1, 9) /*!< Specify PB9 Pin Data Input/Output */
|
||||
#define PB10 GPIO_PIN_ADDR(1, 10) /*!< Specify PB10 Pin Data Input/Output */
|
||||
#define PB11 GPIO_PIN_ADDR(1, 11) /*!< Specify PB11 Pin Data Input/Output */
|
||||
#define PB12 GPIO_PIN_ADDR(1, 12) /*!< Specify PB12 Pin Data Input/Output */
|
||||
#define PB13 GPIO_PIN_ADDR(1, 13) /*!< Specify PB13 Pin Data Input/Output */
|
||||
#define PB14 GPIO_PIN_ADDR(1, 14) /*!< Specify PB14 Pin Data Input/Output */
|
||||
#define PB15 GPIO_PIN_ADDR(1, 15) /*!< Specify PB15 Pin Data Input/Output */
|
||||
|
||||
#define PC0 GPIO_PIN_ADDR(2, 0) /*!< Specify PC0 Pin Data Input/Output */
|
||||
#define PC1 GPIO_PIN_ADDR(2, 1) /*!< Specify PC1 Pin Data Input/Output */
|
||||
#define PC2 GPIO_PIN_ADDR(2, 2) /*!< Specify PC2 Pin Data Input/Output */
|
||||
#define PC3 GPIO_PIN_ADDR(2, 3) /*!< Specify PC3 Pin Data Input/Output */
|
||||
#define PC4 GPIO_PIN_ADDR(2, 4) /*!< Specify PC4 Pin Data Input/Output */
|
||||
#define PC5 GPIO_PIN_ADDR(2, 5) /*!< Specify PC5 Pin Data Input/Output */
|
||||
#define PC6 GPIO_PIN_ADDR(2, 6) /*!< Specify PC6 Pin Data Input/Output */
|
||||
#define PC7 GPIO_PIN_ADDR(2, 7) /*!< Specify PC7 Pin Data Input/Output */
|
||||
#define PC8 GPIO_PIN_ADDR(2, 8) /*!< Specify PC8 Pin Data Input/Output */
|
||||
#define PC9 GPIO_PIN_ADDR(2, 9) /*!< Specify PC9 Pin Data Input/Output */
|
||||
#define PC10 GPIO_PIN_ADDR(2, 10) /*!< Specify PC10 Pin Data Input/Output */
|
||||
#define PC11 GPIO_PIN_ADDR(2, 11) /*!< Specify PC11 Pin Data Input/Output */
|
||||
#define PC12 GPIO_PIN_ADDR(2, 12) /*!< Specify PC12 Pin Data Input/Output */
|
||||
#define PC13 GPIO_PIN_ADDR(2, 13) /*!< Specify PC13 Pin Data Input/Output */
|
||||
#define PC14 GPIO_PIN_ADDR(2, 14) /*!< Specify PC14 Pin Data Input/Output */
|
||||
#define PC15 GPIO_PIN_ADDR(2, 15) /*!< Specify PC15 Pin Data Input/Output */
|
||||
|
||||
#define PD0 GPIO_PIN_ADDR(3, 0) /*!< Specify PD0 Pin Data Input/Output */
|
||||
#define PD1 GPIO_PIN_ADDR(3, 1) /*!< Specify PD1 Pin Data Input/Output */
|
||||
#define PD2 GPIO_PIN_ADDR(3, 2) /*!< Specify PD2 Pin Data Input/Output */
|
||||
#define PD3 GPIO_PIN_ADDR(3, 3) /*!< Specify PD3 Pin Data Input/Output */
|
||||
#define PD4 GPIO_PIN_ADDR(3, 4) /*!< Specify PD4 Pin Data Input/Output */
|
||||
#define PD5 GPIO_PIN_ADDR(3, 5) /*!< Specify PD5 Pin Data Input/Output */
|
||||
#define PD6 GPIO_PIN_ADDR(3, 6) /*!< Specify PD6 Pin Data Input/Output */
|
||||
#define PD7 GPIO_PIN_ADDR(3, 7) /*!< Specify PD7 Pin Data Input/Output */
|
||||
#define PD8 GPIO_PIN_ADDR(3, 8) /*!< Specify PD8 Pin Data Input/Output */
|
||||
#define PD9 GPIO_PIN_ADDR(3, 9) /*!< Specify PD9 Pin Data Input/Output */
|
||||
#define PD10 GPIO_PIN_ADDR(3, 10) /*!< Specify PD10 Pin Data Input/Output */
|
||||
#define PD11 GPIO_PIN_ADDR(3, 11) /*!< Specify PD11 Pin Data Input/Output */
|
||||
#define PD12 GPIO_PIN_ADDR(3, 12) /*!< Specify PD12 Pin Data Input/Output */
|
||||
#define PD13 GPIO_PIN_ADDR(3, 13) /*!< Specify PD13 Pin Data Input/Output */
|
||||
#define PD14 GPIO_PIN_ADDR(3, 14) /*!< Specify PD14 Pin Data Input/Output */
|
||||
#define PD15 GPIO_PIN_ADDR(3, 15) /*!< Specify PD15 Pin Data Input/Output */
|
||||
|
||||
#define PE0 GPIO_PIN_ADDR(4, 0) /*!< Specify PE0 Pin Data Input/Output */
|
||||
#define PE1 GPIO_PIN_ADDR(4, 1) /*!< Specify PE1 Pin Data Input/Output */
|
||||
#define PE2 GPIO_PIN_ADDR(4, 2) /*!< Specify PE2 Pin Data Input/Output */
|
||||
#define PE3 GPIO_PIN_ADDR(4, 3) /*!< Specify PE3 Pin Data Input/Output */
|
||||
#define PE4 GPIO_PIN_ADDR(4, 4) /*!< Specify PE4 Pin Data Input/Output */
|
||||
#define PE5 GPIO_PIN_ADDR(4, 5) /*!< Specify PE5 Pin Data Input/Output */
|
||||
#define PE6 GPIO_PIN_ADDR(4, 6) /*!< Specify PE6 Pin Data Input/Output */
|
||||
#define PE7 GPIO_PIN_ADDR(4, 7) /*!< Specify PE7 Pin Data Input/Output */
|
||||
#define PE8 GPIO_PIN_ADDR(4, 8) /*!< Specify PE8 Pin Data Input/Output */
|
||||
#define PE9 GPIO_PIN_ADDR(4, 9) /*!< Specify PE9 Pin Data Input/Output */
|
||||
#define PE10 GPIO_PIN_ADDR(4, 10) /*!< Specify PE10 Pin Data Input/Output */
|
||||
#define PE11 GPIO_PIN_ADDR(4, 11) /*!< Specify PE11 Pin Data Input/Output */
|
||||
#define PE12 GPIO_PIN_ADDR(4, 12) /*!< Specify PE12 Pin Data Input/Output */
|
||||
#define PE13 GPIO_PIN_ADDR(4, 13) /*!< Specify PE13 Pin Data Input/Output */
|
||||
#define PE14 GPIO_PIN_ADDR(4, 14) /*!< Specify PE14 Pin Data Input/Output */
|
||||
#define PE15 GPIO_PIN_ADDR(4, 15) /*!< Specify PE15 Pin Data Input/Output */
|
||||
|
||||
#define PF0 GPIO_PIN_ADDR(5, 0) /*!< Specify PF0 Pin Data Input/Output */
|
||||
#define PF1 GPIO_PIN_ADDR(5, 1) /*!< Specify PF1 Pin Data Input/Output */
|
||||
#define PF2 GPIO_PIN_ADDR(5, 2) /*!< Specify PF2 Pin Data Input/Output */
|
||||
#define PF3 GPIO_PIN_ADDR(5, 3) /*!< Specify PF3 Pin Data Input/Output */
|
||||
#define PF4 GPIO_PIN_ADDR(5, 4) /*!< Specify PF4 Pin Data Input/Output */
|
||||
#define PF5 GPIO_PIN_ADDR(5, 5) /*!< Specify PF5 Pin Data Input/Output */
|
||||
|
||||
/*@}*/ /* end of group NANO100_GPIO_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup NANO100_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear GPIO Pin Interrupt Flag
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear the interrupt status of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_CLR_INT_FLAG(gpio, u32PinMask) ((gpio)->ISRC = u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Disable Pin De-bounce Function
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable the interrupt de-bounce function of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Enable Pin De-bounce Function
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable the interrupt de-bounce function of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN |= u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Disable I/O Digital Input Path
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable I/O digital input path of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->OFFD |= (u32PinMask << 16))
|
||||
|
||||
/**
|
||||
* @brief Enable I/O Digital Input Path
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable I/O digital input path of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->OFFD &= ~(u32PinMask << 16))
|
||||
|
||||
/**
|
||||
* @brief Disable I/O DOUT mask
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable I/O DOUT mask of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DMASK &= ~u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Enable I/O DOUT mask
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable I/O DOUT mask of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DMASK |= u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Get GPIO Pin Interrupt Flag
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @retval 0 No interrupt at specified GPIO pin
|
||||
* @retval 1 The specified GPIO pin generate an interrupt
|
||||
*
|
||||
* @details Get the interrupt status of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_GET_INT_FLAG(gpio, u32PinMask) ((gpio)->ISRC & u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Set De-bounce Sampling Cycle Time
|
||||
*
|
||||
* @param[in] u32ClkSrc The de-bounce counter clock source. It could be \ref GPIO_DBCLKSRC_HCLK or \ref GPIO_DBCLKSRC_IRC10K
|
||||
* @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be \n
|
||||
* \ref GPIO_DBCLKSEL_1, \ref GPIO_DBCLKSEL_2, \ref GPIO_DBCLKSEL_4, \ref GPIO_DBCLKSEL_8, \n
|
||||
* \ref GPIO_DBCLKSEL_16, \ref GPIO_DBCLKSEL_32, \ref GPIO_DBCLKSEL_64, \ref GPIO_DBCLKSEL_128, \n
|
||||
* \ref GPIO_DBCLKSEL_256, \ref GPIO_DBCLKSEL_512, \ref GPIO_DBCLKSEL_1024, \ref GPIO_DBCLKSEL_2048, \n
|
||||
* \ref GPIO_DBCLKSEL_4096, \ref GPIO_DBCLKSEL_8192, \ref GPIO_DBCLKSEL_16384, \ref GPIO_DBCLKSEL_32768
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
|
||||
* Example: \ref GPIO_SET_DEBOUNCE_TIME(\ref GPIO_DBCLKSRC_IRC10K, \ref GPIO_DBCLKSEL_4) \n
|
||||
* It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
|
||||
* Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
|
||||
* and system will sampling interrupt input once per 1600 us.
|
||||
*/
|
||||
#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBNCECON = (GP_DBNCECON_DBCLK_ON_Msk | u32ClkSrc | u32ClkSel))
|
||||
|
||||
/**
|
||||
* @brief Get GPIO Port IN Data
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
*
|
||||
* @retval The specified port data
|
||||
*
|
||||
* @details Get the PIN register of specified GPIO port.
|
||||
*/
|
||||
#define GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
|
||||
|
||||
/**
|
||||
* @brief Set GPIO Port OUT Data
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32Data GPIO port data
|
||||
*
|
||||
* @retval None
|
||||
*
|
||||
* @details Set the Data into specified GPIO port.
|
||||
*/
|
||||
#define GPIO_SET_OUT_DATA(gpio, u32Data) ((gpio)->DOUT = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Disable Pin Pull-up resistor Function
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable the Pull-up resistor function of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_PULL_UP(gpio, u32PinMask) ((gpio)->PUEN &= ~u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Enable Pin Pull-up resistor Function
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable the Pull-up resistor function of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_PULL_UP(gpio, u32PinMask) ((gpio)->PUEN |= u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Toggle Specified GPIO pin
|
||||
*
|
||||
* @param[in] u32Pin Pxy
|
||||
*
|
||||
* @retval None
|
||||
*
|
||||
* @details Toggle the specified GPIO pint.
|
||||
*/
|
||||
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
|
||||
|
||||
/**
|
||||
* @brief Enable External GPIO interrupt 0
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32Pin The pin of specified GPIO port
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
|
||||
* \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_EnableEINT0 GPIO_EnableInt
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable External GPIO interrupt 0
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_DisableEINT0 GPIO_DisableInt
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable External GPIO interrupt 1
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32Pin The pin of specified GPIO port
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
|
||||
* \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_EnableEINT1 GPIO_EnableInt
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable External GPIO interrupt 1
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
|
||||
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_DisableEINT1 GPIO_DisableInt
|
||||
|
||||
|
||||
void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode);
|
||||
void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs);
|
||||
void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_GPIO_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_GPIO_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__GPIO_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,194 @@
|
||||
/****************************************************************************//**
|
||||
* @file i2c.h
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 15/06/05 5:06p $
|
||||
* @brief Nano100 series I2C driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_I2C_Driver I2C Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_I2C_EXPORTED_CONSTANTS I2C Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define I2C_STA 0x08 /*!< I2C START bit value */
|
||||
#define I2C_STO 0x04 /*!< I2C STOP bit value*/
|
||||
#define I2C_SI 0x10 /*!< I2C SI bit value */
|
||||
#define I2C_AA 0x02 /*!< I2C ACK bit value */
|
||||
|
||||
#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */
|
||||
#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */
|
||||
|
||||
/*@}*/ /* end of group NANO100_I2C_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro sets the I2C control register at one time.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8Ctrl is the register value of I2C control register.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ( (i2c)->CON = ((i2c)->CON & ~0x1e) | u8Ctrl )
|
||||
|
||||
/**
|
||||
* @brief This macro only set START bit to the control register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_START(i2c) ( (i2c)->CON = ((i2c)->CON & ~I2C_CON_I2C_STS_Msk) | I2C_CON_START_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro only set STOP bit to the control register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return 0 success
|
||||
* @return -1 time out
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE int32_t I2C_STOP(I2C_T *i2c)
|
||||
{
|
||||
int32_t tout = (SystemCoreClock / 10);
|
||||
|
||||
i2c->CON |= (I2C_CON_I2C_STS_Msk | I2C_CON_STOP_Msk);
|
||||
while((i2c->CON & I2C_CON_STOP_Msk) && (tout-- > 0));
|
||||
if (i2c->CON & I2C_CON_STOP_Msk)
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This macro will return when I2C module is ready.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return 0 success
|
||||
* @return -1 time out
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE int32_t I2C_WAIT_READY(I2C_T *i2c)
|
||||
{
|
||||
int32_t tout = (SystemCoreClock / 10);
|
||||
|
||||
while(!(i2c->INTSTS & I2C_INTSTS_INTSTS_Msk) && (tout-- > 0));
|
||||
if (!(i2c->INTSTS & I2C_INTSTS_INTSTS_Msk))
|
||||
return -1;
|
||||
i2c->INTSTS |= I2C_INTSTS_INTSTS_Msk;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This macro returns the data stored in data register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Data.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_DATA(i2c) ( (i2c)->DATA )
|
||||
|
||||
/**
|
||||
* @brief This macro writes the data to data register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8Data is the data which will be write to data register of I2C module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SET_DATA(i2c, u8Data) ( (i2c)->DATA = u8Data )
|
||||
|
||||
/**
|
||||
* @brief This macro returns the status of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
|
||||
|
||||
/**
|
||||
* @brief This macro returns timeout flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
* @retval 0 Flag is not set.
|
||||
* @retval 1 Flag is set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->INTSTS & I2C_INTSTS_TIF_Msk) == I2C_INTSTS_TIF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief This macro clears timeout flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_CLEAR_TIMEOUT_FLAG(i2c) ( (i2c)->INTSTS |= I2C_INTSTS_TIF_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro returns wakeup flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
* @retval 0 Flag is not set.
|
||||
* @retval 1 Flag is set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKUPSTS & I2C_WKUPSTS_WKUPIF_Msk) == I2C_WKUPSTS_WKUPIF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief This macro clears wakeup flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->WKUPSTS |= I2C_WKUPSTS_WKUPIF_Msk )
|
||||
|
||||
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
|
||||
void I2C_Close(I2C_T *i2c);
|
||||
void I2C_ClearTimeoutFlag(I2C_T *i2c);
|
||||
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
|
||||
void I2C_DisableInt(I2C_T *i2c);
|
||||
void I2C_EnableInt(I2C_T *i2c);
|
||||
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
|
||||
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
|
||||
uint32_t I2C_GetIntFlag(I2C_T *i2c);
|
||||
void I2C_ClearIntFlag(I2C_T *i2c);
|
||||
uint32_t I2C_GetStatus(I2C_T *i2c);
|
||||
uint32_t I2C_GetData(I2C_T *i2c);
|
||||
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
|
||||
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
|
||||
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
|
||||
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
|
||||
void I2C_DisableTimeout(I2C_T *i2c);
|
||||
void I2C_EnableWakeup(I2C_T *i2c);
|
||||
void I2C_DisableWakeup(I2C_T *i2c);
|
||||
|
||||
/*@}*/ /* end of group NANO100_I2C_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_I2C_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__I2C_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,297 @@
|
||||
/**************************************************************************//**
|
||||
* @file i2s.h
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 15/06/08 4:59p $
|
||||
* @brief Nano100 series I2S driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __I2S_H__
|
||||
#define __I2S_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_I2S_Driver I2S Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_I2S_EXPORTED_CONSTANTS I2S Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define I2S_DATABIT_8 (0 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 8-bit */
|
||||
#define I2S_DATABIT_16 (1 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 16-bit */
|
||||
#define I2S_DATABIT_24 (2 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 24-bit */
|
||||
#define I2S_DATABIT_32 (3 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 32-bit */
|
||||
|
||||
/* Audio Format */
|
||||
#define I2S_MONO I2S_CTRL_MONO_Msk /*!< Mono channel */
|
||||
#define I2S_STEREO 0 /*!< Stereo channel */
|
||||
|
||||
/* I2S Data Format */
|
||||
#define I2S_FORMAT_MSB I2S_CTRL_FORMAT_Msk /*!< MSB data format */
|
||||
#define I2S_FORMAT_I2S 0 /*!< I2S data format */
|
||||
|
||||
/* I2S Interface */
|
||||
#define I2S_I2S 0 /*!< I2S interface is selected */
|
||||
|
||||
/* I2S Operation mode */
|
||||
#define I2S_MODE_SLAVE I2S_CTRL_SLAVE_Msk /*!< As slave mode */
|
||||
#define I2S_MODE_MASTER 0 /*!< As master mode */
|
||||
|
||||
/* I2S FIFO Threshold */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 1 word */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 2 words */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 3 words */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 4 words */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 5 words */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 6 words */
|
||||
#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 7 words */
|
||||
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 2 words */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 3 words */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 4 words */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 5 words */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 6 words */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 7 words */
|
||||
#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 8 words */
|
||||
|
||||
/* I2S Record Channel */
|
||||
#define I2S_MONO_RIGHT 0 /*!< Record mono right channel */
|
||||
#define I2S_MONO_LEFT I2S_CTRL_RXLCH_Msk /*!< Record mono left channel */
|
||||
|
||||
/* I2S Channel */
|
||||
#define I2S_RIGHT 0 /*!< Select right channel */
|
||||
#define I2S_LEFT 1 /*!< Select left channel */
|
||||
|
||||
/*@}*/ /* end of group NANO100_I2S_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup NANO100_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
|
||||
@{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable zero cross detect function.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @param[in] u32ChMask is the mask for left or right channel. Valid values are:
|
||||
* - \ref I2S_RIGHT
|
||||
* - \ref I2S_LEFT
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
|
||||
{
|
||||
if(u32ChMask == I2S_RIGHT)
|
||||
i2s->CTRL |= I2S_CTRL_RCHZCEN_Msk;
|
||||
else
|
||||
i2s->CTRL |= I2S_CTRL_LCHZCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable zero cross detect function.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @param[in] u32ChMask is the mask for left or right channel. Valid values are:
|
||||
* - \ref I2S_RIGHT
|
||||
* - \ref I2S_LEFT
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
|
||||
{
|
||||
if(u32ChMask == I2S_RIGHT)
|
||||
i2s->CTRL &= ~I2S_CTRL_RCHZCEN_Msk;
|
||||
else
|
||||
i2s->CTRL &= ~I2S_CTRL_LCHZCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTRL |= I2S_CTRL_TXDMA_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_TXDMA_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTRL |= I2S_CTRL_RXDMA_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_RXDMA_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable I2S Tx function .
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_ENABLE_TX(i2s) ( (i2s)->CTRL |= I2S_CTRL_TXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable I2S Tx function .
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_DISABLE_TX(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_TXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable I2S Rx function .
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_ENABLE_RX(i2s) ( (i2s)->CTRL |= I2S_CTRL_RXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable I2S Rx function .
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_DISABLE_RX(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_RXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable Tx Mute function .
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTRL |= I2S_CTRL_MUTE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable Tx Mute function .
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_MUTE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTRL |= I2S_CTRL_CLR_TXFIFO_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTRL |= I2S_CTRL_CLR_RXFIFO_Msk )
|
||||
|
||||
/**
|
||||
* @brief This function sets the recording source channel when mono mode is used.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @param[in] u32Ch left or right channel. Valid values are:
|
||||
* - \ref I2S_MONO_LEFT
|
||||
* - \ref I2S_MONO_RIGHT
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_SET_MONO_RX_CHANNEL(i2s, u32Ch) ( u32Ch == I2S_MONO_LEFT ? ((i2s)->CTRL |= I2S_CTRL_RXLCH_Msk) : ((i2s)->CTRL &= ~I2S_CTRL_RXLCH_Msk) )
|
||||
|
||||
/**
|
||||
* @brief Write data to I2S Tx FIFO.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @param[in] u32Data The data written to FIFO.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = u32Data )
|
||||
|
||||
/**
|
||||
* @brief Read Rx FIFO.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return Data in Rx FIFO.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
|
||||
|
||||
/**
|
||||
* @brief This function gets the interrupt flag according to the mask parameter.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @param[in] u32Mask is the mask for the all interrupt flags.
|
||||
* @return The masked bit value of interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_GET_INT_FLAG(i2s, u32Mask) ((i2s)->STATUS & (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief This function clears the interrupt flag according to the mask parameter.
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @param[in] u32Mask is the mask for the all interrupt flags.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= (u32Mask) )
|
||||
|
||||
/**
|
||||
* @brief Get transmit FIFO level
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return FIFO level
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_GET_TX_FIFO_LEVEL(i2s) ((((i2s)->STATUS & I2S_STATUS_TX_LEVEL_Msk) >> I2S_STATUS_TX_LEVEL_Pos) & 0xF)
|
||||
|
||||
/**
|
||||
* @brief Get receive FIFO level
|
||||
* @param[in] i2s is the base address of I2S module.
|
||||
* @return FIFO level
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2S_GET_RX_FIFO_LEVEL(i2s) ((((i2s)->STATUS & I2S_STATUS_RX_LEVEL_Msk) >> I2S_STATUS_RX_LEVEL_Pos) & 0xF)
|
||||
|
||||
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface);
|
||||
void I2S_Close(I2S_T *i2s);
|
||||
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
|
||||
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
|
||||
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
|
||||
void I2S_DisableMCLK(I2S_T *i2s);
|
||||
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||
|
||||
/*@}*/ /* end of group NANO100_I2S_EXPORTED_FUNCTIONS */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_I2S_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__I2S_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
|
||||
@@ -0,0 +1,227 @@
|
||||
/****************************************************************************//**
|
||||
* @file lcd.h
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 15/06/26 1:30p $
|
||||
* @brief Nano100 series I2C driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __LCD_H__
|
||||
#define __LCD_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
//#include <stdbool.h>
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_LCD_Driver LCD Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup NANO100_LCD_EXPORTED_CONSTANTS LCD Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/// @cond
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macro, type and constant definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/// @endcond
|
||||
|
||||
#define LCD_FREQ_DIV32 ((uint32_t) 0x00000000) /*!< Clock source (32 or 10KHz) divide by 32 */
|
||||
#define LCD_FREQ_DIV64 ((uint32_t) 0x00000010) /*!< Clock source (32 or 10KHz) divide by 64 */
|
||||
#define LCD_FREQ_DIV96 ((uint32_t) 0x00000020) /*!< Clock source (32 or 10KHz) divide by 96 */
|
||||
#define LCD_FREQ_DIV128 ((uint32_t) 0x00000030) /*!< Clock source (32 or 10KHz) divide by 128 */
|
||||
#define LCD_FREQ_DIV192 ((uint32_t) 0x00000040) /*!< Clock source (32 or 10KHz) divide by 192 */
|
||||
#define LCD_FREQ_DIV256 ((uint32_t) 0x00000050) /*!< Clock source (32 or 10KHz) divide by 256 */
|
||||
#define LCD_FREQ_DIV384 ((uint32_t) 0x00000060) /*!< Clock source (32 or 10KHz) divide by 384 */
|
||||
#define LCD_FREQ_DIV512 ((uint32_t) 0x00000070) /*!< Clock source (32 or 10KHz) divide by 512 */
|
||||
|
||||
#define LCD_MUX_STATIC ((uint32_t) 0x00000000) /*!< Static multiplexing */
|
||||
#define LCD_MUX_ONE_SECOND ((uint32_t) 0x00000002) /*!< Duplex multiplexing */
|
||||
#define LCD_MUX_ONE_THIRD ((uint32_t) 0x00000004) /*!< Triplex multiplexing */
|
||||
#define LCD_MUX_ONE_FOURTH ((uint32_t) 0x00000006) /*!< Quadruplex multiplexing */
|
||||
#define LCD_MUX_ONE_FIFTH ((uint32_t) 0x00000008) /*!< 1/5 duty */
|
||||
#define LCD_MUX_ONE_SIXTH ((uint32_t) 0x0000000A) /*!< 1/6 duty */
|
||||
|
||||
#define LCD_BIAS_STATIC ((uint32_t) 0x00000000) /*!< Static bias */
|
||||
#define LCD_BIAS_HALF ((uint32_t) 0x00000002) /*!< 1/2 bias */
|
||||
#define LCD_BIAS_THIRD ((uint32_t) 0x00000004) /*!< 1/3 bias */
|
||||
|
||||
#define LCD_CPUMP_DIV1 ((uint32_t) 0x00000000) /*!< Clock source (32 or 10KHz) divide by 1 and is used by analog component */
|
||||
#define LCD_CPUMP_DIV2 ((uint32_t) 0x00000800) /*!< Clock source (32 or 10KHz) divide by 2 */
|
||||
#define LCD_CPUMP_DIV4 ((uint32_t) 0x00001000) /*!< Clock source (32 or 10KHz) divide by 4 */
|
||||
#define LCD_CPUMP_DIV8 ((uint32_t) 0x00001800) /*!< Clock source (32 or 10KHz) divide by 8 */
|
||||
#define LCD_CPUMP_DIV16 ((uint32_t) 0x00002000) /*!< Clock source (32 or 10KHz) divide by 16 */
|
||||
#define LCD_CPUMP_DIV32 ((uint32_t) 0x00002800) /*!< Clock source (32 or 10KHz) divide by 32 */
|
||||
#define LCD_CPUMP_DIV64 ((uint32_t) 0x00003000) /*!< Clock source (32 or 10KHz) divide by 64 */
|
||||
#define LCD_CPUMP_DIV128 ((uint32_t) 0x00003800) /*!< Clock source (32 or 10KHz) divide by 128 */
|
||||
|
||||
#define LCD_CPVOl_2_7V ((uint32_t) 0x00000000) /*!< Set charge pump voltage to 2.7 V */
|
||||
#define LCD_CPVOl_2_8V ((uint32_t) 0x00000100) /*!< Set charge pump voltage to 2.8 V */
|
||||
#define LCD_CPVOl_2_9V ((uint32_t) 0x00000200) /*!< Set charge pump voltage to 2.9 V */
|
||||
#define LCD_CPVOl_3V ((uint32_t) 0x00000300) /*!< Set charge pump voltage to 3 V */
|
||||
#define LCD_CPVOl_3_1V ((uint32_t) 0x00000400) /*!< Set charge pump voltage to 3.1 V */
|
||||
#define LCD_CPVOl_3_2V ((uint32_t) 0x00000500) /*!< Set charge pump voltage to 3.2 V */
|
||||
#define LCD_CPVOl_3_3V ((uint32_t) 0x00000600) /*!< Set charge pump voltage to 3.3 V */
|
||||
#define LCD_CPVOl_3_4V ((uint32_t) 0x00000700) /*!< Set charge pump voltage to 3.4 V */
|
||||
|
||||
#define LCD_FCPRESC_DIV1 ((uint32_t) 0x00000000) /*!< Set pre-scale divider value to 1 */
|
||||
#define LCD_FCPRESC_DIV2 ((uint32_t) 0x00000004) /*!< Set pre-scale divider value to 2 */
|
||||
#define LCD_FCPRESC_DIV4 ((uint32_t) 0x00000008) /*!< Set pre-scale divider value to 4 */
|
||||
#define LCD_FCPRESC_DIV8 ((uint32_t) 0x0000000C) /*!< Set pre-scale divider value to 8 */
|
||||
|
||||
#define LCD_FRAMECOUNT_INT ((uint32_t) 0x00000001) /*!< Indicate frame count interrupt */
|
||||
#define LCD_POWERDOWN_INT ((uint32_t) 0x00000002) /*!< Indicate power down interrupt */
|
||||
#define LCD_ALL_INT ((uint32_t) 0x00000003) /*!< Indicate frame count & power down interrupt */
|
||||
|
||||
#define ERR_LCD_CAL_BLINK_FAIL 0xFFFF0000 /*!< Specifies that overflow to calculate the blinking frequency */
|
||||
|
||||
/*@}*/ /* end of group NANO100_LCD_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_LCD_EXPORTED_STRUCTS LCD Exported Structs
|
||||
@{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LCD_C_TYPE = 0, /*!< Select LCD C-Type */
|
||||
LCD_EXTERNAL_R_TYPE = 1, /*!< Select LCD External R-Type */
|
||||
LCD_INTERNAL_R_TYPE = 2, /*!< Select LCD Internal R-Type */
|
||||
LCD_EXTERNAL_C_TYPE = 3 /*!< Select LCD External C-Type */
|
||||
} LCD_PanelType;
|
||||
|
||||
/*@}*/ /* end of group NANO100_LCD_EXPORTED_STRUCTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_LCD_EXPORTED_FUNCTIONS LCD Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get LCD Power Down interrupt flag.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return LCD Power Down interrupt Flag.
|
||||
*/
|
||||
#define LCD_GET_PD_INT_FLAG() ((LCD->FCSTS & LCD_FCSTS_PDSTS_Msk) >> LCD_FCSTS_PDSTS_Pos)
|
||||
|
||||
/**
|
||||
* @brief Clear LCD Power Down interrupt flag.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
#define LCD_CLR_PD_INT_FLAG() (LCD->FCSTS = LCD_FCSTS_PDSTS_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get LCD Frame Count interrupt flag.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return LCD Frame Count interrupt Flag.
|
||||
*/
|
||||
#define LCD_GET_FRAME_CNT_INT_FLAG() ((LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) >> LCD_FCSTS_FCSTS_Pos)
|
||||
|
||||
/**
|
||||
* @brief Clear LCD Frame Count interrupt flag.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
#define LCD_CLR_FRAME_CNT_INT_FLAG() (LCD->FCSTS = LCD_FCSTS_FCSTS_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable LCD Power Down Display function.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
#define LCD_ENABLE_PD_DISPLAY() (LCD->CTL |= LCD_CTL_PDDISP_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable LCD Power Down Display function.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
#define LCD_DISABLE_PD_DISPLAY() (LCD->CTL &= ~LCD_CTL_PDDISP_EN_Msk)
|
||||
|
||||
uint32_t LCD_EnableFrameCounter(uint32_t u32Count);
|
||||
void LCD_DisableFrameCounter(void);
|
||||
uint32_t LCD_EnableBlink(uint32_t u32ms);
|
||||
void LCD_DisableBlink(void);
|
||||
void LCD_EnableInt(uint32_t IntSrc);
|
||||
void LCD_DisableInt(uint32_t IntSrc);
|
||||
uint32_t LCD_Open(uint32_t u32DrivingType, uint32_t u32ComNum, uint32_t u32BiasLevel, uint32_t u32FramerateDiv, uint32_t u32DrivingVol);
|
||||
void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag);
|
||||
void LCD_SetAllPixels(uint32_t u32OnOff);
|
||||
void LCD_Close(void);
|
||||
|
||||
/**
|
||||
* @brief Enable LCD controller
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
static __INLINE void LCD_EnableDisplay(void)
|
||||
{
|
||||
/* Enable LCD */
|
||||
LCD->CTL |= LCD_CTL_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable LCD controller
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
static __INLINE void LCD_DisableDisplay(void)
|
||||
{
|
||||
/* Enable LCD */
|
||||
LCD->CTL &= ~LCD_CTL_EN_Msk;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_LCD_EXPORTED_FUNCTIONS */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_LCD_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LCD_H__ */
|
||||
|
||||
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
/**************************************************************************//**
|
||||
* @file pdma.h
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 15/06/10 4:52p $
|
||||
* @brief Nano100 series PDMA driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __PDMA_H__
|
||||
#define __PDMA_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_PDMA_Driver PDMA Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Data Width Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_WIDTH_8 0x00080000UL /*!<DMA Transfer Width 8-bit */
|
||||
#define PDMA_WIDTH_16 0x00100000UL /*!<DMA Transfer Width 16-bit */
|
||||
#define PDMA_WIDTH_32 0x00000000UL /*!<DMA Transfer Width 32-bit */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Address Attribute Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment */
|
||||
#define PDMA_SAR_FIX 0x00000020UL /*!<DMA SAR fix address */
|
||||
#define PDMA_SAR_WRA 0x00000030UL /*!<DMA SAR wrap around */
|
||||
#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment */
|
||||
#define PDMA_DAR_FIX 0x00000080UL /*!<DMA DAR fix address */
|
||||
#define PDMA_DAR_WRA 0x000000C0UL /*!<DMA DAR wrap around */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Peripheral Transfer Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_SPI0_TX 0x00000000UL /*!<DMA Connect to SPI0 TX */
|
||||
#define PDMA_SPI1_TX 0x00000001UL /*!<DMA Connect to SPI1 TX */
|
||||
#define PDMA_UART0_TX 0x00000002UL /*!<DMA Connect to UART0 TX */
|
||||
#define PDMA_UART1_TX 0x00000003UL /*!<DMA Connect to UART1 TX */
|
||||
#define PDMA_USB_TX 0x00000004UL /*!<DMA Connect to USB TX */
|
||||
#define PDMA_I2S_TX 0x00000005UL /*!<DMA Connect to I2S TX */
|
||||
#define PDMA_DAC0_TX 0x00000006UL /*!<DMA Connect to DAC0 TX */
|
||||
#define PDMA_DAC1_TX 0x00000007UL /*!<DMA Connect to DAC1 TX */
|
||||
#define PDMA_SPI2_TX 0x00000008UL /*!<DMA Connect to SPI2 TX */
|
||||
#define PDMA_TMR0 0x00000009UL /*!<DMA Connect to TMR0 */
|
||||
#define PDMA_TMR1 0x0000000AUL /*!<DMA Connect to TMR1 */
|
||||
#define PDMA_TMR2 0x0000000BUL /*!<DMA Connect to TMR2 */
|
||||
#define PDMA_TMR3 0x0000000CUL /*!<DMA Connect to TMR3 */
|
||||
|
||||
#define PDMA_SPI0_RX 0x00000010UL /*!<DMA Connect to SPI0 RX */
|
||||
#define PDMA_SPI1_RX 0x00000011UL /*!<DMA Connect to SPI1 RX */
|
||||
#define PDMA_UART0_RX 0x00000012UL /*!<DMA Connect to UART0 RX */
|
||||
#define PDMA_UART1_RX 0x00000013UL /*!<DMA Connect to UART1 RX */
|
||||
#define PDMA_USB_RX 0x00000014UL /*!<DMA Connect to USB RX */
|
||||
#define PDMA_I2S_RX 0x00000015UL /*!<DMA Connect to I2S RX */
|
||||
#define PDMA_ADC 0x00000016UL /*!<DMA Connect to I2S1 RX */
|
||||
#define PDMA_SPI2_RX 0x00000018UL /*!<DMA Connect to SPI2 RX */
|
||||
#define PDMA_PWM0_CH0 0x00000019UL /*!<DMA Connect to PWM0 CH0 */
|
||||
#define PDMA_PWM0_CH2 0x0000001AUL /*!<DMA Connect to PWM0 CH2 */
|
||||
#define PDMA_PWM1_CH0 0x0000001BUL /*!<DMA Connect to PWM1 CH0 */
|
||||
#define PDMA_PWM1_CH2 0x0000001CUL /*!<DMA Connect to PWM1 CH2 */
|
||||
#define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory */
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_PDMA_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup NANO100_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get PDMA Interrupt Status
|
||||
*
|
||||
* @param[in] None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro gets the interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMAGCR->GCRISR))
|
||||
|
||||
/**
|
||||
* @brief Get PDMA Channel Interrupt Status
|
||||
*
|
||||
* @param[in] u32Ch Selected DMA channel
|
||||
*
|
||||
* @return Interrupt Status
|
||||
*
|
||||
* @details This macro gets the channel interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))))
|
||||
|
||||
/**
|
||||
* @brief Clear PDMA Channel Interrupt Flag
|
||||
*
|
||||
* @param[in] u32Ch Selected DMA channel
|
||||
* @param[in] u32Mask Interrupt Mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clear the channel interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Check Channel Status
|
||||
*
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @return 0 = idle
|
||||
* @return 1 = busy
|
||||
*
|
||||
* @details Check the selected channel is busy or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CSR +(uint32_t)((u32Ch-1)*0x100)))&PDMA_CSR_TRIG_EN_Msk)? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Set Source Address
|
||||
*
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Addr The selected address
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel source address.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
|
||||
|
||||
/**
|
||||
* @brief Set Destination Address
|
||||
*
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Addr The selected address
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel destination address.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
|
||||
|
||||
/**
|
||||
* @brief Set Transfer Count
|
||||
*
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Count Transfer Count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel transfer count.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) \
|
||||
do{\
|
||||
if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \
|
||||
*((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 2); \
|
||||
else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \
|
||||
*((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = (u32Count); \
|
||||
else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \
|
||||
*((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 1); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Stop the channel
|
||||
*
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro stop the selected channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk)
|
||||
|
||||
void PDMA_Open(uint32_t u32Mask);
|
||||
void PDMA_Close(void);
|
||||
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
|
||||
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
|
||||
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
|
||||
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
|
||||
void PDMA_Trigger(uint32_t u32Ch);
|
||||
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
|
||||
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
|
||||
|
||||
/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_PDMA_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__PDMA_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,205 @@
|
||||
/**************************************************************************//**
|
||||
* @file pwm.h
|
||||
* @version V1.00
|
||||
* $Revision: 12 $
|
||||
* $Date: 15/06/30 2:52p $
|
||||
* @brief NANO100 series PWM driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __PWM_H__
|
||||
#define __PWM_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_PWM_Driver PWM Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_PWM_EXPORTED_CONSTANTS PWM Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define PWM_CHANNEL_NUM (4) /*!< PWM channel number \hideinitializer */
|
||||
#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
|
||||
#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
|
||||
#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
|
||||
#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
|
||||
#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
|
||||
#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
|
||||
#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
|
||||
#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
|
||||
#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
|
||||
#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
|
||||
#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
|
||||
#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
|
||||
#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
|
||||
#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
|
||||
#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
|
||||
#define PWM_RISING_LATCH_INT_ENABLE (1UL) /*!< PWM rising latch interrupt enable \hideinitializer */
|
||||
#define PWM_FALLING_LATCH_INT_ENABLE (2UL) /*!< PWM falling latch interrupt enable \hideinitializer */
|
||||
#define PWM_RISING_FALLING_LATCH_INT_ENABLE (3UL) /*!< PWM rising latch interrupt enable \hideinitializer */
|
||||
#define PWM_RISING_LATCH_INT_FLAG (2UL) /*!< PWM rising latch condition happened \hideinitializer */
|
||||
#define PWM_FALLING_LATCH_INT_FLAG (4UL) /*!< PWM falling latch condition happened \hideinitializer */
|
||||
#define PWM_RISING_FALLING_LATCH_INT_FLAG (6UL) /*!< PWM rising latch condition happened \hideinitializer */
|
||||
#define PWM_RISING_LATCH_PDMA_ENABLE (0x10UL) /*!< PWM rising latch PDMA enable \hideinitializer */
|
||||
#define PWM_FALLING_LATCH_PDMA_ENABLE (0x20UL) /*!< PWM falling latch PDMA enable \hideinitializer */
|
||||
#define PWM_RISING_FALLING_LATCH_PDMA_ENABLE (0x30UL) /*!< PWM rising and falling latch PDMA enable \hideinitializer */
|
||||
#define PWM_CAP_PDMA_RFORDER_R (0x1000UL) /*!< PWM captured data transferred by PDMA is rising latch first \hideinitializer */
|
||||
#define PWM_CAP_PDMA_RFORDER_F (0UL) /*!< PWM captured data transferred by PDMA is falling latch first \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group NANO100_PWM_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro enable output inverter of specified channel(s)
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask)\
|
||||
do { \
|
||||
uint8_t i; \
|
||||
(pwm)->CTL &= ~(PWM_CTL_CH0INV_Msk | PWM_CTL_CH1INV_Msk | PWM_CTL_CH2INV_Msk | PWM_CTL_CH3INV_Msk);\
|
||||
for (i = 0; i < PWM_CHANNEL_NUM; i++) { \
|
||||
if ( (u32ChannelMask) & (1 << i)) { \
|
||||
(pwm)->CTL |= (PWM_CTL_CH0INV_Msk << (i * 8)); \
|
||||
} \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief This macro get captured rising data
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CRL0 + 2 * u32ChannelNum))
|
||||
|
||||
/**
|
||||
* @brief This macro get captured falling data
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CFL0 + 2 * u32ChannelNum))
|
||||
|
||||
/**
|
||||
* @brief This macro set the prescaler of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
|
||||
* @return None
|
||||
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
|
||||
* channel 1 will also be affected.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
|
||||
(pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
|
||||
|
||||
/**
|
||||
* @brief This macro set the divider of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Divider Clock divider of specified channel. Valid values are
|
||||
* - \ref PWM_CLK_DIV_1
|
||||
* - \ref PWM_CLK_DIV_2
|
||||
* - \ref PWM_CLK_DIV_4
|
||||
* - \ref PWM_CLK_DIV_8
|
||||
* - \ref PWM_CLK_DIV_16
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
|
||||
(pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u32Divider << (4 * u32ChannelNum)))
|
||||
|
||||
/**
|
||||
* @brief This macro set the duty of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next PWM period
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) \
|
||||
do { \
|
||||
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; \
|
||||
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= (u32CMR << PWM_DUTY_CM_Pos); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro set the period of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next PWM period
|
||||
* @note PWM counter will stop if period length set to 0
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) \
|
||||
do { \
|
||||
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; \
|
||||
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u32CNR; \
|
||||
} while(0)
|
||||
|
||||
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
|
||||
uint32_t u32ChannelNum,
|
||||
uint32_t u32Frequency,
|
||||
uint32_t u32DutyCycle);
|
||||
uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
|
||||
uint32_t u32ChannelNum,
|
||||
uint32_t u32UnitTimeNsec,
|
||||
uint32_t u32CaptureEdge);
|
||||
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
|
||||
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||||
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
|
||||
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_PWM_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__PWM_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,254 @@
|
||||
/**************************************************************************//**
|
||||
* @file rtc.h
|
||||
* @version V1.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 15/06/26 1:34p $
|
||||
* @brief Nano100 series RTC driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __RTC_H__
|
||||
#define __RTC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_RTC_Driver RTC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup NANO100_RTC_EXPORTED_CONSTANTS RTC Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
#define RTC_INIT_KEY 0xA5EB1357 /*!< RTC Access Key */
|
||||
#define RTC_WRITE_KEY 0xA965 /*!< RTC Access Key */
|
||||
|
||||
#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time Out Value */
|
||||
|
||||
#define RTC_YEAR2000 2000 /*!< RTC Reference */
|
||||
#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference */
|
||||
|
||||
#define RTC_CLOCK_12 0 /*!< RTC 12 Hour */
|
||||
#define RTC_CLOCK_24 1 /*!< RTC 24 Hour */
|
||||
|
||||
#define RTC_AM 1 /*!< RTC AM */
|
||||
#define RTC_PM 2 /*!< RTC PM */
|
||||
|
||||
#define RTC_TICK_1_SEC ((uint32_t) 0x00000000) /*!< Time tick is 1 second */
|
||||
#define RTC_TICK_1_2_SEC ((uint32_t) 0x00000001) /*!< Time tick is 1/2 second */
|
||||
#define RTC_TICK_1_4_SEC ((uint32_t) 0x00000002) /*!< Time tick is 1/4 second */
|
||||
#define RTC_TICK_1_8_SEC ((uint32_t) 0x00000003) /*!< Time tick is 1/8 second */
|
||||
#define RTC_TICK_1_16_SEC ((uint32_t) 0x00000004) /*!< Time tick is 1/16 second */
|
||||
#define RTC_TICK_1_32_SEC ((uint32_t) 0x00000005) /*!< Time tick is 1/32 second */
|
||||
#define RTC_TICK_1_64_SEC ((uint32_t) 0x00000006) /*!< Time tick is 1/64 second */
|
||||
#define RTC_TICK_1_128_SEC ((uint32_t) 0x00000007) /*!< Time tick is 1/128 second */
|
||||
|
||||
#define RTC_SUNDAY ((uint32_t) 0x00000000) /*!< Day of week is sunday */
|
||||
#define RTC_MONDAY ((uint32_t) 0x00000001) /*!< Day of week is monday */
|
||||
#define RTC_TUESDAY ((uint32_t) 0x00000002) /*!< Day of week is tuesday */
|
||||
#define RTC_WEDNESDAY ((uint32_t) 0x00000003) /*!< Day of week is wednesday */
|
||||
#define RTC_THURSDAY ((uint32_t) 0x00000004) /*!< Day of week is thursday */
|
||||
#define RTC_FRIDAY ((uint32_t) 0x00000005) /*!< Day of week is friday */
|
||||
#define RTC_SATURDAY ((uint32_t) 0x00000006) /*!< Day of week is saturday */
|
||||
|
||||
|
||||
#define RTC_SNOOPER_RISING 0 /*!< Snooper Active Rising Edge */
|
||||
#define RTC_SNOOPER_FALLING 1 /*!< Snooper Active Falling Edge */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_RTC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_RTC_EXPORTED_STRUCTS RTC Exported Structs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RTC define Time Data Struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32Year; /*!< Year value */
|
||||
uint32_t u32Month; /*!< Month value */
|
||||
uint32_t u32Day; /*!< Day value */
|
||||
uint32_t u32DayOfWeek; /*!< Day of week value */
|
||||
uint32_t u32Hour; /*!< Hour value */
|
||||
uint32_t u32Minute; /*!< Minute value */
|
||||
uint32_t u32Second; /*!< Second value */
|
||||
uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
|
||||
uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
|
||||
} S_RTC_TIME_DATA_T;
|
||||
|
||||
/*@}*/ /* end of group NANO100_RTC_EXPORTED_STRUCTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read spare register
|
||||
*
|
||||
* @param[in] u32RegNum The spare register number(0~23)
|
||||
*
|
||||
* @return Spare register content.
|
||||
*
|
||||
*/
|
||||
#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[u32RegNum])
|
||||
|
||||
/**
|
||||
* @brief Write spare register
|
||||
*
|
||||
* @param[in] u32RegNum The spare register number(0~23)
|
||||
* @param[in] u32RegValue The spare register value
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[u32RegNum] = u32RegValue)
|
||||
|
||||
/**
|
||||
* @brief According to current time, return this year is leap year or not
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return 0 = This year is not a leap year. \n
|
||||
* 1 = This year is a leap year.
|
||||
*
|
||||
*/
|
||||
#define RTC_IS_LEAP_YEAR() ((RTC->LIR & (RTC_LIR_LIR_Msk))?1:0)
|
||||
|
||||
/**
|
||||
* @brief Clear alarm interrupt status.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->RIIR = RTC_RIIR_AIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear tick interrupt status.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
#define RTC_CLEAR_TICK_INT_FLAG() (RTC->RIIR = RTC_RIIR_TIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear tamper detect pin status.
|
||||
*
|
||||
* @param[in] u32PinNum tamper detect pin number.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
#define RTC_CLEAR_TAMPER_FLAG(u32PinNum) (RTC->RIIR = RTC_RIIR_SNOOPIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get alarm interrupt status.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return Alarm interrupt status
|
||||
*
|
||||
*/
|
||||
#define RTC_GET_ALARM_INT_FLAG() ((RTC->RIIR & RTC_RIIR_AIF_Msk) >> RTC_RIIR_AIF_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get alarm interrupt status.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return Alarm interrupt status
|
||||
*
|
||||
*/
|
||||
#define RTC_GET_TICK_INT_FLAG() ((RTC->RIIR & RTC_RIIR_TIF_Msk) >> RTC_RIIR_TIF_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get tamper detect pin status.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return 1: Snooper Pin Event Detected \n
|
||||
* 0: Snooper Pin Event Never Detected
|
||||
*
|
||||
*/
|
||||
#define RTC_GET_TAMPER_FLAG() ( (RTC->RIIR & RTC_RIIR_SNOOPIF_Msk) >> RTC_RIIR_SNOOPIF_Pos)
|
||||
|
||||
/**
|
||||
* @brief Enable Timer tick wakeup function.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
#define RTC_ENABLE_TICK_WAKEUP() (RTC->TTR |= RTC_TTR_TWKE_Msk);
|
||||
|
||||
/**
|
||||
* @brief Disable Timer tick wakeup function.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
#define RTC_DISABLE_TICK_WAKEUP() (RTC->TTR &= ~RTC_TTR_TWKE_Msk);
|
||||
|
||||
|
||||
void RTC_Open(S_RTC_TIME_DATA_T *sPt);
|
||||
void RTC_Close(void);
|
||||
void RTC_32KCalibration(int32_t i32FrequencyX100);
|
||||
void RTC_SetTickPeriod(uint32_t u32TickSelection);
|
||||
void RTC_EnableInt(uint32_t u32IntFlagMask);
|
||||
void RTC_DisableInt(uint32_t u32IntFlagMask);
|
||||
uint32_t RTC_GetDayOfWeek(void);
|
||||
void RTC_DisableTamperDetection(void);
|
||||
void RTC_EnableTamperDetection(uint32_t u32PinCondition);
|
||||
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
|
||||
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
|
||||
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_RTC_EXPORTED_FUNCTIONS */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_RTC_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __RTC_H__ */
|
||||
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,269 @@
|
||||
/**************************************************************************//**
|
||||
* @file sc.h
|
||||
* @version V1.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 15/07/31 7:26p $
|
||||
* @brief Nano100 series Smartcard (SC) driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013~2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SC_H__
|
||||
#define __SC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SC_Driver SC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SC_EXPORTED_CONSTANTS SC Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers */
|
||||
#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high */
|
||||
#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low */
|
||||
#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status */
|
||||
#define SC_CLK_ON 1 /*!< Smartcard clock on */
|
||||
#define SC_CLK_OFF 0 /*!< Smartcard clock off */
|
||||
|
||||
#define SC_TMR_MODE_0 (0ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 0, down count */
|
||||
#define SC_TMR_MODE_1 (1ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit */
|
||||
#define SC_TMR_MODE_2 (2ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit */
|
||||
#define SC_TMR_MODE_3 (3ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode */
|
||||
#define SC_TMR_MODE_4 (4ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout */
|
||||
#define SC_TMR_MODE_5 (5ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout */
|
||||
#define SC_TMR_MODE_6 (6ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout */
|
||||
#define SC_TMR_MODE_7 (7ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit */
|
||||
#define SC_TMR_MODE_8 (8ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 8, up count */
|
||||
#define SC_TMR_MODE_F (0xF << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_SC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_SC_EXPORTED_FUNCTIONS SC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro enable smartcard interrupt
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32Mask Interrupt mask to be enabled. A combination of
|
||||
* - \ref SC_IER_ACON_ERR_IE_Msk
|
||||
* - \ref SC_IER_RTMR_IE_Msk
|
||||
* - \ref SC_IER_INIT_IE_Msk
|
||||
* - \ref SC_IER_CD_IE_Msk
|
||||
* - \ref SC_IER_BGT_IE_Msk
|
||||
* - \ref SC_IER_TMR2_IE_Msk
|
||||
* - \ref SC_IER_TMR1_IE_Msk
|
||||
* - \ref SC_IER_TMR0_IE_Msk
|
||||
* - \ref SC_IER_TERR_IE_Msk
|
||||
* - \ref SC_IER_TBE_IE_Msk
|
||||
* - \ref SC_IER_RDA_IE_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_ENABLE_INT(sc, u32Mask) ((sc)->IER |= (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief This macro disable smartcard interrupt
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
|
||||
* - \ref SC_IER_ACON_ERR_IE_Msk
|
||||
* - \ref SC_IER_RTMR_IE_Msk
|
||||
* - \ref SC_IER_INIT_IE_Msk
|
||||
* - \ref SC_IER_CD_IE_Msk
|
||||
* - \ref SC_IER_BGT_IE_Msk
|
||||
* - \ref SC_IER_TMR2_IE_Msk
|
||||
* - \ref SC_IER_TMR1_IE_Msk
|
||||
* - \ref SC_IER_TMR0_IE_Msk
|
||||
* - \ref SC_IER_TERR_IE_Msk
|
||||
* - \ref SC_IER_TBE_IE_Msk
|
||||
* - \ref SC_IER_RDA_IE_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask))
|
||||
|
||||
/**
|
||||
* @brief This macro set VCC pin state of smartcard interface
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_SET_VCC_PIN(sc, u32State) \
|
||||
do {\
|
||||
uint32_t reg = (sc)->PINCSR;\
|
||||
if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
|
||||
((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
|
||||
reg &= ~SC_PINCSR_POW_EN_Msk;\
|
||||
else\
|
||||
reg |= SC_PINCSR_POW_EN_Msk;\
|
||||
if(u32State)\
|
||||
(sc)->PINCSR = reg | SC_PINCSR_POW_EN_Msk;\
|
||||
else\
|
||||
(sc)->PINCSR = reg & ~SC_PINCSR_POW_EN_Msk;\
|
||||
}while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief This macro turns CLK output on or off
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_SET_CLK_PIN(sc, u32OnOff)\
|
||||
do {\
|
||||
uint32_t reg = (sc)->PINCSR;\
|
||||
if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
|
||||
((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
|
||||
reg &= ~SC_PINCSR_POW_EN_Msk;\
|
||||
else\
|
||||
reg |= SC_PINCSR_POW_EN_Msk;\
|
||||
if(u32OnOff)\
|
||||
(sc)->PINCSR = reg | SC_PINCSR_CLK_KEEP_Msk;\
|
||||
else\
|
||||
(sc)->PINCSR = reg & ~SC_PINCSR_CLK_KEEP_Msk;\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro set I/O pin state of smartcard interface
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_SET_IO_PIN(sc, u32State)\
|
||||
do {\
|
||||
uint32_t reg = (sc)->PINCSR;\
|
||||
if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
|
||||
((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
|
||||
reg &= ~SC_PINCSR_POW_EN_Msk;\
|
||||
else\
|
||||
reg |= SC_PINCSR_POW_EN_Msk;\
|
||||
if(u32State)\
|
||||
(sc)->PINCSR = reg | SC_PINCSR_SC_DATA_O_Msk;\
|
||||
else\
|
||||
(sc)->PINCSR = reg & ~SC_PINCSR_SC_DATA_O_Msk;\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro set RST pin state of smartcard interface
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_SET_RST_PIN(sc, u32State)\
|
||||
do {\
|
||||
uint32_t reg = (sc)->PINCSR;\
|
||||
if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
|
||||
((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
|
||||
reg &= ~SC_PINCSR_POW_EN_Msk;\
|
||||
else\
|
||||
reg |= SC_PINCSR_POW_EN_Msk;\
|
||||
if(u32State)\
|
||||
(sc)->PINCSR = reg | SC_PINCSR_SC_RST_Msk;\
|
||||
else\
|
||||
(sc)->PINCSR = reg & ~SC_PINCSR_SC_RST_Msk;\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro read one byte from smartcard module receive FIFO
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @return[in] One byte read from receive FIFO
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_READ(sc) ((char)((sc)->RBR))
|
||||
|
||||
/**
|
||||
* @brief This macro write one byte to smartcard module transmit FIFO
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u8Data Data to write to transmit FIFO
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_WRITE(sc, u8Data) ((sc)->THR = (u8Data))
|
||||
|
||||
/**
|
||||
* @brief This macro set smartcard stop bit length
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32Len Stop bit length, ether 1 or 2.
|
||||
* @return None
|
||||
* @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_SLEN_Msk) | (u32Len == 1 ? SC_CTL_SLEN_Msk : 0))
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable Tx error retry, and set Tx error retry count
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
|
||||
{
|
||||
// Retry count must set while enable bit disabled, so disable it first
|
||||
sc->CTL &= ~(SC_CTL_TX_ERETRY_Msk | SC_CTL_TX_ERETRY_EN_Msk);
|
||||
|
||||
if(u32Count != 0)
|
||||
{
|
||||
sc->CTL |= ((u32Count - 1) << SC_CTL_TX_ERETRY_Pos) | SC_CTL_TX_ERETRY_EN_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable Rx error retry, and set Rx error retry count
|
||||
* @param[in] sc Base address of smartcard module
|
||||
* @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
|
||||
{
|
||||
// Retry count must set while enable bit disabled, so disable it first
|
||||
sc->CTL &= ~(SC_CTL_RX_ERETRY_Msk | SC_CTL_RX_ERETRY_EN_Msk);
|
||||
|
||||
if(u32Count != 0)
|
||||
{
|
||||
sc->CTL |= ((u32Count - 1) << SC_CTL_RX_ERETRY_Pos) | SC_CTL_RX_ERETRY_EN_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint32_t SC_IsCardInserted(SC_T *sc);
|
||||
void SC_ClearFIFO(SC_T *sc);
|
||||
void SC_Close(SC_T *sc);
|
||||
void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
|
||||
void SC_ResetReader(SC_T *sc);
|
||||
void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
|
||||
void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
|
||||
void SC_StopAllTimer(SC_T *sc);
|
||||
void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
|
||||
void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_SC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_SC_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,261 @@
|
||||
/**************************************************************************//**
|
||||
* @file sc.h
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 14/05/20 7:57p $
|
||||
* @brief Nano100 series Smartcard UART mode (SCUART) driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SCUART_H__
|
||||
#define __SCUART_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SCUART_Driver SCUART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define SCUART_CHAR_LEN_5 (0x3ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 5 bits */
|
||||
#define SCUART_CHAR_LEN_6 (0x2ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 6 bits */
|
||||
#define SCUART_CHAR_LEN_7 (0x1ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 7 bits */
|
||||
#define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits */
|
||||
|
||||
#define SCUART_PARITY_NONE (SC_UACTL_PBDIS_Msk) /*!< Set SCUART transfer with no parity */
|
||||
#define SCUART_PARITY_ODD (SC_UACTL_OPE_Msk) /*!< Set SCUART transfer with odd parity */
|
||||
#define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity */
|
||||
|
||||
#define SCUART_STOP_BIT_1 (SC_CTL_SLEN_Msk) /*!< Set SCUART transfer with one stop bit */
|
||||
#define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_SCUART_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* TX Macros */
|
||||
/**
|
||||
* @brief Write Data to Tx data register
|
||||
* @param[in] sc The base address of smartcard module.
|
||||
* @param[in] u8Data Data byte to transmit
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_WRITE(sc, u8Data) ((sc)->THR = (u8Data))
|
||||
|
||||
/**
|
||||
* @brief Get TX FIFO empty flag status from register
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Transmit FIFO empty status
|
||||
* @retval 0 Transmit FIFO is not empty
|
||||
* @retval SC_TRSR_TX_EMPTY_F_Msk Transmit FIFO is empty
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_GET_TX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_TX_EMPTY_F_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get TX FIFO full flag status from register
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Transmit FIFO full status
|
||||
* @retval 0 Transmit FIFO is not full
|
||||
* @retval SC_TRSR_TX_FULL_F_Msk Transmit FIFO is full
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_GET_TX_FULL(sc) ((sc)->TRSR & SC_TRSR_TX_FULL_F_Msk)
|
||||
|
||||
/**
|
||||
* @brief Wait specified smartcard port transmission complete
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return None
|
||||
* @note This Macro blocks until transmit complete.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->TRSR & SC_TRSR_TX_ATV_Msk)
|
||||
|
||||
/**
|
||||
* @brief Check specified smartcard port transmit FIFO is full or not
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Transmit FIFO full status
|
||||
* @retval 0 Transmit FIFO is not full
|
||||
* @retval 1 Transmit FIFO is full
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_IS_TX_FULL(sc) ((sc)->TRSR & SC_TRSR_TX_FULL_F_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Check specified smartcard port transmission is over
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Transmit complete status
|
||||
* @retval 0 Transmit is not complete
|
||||
* @retval 1 Transmit complete
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_IS_TX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_TX_ATV_Msk ? 0 : 1)
|
||||
|
||||
|
||||
/* RX Macros */
|
||||
|
||||
/**
|
||||
* @brief Read Rx data register
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return The oldest data byte in RX FIFO
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_READ(sc) ((sc)->RBR)
|
||||
|
||||
/**
|
||||
* @brief Get RX FIFO empty flag status from register
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Receive FIFO empty status
|
||||
* @retval 0 Receive FIFO is not empty
|
||||
* @retval SC_TRSR_RX_EMPTY_F_Msk Receive FIFO is empty
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_GET_RX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_RX_EMPTY_F_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get RX FIFO full flag status from register
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Receive FIFO full status
|
||||
* @retval 0 Receive FIFO is not full
|
||||
* @retval SC_TRSR_TX_FULL_F_Msk Receive FIFO is full
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_GET_RX_FULL(sc) ((sc)->TRSR & SC_TRSR_RX_FULL_F_Msk)
|
||||
|
||||
/**
|
||||
* @brief Check if receive data number in FIFO reach FIFO trigger level or not
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Receive FIFO data status
|
||||
* @retval 0 The number of bytes in receive FIFO is less than trigger level
|
||||
* @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
|
||||
* @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_IS_RX_READY(sc) ((sc)->ISR & SC_ISR_RDA_IS_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Check specified smartcard port receive FIFO is full or not
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Receive FIFO full status
|
||||
* @retval 0 Receive FIFO is not full
|
||||
* @retval 1 Receive FIFO is full
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_IS_RX_FULL(sc) ((sc)->TRSR & SC_TRSR_RX_FULL_F_Msk ? 1 : 0)
|
||||
|
||||
/* Interrupt Macros */
|
||||
|
||||
/**
|
||||
* @brief Enable specified interrupts
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @param[in] u32Mask Interrupt masks to enable, a combination of following bits
|
||||
* - \ref SC_IER_RTMR_IE_Msk
|
||||
* - \ref SC_IER_TERR_IE_Msk
|
||||
* - \ref SC_IER_TBE_IE_Msk
|
||||
* - \ref SC_IER_RDA_IE_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->IER |= (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Disable specified interrupts
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @param[in] u32Mask Interrupt masks to disable, a combination of following bits
|
||||
* - \ref SC_IER_RTMR_IE_Msk
|
||||
* - \ref SC_IER_TERR_IE_Msk
|
||||
* - \ref SC_IER_TBE_IE_Msk
|
||||
* - \ref SC_IER_RDA_IE_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Get specified interrupt flag/status
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @param[in] u32Type Interrupt flag/status to check, could be one of following value
|
||||
* - \ref SC_ISR_RTMR_IS_Msk
|
||||
* - \ref SC_ISR_TERR_IS_Msk
|
||||
* - \ref SC_ISR_TBE_IS_Msk
|
||||
* - \ref SC_ISR_RDA_IS_Msk
|
||||
* @return The status of specified interrupt
|
||||
* @retval 0 Specified interrupt does not happened
|
||||
* @retval 1 Specified interrupt happened
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->ISR & u32Type ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Clear specified interrupt flag/status
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
|
||||
* - \ref SC_ISR_RTMR_IS_Msk
|
||||
* - \ref SC_ISR_TERR_IS_Msk
|
||||
* - \ref SC_ISR_TBE_IS_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->ISR = u32Type)
|
||||
|
||||
/**
|
||||
* @brief Get receive error flag/status
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @return Current receive error status, could one of following errors:
|
||||
* @retval SC_TRSR_RX_EPA_F_Msk Parity error
|
||||
* @retval SC_TRSR_RX_EFR_F_Msk Frame error
|
||||
* @retval SC_TRSR_RX_EBR_F_Msk Break error
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_GET_ERR_FLAG(sc) ((sc)->TRSR & (SC_TRSR_RX_EPA_F_Msk | SC_TRSR_RX_EFR_F_Msk | SC_TRSR_RX_EBR_F_Msk))
|
||||
|
||||
/**
|
||||
* @brief Clear specified receive error flag/status
|
||||
* @param[in] sc The base address of smartcard module
|
||||
* @param[in] u32Mask Receive error flag/status to clear, combination following values
|
||||
* - \ref SC_TRSR_RX_EPA_F_Msk
|
||||
* - \ref SC_TRSR_RX_EFR_F_Msk
|
||||
* - \ref SC_TRSR_RX_EBR_F_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->TRSR = u32Mask)
|
||||
|
||||
void SCUART_Close(SC_T* sc);
|
||||
uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
|
||||
uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
|
||||
uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
|
||||
void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
|
||||
void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
|
||||
|
||||
/*@}*/ /* end of group NANO100_SCUART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_SCUART_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SCUART_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,387 @@
|
||||
/****************************************************************************//**
|
||||
* @file spi.h
|
||||
* @version V1.00
|
||||
* $Revision: 8 $
|
||||
* $Date: 15/06/08 5:03p $
|
||||
* @brief NANO100 series SPI driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SPI_Driver SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup NANO100_SPI_EXPORTED_CONSTANTS SPI Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
|
||||
#define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
|
||||
#define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
|
||||
#define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
|
||||
|
||||
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
|
||||
#define SPI_MASTER (0x0) /*!< Set as master */
|
||||
|
||||
#define SPI_SS0 (0x1) /*!< Set SS0 */
|
||||
#define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS0 active high */
|
||||
#define SPI_SS0_ACTIVE_LOW (0x0) /*!< SS0 active low */
|
||||
|
||||
#define SPI_SS1 (0x2) /*!< Set SS1 */
|
||||
#define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS1 active high */
|
||||
#define SPI_SS1_ACTIVE_LOW (0x0) /*!< SS1 active low */
|
||||
|
||||
#define SPI_IE_MASK (0x01) /*!< Interrupt enable mask */
|
||||
#define SPI_SSTA_INTEN_MASK (0x04) /*!< Slave 3-Wire mode start interrupt enable mask */
|
||||
#define SPI_FIFO_TX_INTEN_MASK (0x08) /*!< FIFO TX interrupt mask */
|
||||
#define SPI_FIFO_RX_INTEN_MASK (0x10) /*!< FIFO RX interrupt mask */
|
||||
#define SPI_FIFO_RXOVR_INTEN_MASK (0x20) /*!< FIFO RX overrun interrupt mask */
|
||||
#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) /*!< FIFO timeout interrupt mask */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_SPI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Abort the current transfer in slave 3-wire mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSR |= SPI_SSR_SLV_ABORT_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear the slave 3-wire mode start interrupt flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear the unit transfer interrupt flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_INTSTS_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable slave 3-wire mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSR &= ~SPI_SSR_NOSLVSEL_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable slave 3-wire mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSR |= SPI_SSR_NOSLVSEL_Msk )
|
||||
|
||||
/**
|
||||
* @brief Get the count of available data in RX FIFO.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return The count of available data in RX FIFO.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_CNT_Msk) >> SPI_STATUS_RX_FIFO_CNT_Pos) & 0xf )
|
||||
|
||||
/**
|
||||
* @brief Get the Rx FIFO empty flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Rx FIFO flag
|
||||
* @retval 0 Rx FIFO is not empty
|
||||
* @retval 1 Rx FIFO is empty
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Get the Tx FIFO empty flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Tx FIFO flag
|
||||
* @retval 0 Tx FIFO is not empty
|
||||
* @retval 1 Tx FIFO is empty
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Get the Tx FIFO full flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Tx FIFO flag
|
||||
* @retval 0 Tx FIFO is not full
|
||||
* @retval 1 Tx FIFO is full
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Get the datum read from RX0 FIFO.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Data in Rx0 register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_READ_RX0(spi) ( (spi)->RX0 )
|
||||
|
||||
/**
|
||||
* @brief Get the datum read from RX1 FIFO.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Data in Rx1 register.
|
||||
*/
|
||||
#define SPI_READ_RX1(spi) ( (spi)->RX1 )
|
||||
|
||||
/**
|
||||
* @brief Write datum to TX0 register.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_WRITE_TX0(spi, u32TxData) ( (spi)->TX0 = u32TxData )
|
||||
|
||||
/**
|
||||
* @brief Write datum to TX1 register.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_WRITE_TX1(spi, u32TxData) ( (spi)->TX1 = u32TxData )
|
||||
|
||||
/**
|
||||
* @brief Set SPIn_SS0 pin to high state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_SS0_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)))
|
||||
|
||||
/**
|
||||
* @brief Set SPIn_SS0 pin to low state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_SS0_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)) | SPI_SS0)
|
||||
|
||||
/**
|
||||
* @brief Set SPIn_SS1 pin to high state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_SS1_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)))
|
||||
|
||||
/**
|
||||
* @brief Set SPIn_SS1 pin to low state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_SS1_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)) | SPI_SS1)
|
||||
|
||||
/**
|
||||
* @brief Set SPIn_SS0, SPIn_SS1 pin to high or low state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] ss0 0 = Set SPIn_SS0 to low. 1 = Set SPIn_SS0 to high.
|
||||
* @param[in] ss1 0 = Set SPIn_SS1 to low. 1 = Set SPIn_SS1 to high.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIn_SS0/SPIn_SS1 pin to specified high/low state.
|
||||
* Only available in Master mode.
|
||||
*/
|
||||
#define SPI_SET_SS_LEVEL(spi, ss0, ss1) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SSR_SSR_Msk)) | (((ss1)^1) << 1) | ((ss0)^1))
|
||||
|
||||
/**
|
||||
* @brief Enable byte reorder function.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable byte reorder function.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the length of suspend interval.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32SuspCycle decides the length of suspend interval.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CTL_SP_CYCLE_Pos) )
|
||||
|
||||
/**
|
||||
* @brief Set the SPI transfer sequence with LSB first.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the SPI transfer sequence with MSB first.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the data width of a SPI transaction.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32Width is the data width (from 8-32 bits).
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
|
||||
{
|
||||
if(u32Width == 32)
|
||||
u32Width = 0;
|
||||
|
||||
spi->CTL = (spi->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (u32Width << SPI_CTL_TX_BIT_LEN_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SPI busy state.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return SPI busy status
|
||||
* @retval 0 SPI module is not busy
|
||||
* @retval 1 SPI module is busy
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_GO_BUSY_Msk) == SPI_CTL_GO_BUSY_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Set the GO_BUSY bit to trigger SPI transfer.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_GO_BUSY_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable SPI Dual IO function.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUAL_IO_EN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable Dual IO function and set SPI Dual IO direction to input.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DUAL_IO_DIR_Msk) | SPI_CTL_DUAL_IO_EN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable Dual IO function and set SPI Dual IO direction to output.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= (SPI_CTL_DUAL_IO_DIR_Msk | SPI_CTL_DUAL_IO_EN_Msk) )
|
||||
|
||||
/**
|
||||
* @brief Trigger RX PDMA transfer.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_RX_DMA_EN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Trigger TX PDMA transfer.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_TX_DMA_EN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable 2-bit transfer mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable 2-bit transfer mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Get the status register value.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return status value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define SPI_GET_STATUS(spi) ( (spi)->STATUS )
|
||||
|
||||
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||
void SPI_Close(SPI_T *spi);
|
||||
void SPI_ClearRxFIFO(SPI_T *spi);
|
||||
void SPI_ClearTxFIFO(SPI_T *spi);
|
||||
void SPI_DisableAutoSS(SPI_T *spi);
|
||||
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
|
||||
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||
void SPI_DisableFIFO(SPI_T *spi);
|
||||
uint32_t SPI_GetBusClock(SPI_T *spi);
|
||||
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
|
||||
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
|
||||
void SPI_EnableWakeup(SPI_T *spi);
|
||||
void SPI_DisableWakeup(SPI_T *spi);
|
||||
/*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SPI_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,874 @@
|
||||
/**************************************************************************//**
|
||||
* @file sys.h
|
||||
* @version V1.00
|
||||
* $Revision: 17 $
|
||||
* $Date: 15/06/24 1:11p $
|
||||
* @brief Nano100 Series system control header file.
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SYS_H__
|
||||
#define __SYS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SYS_Driver SYS Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_SYS_EXPORTED_CONSTANTS SYS Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Module Reset Control Resister constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CHIP_RST ((0x0<<24) | SYS_IPRST_CTL1_CHIP_RST_Pos ) /*!< CHIP reset is one of the SYS_ResetModule parameter */
|
||||
#define CPU_RST ((0x0<<24) | SYS_IPRST_CTL1_CPU_RST_Pos ) /*!< CPU reset is one of the SYS_ResetModule parameter */
|
||||
#define DMA_RST ((0x0<<24) | SYS_IPRST_CTL1_DMA_RST_Pos ) /*!< DMA reset is one of the SYS_ResetModule parameter */
|
||||
#define EBI_RST ((0x0<<24) | SYS_IPRST_CTL1_EBI_RST_Pos ) /*!< EBI reset is one of the SYS_ResetModule parameter */
|
||||
#define SC1_RST ((0x4<<24) | SYS_IPRST_CTL2_SC1_RST_Pos ) /*!< SmartCard1 reset is one of the SYS_ResetModule parameter */
|
||||
#define SC0_RST ((0x4<<24) | SYS_IPRST_CTL2_SC0_RST_Pos ) /*!< SmartCard0 reset is one of the SYS_ResetModule parameter */
|
||||
#define I2S_RST ((0x4<<24) | SYS_IPRST_CTL2_I2S_RST_Pos ) /*!< I2S reset is one of the SYS_ResetModule parameter */
|
||||
#define ADC_RST ((0x4<<24) | SYS_IPRST_CTL2_ADC_RST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */
|
||||
#define USBD_RST ((0x4<<24) | SYS_IPRST_CTL2_USBD_RST_Pos ) /*!< USBD reset is one of the SYS_ResetModule parameter */
|
||||
#define DAC_RST ((0x4<<24) | SYS_IPRST_CTL2_DAC_RST_Pos ) /*!< DAC reset is one of the SYS_ResetModule parameter */
|
||||
#define PWM1_RST ((0x4<<24) | SYS_IPRST_CTL2_PWM1_RST_Pos ) /*!< PWM1 reset is one of the SYS_ResetModule parameter */
|
||||
#define PWM0_RST ((0x4<<24) | SYS_IPRST_CTL2_PWM0_RST_Pos ) /*!< PWM0 reset is one of the SYS_ResetModule parameter */
|
||||
#define UART1_RST ((0x4<<24) | SYS_IPRST_CTL2_UART1_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */
|
||||
#define UART0_RST ((0x4<<24) | SYS_IPRST_CTL2_UART0_RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */
|
||||
#define SPI2_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI2_RST_Pos ) /*!< SPI2 reset is one of the SYS_ResetModule parameter */
|
||||
#define SPI1_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI1_RST_Pos ) /*!< SPI1 reset is one of the SYS_ResetModule parameter */
|
||||
#define SPI0_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI0_RST_Pos ) /*!< SPI0 reset is one of the SYS_ResetModule parameter */
|
||||
#define I2C1_RST ((0x4<<24) | SYS_IPRST_CTL2_I2C1_RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
|
||||
#define I2C0_RST ((0x4<<24) | SYS_IPRST_CTL2_I2C0_RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
|
||||
#define TMR3_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR3_RST_Pos ) /*!< Timer3 reset is one of the SYS_ResetModule parameter */
|
||||
#define TMR2_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR2_RST_Pos ) /*!< Timer2 reset is one of the SYS_ResetModule parameter */
|
||||
#define TMR1_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR1_RST_Pos ) /*!< Timer1 reset is one of the SYS_ResetModule parameter */
|
||||
#define TMR0_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR0_RST_Pos ) /*!< Timer0 reset is one of the SYS_ResetModule parameter */
|
||||
#define GPIO_RST ((0x4<<24) | SYS_IPRST_CTL2_GPIO_RST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Multi-Function constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/********************* Bit definition of VREFCTL register **********************/
|
||||
#define SYS_VREFCTL_BGP_EN SYS_VREFCTL_BGP_EN_Msk /*!<Band-gap Enable */
|
||||
#define SYS_VREFCTL_REG_EN SYS_VREFCTL_REG_EN_Msk /*!<Regulator Enable */
|
||||
#define SYS_VREFCTL_SEL25 SYS_VREFCTL_SEL25_Msk /*!<Regulator Output Voltage 2.5V */
|
||||
#define SYS_VREFCTL_EXTMODE SYS_VREFCTL_EXT_MODE_Msk /*!<Regulator External Mode */
|
||||
|
||||
/********************* Bit definition of IRCTRIMCTL register **********************/
|
||||
#define SYS_IRCTRIMCTL_TRIM_11_0592M (0x1UL<<SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!<Trim HIRC to 11.0592 MHz */
|
||||
#define SYS_IRCTRIMCTL_TRIM_12M (0x2UL<<SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!<Trim HIRC to 12 MHz */
|
||||
#define SYS_IRCTRIMCTL_TRIM_12_288M (0x3UL<<SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!<Trim HIRC to 12.288 MHz */
|
||||
|
||||
#define SYS_IRCTRIMCTL_LOOP_4CLK (0x0UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 4 x 32.768 kHz clock */
|
||||
#define SYS_IRCTRIMCTL_LOOP_8CLK (0x1UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 8 x 32.768 kHz clock */
|
||||
#define SYS_IRCTRIMCTL_LOOP_16CLK (0x2UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 16 x 32.768 kHz clock */
|
||||
#define SYS_IRCTRIMCTL_LOOP_32CLK (0x3UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 32 x 32.768 kHz clock */
|
||||
|
||||
#define SYS_IRCTRIMCTL_RETRY_64 (0x0UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 64 */
|
||||
#define SYS_IRCTRIMCTL_RETRY_128 (0x1UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 128 */
|
||||
#define SYS_IRCTRIMCTL_RETRY_256 (0x2UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 256 */
|
||||
#define SYS_IRCTRIMCTL_RETRY_512 (0x3UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 512 */
|
||||
|
||||
/********************* Bit definition of IRCTRIMIEN register **********************/
|
||||
#define SYS_IRCTRIMIEN_DISABLE ((uint32_t)0x00000000) /*!<Trim failure interrupt disable */
|
||||
#define SYS_IRCTRIMIEN_FAIL_EN SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk /*!<Trim failure interrupt enable */
|
||||
#define SYS_IRCTRIMIEN_32KERR_EN SYS_IRCTRIMIEN_32K_ERR_IEN_Msk /*!<32.768 kHz Clock Error Interrupt Enable */
|
||||
|
||||
/********************* Bit definition of IRCTRIMINT register **********************/
|
||||
#define SYS_IRCTRIMINT_FREQLOCK SYS_IRCTRIMINT_FREQ_LOCK_Msk /*!<HIRC frequency lock status */
|
||||
#define SYS_IRCTRIMINT_FAIL_INT SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk /*!<Trim failure interrupt status */
|
||||
#define SYS_IRCTRIMINT_32KERR_INT SYS_IRCTRIMINT_32K_ERR_INT_Msk /*!<32.768 kHz Clock Error Interrupt Status */
|
||||
|
||||
/********************* Bit definition of PA_L_MFP register **********************/
|
||||
|
||||
#define SYS_PA_L_MFP_PA7_MFP_GPA7 (0UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - GPIOA[7] */
|
||||
#define SYS_PA_L_MFP_PA7_MFP_ADC_CH7 (1UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - ADC input channel 7 */
|
||||
#define SYS_PA_L_MFP_PA7_MFP_EBI_AD6 (2UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - EBI AD[6] */
|
||||
#define SYS_PA_L_MFP_PA7_MFP_TMR2_CAP (3UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - Timer 2 capture event */
|
||||
#define SYS_PA_L_MFP_PA7_MFP_SC2_DAT (4UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - SmartCard 2 data pin */
|
||||
#define SYS_PA_L_MFP_PA7_MFP_PWM0_CH2 (5UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - PWM0 Channel 2 */
|
||||
#define SYS_PA_L_MFP_PA7_MFP_LCD_S36 (7UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - LCD SEG 36 */
|
||||
|
||||
#define SYS_PA_L_MFP_PA6_MFP_GPA6 (0UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - GPIOA[6] */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_ADC_CH6 (1UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - ADC input channel 6 */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_EBI_AD7 (2UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - EBI AD[7] */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_TMR3_CAP (3UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - Timer 3 Capture event */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_SC2_CLK (4UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - SmartCard 2 clock */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_PWM0_CH3 (5UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - PWM0 Channel 3 */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_LCD_S37 (7UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - LCD SEG 37 */
|
||||
#define SYS_PA_L_MFP_PA6_MFP_LCD_S19 (7UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - LCD SEG 19 */
|
||||
|
||||
#define SYS_PA_L_MFP_PA5_MFP_GPA5 (0UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - GPIOA[5] */
|
||||
#define SYS_PA_L_MFP_PA5_MFP_ADC_CH5 (1UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - ADC input channel 5 */
|
||||
#define SYS_PA_L_MFP_PA5_MFP_EBI_AD8 (2UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - EBI AD[8] */
|
||||
#define SYS_PA_L_MFP_PA5_MFP_SC2_RST (4UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - SmartCard2 RST */
|
||||
#define SYS_PA_L_MFP_PA5_MFP_I2C0_SCL (5UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - I2C0 clock */
|
||||
#define SYS_PA_L_MFP_PA5_MFP_LCD_S38 (7UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - LCD SEG 38 */
|
||||
#define SYS_PA_L_MFP_PA5_MFP_LCD_S20 (7UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - LCD SEG 20 */
|
||||
|
||||
#define SYS_PA_L_MFP_PA4_MFP_GPA4 (0UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - GPIOA[4] */
|
||||
#define SYS_PA_L_MFP_PA4_MFP_ADC_CH4 (1UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - ADC input channel 4 */
|
||||
#define SYS_PA_L_MFP_PA4_MFP_EBI_AD9 (2UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - EBI AD[9] */
|
||||
#define SYS_PA_L_MFP_PA4_MFP_SC2_PWR (4UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - SmartCard 2 power */
|
||||
#define SYS_PA_L_MFP_PA4_MFP_I2C0_SDA (5UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - I2C0 DATA */
|
||||
#define SYS_PA_L_MFP_PA4_MFP_LCD_S39 (7UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - LCD SEG 39 */
|
||||
#define SYS_PA_L_MFP_PA4_MFP_LCD_S21 (7UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - LCD SEG 21 */
|
||||
|
||||
#define SYS_PA_L_MFP_PA3_MFP_GPA3 (0UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - GPIOA[3] */
|
||||
#define SYS_PA_L_MFP_PA3_MFP_ADC_CH3 (1UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - ADC input channel 3 */
|
||||
#define SYS_PA_L_MFP_PA3_MFP_EBI_AD10 (2UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - EBI AD[10] */
|
||||
#define SYS_PA_L_MFP_PA3_MFP_UART1_TX (5UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - UART 1 RX */
|
||||
#define SYS_PA_L_MFP_PA3_MFP_LCD_S22 (7UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - LCD SEG 22 */
|
||||
|
||||
#define SYS_PA_L_MFP_PA2_MFP_GPA2 (0UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - GPIOA[2] */
|
||||
#define SYS_PA_L_MFP_PA2_MFP_ADC_CH2 (1UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - ADC input channel 2 */
|
||||
#define SYS_PA_L_MFP_PA2_MFP_EBI_AD11 (2UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - EBI AD[11] */
|
||||
#define SYS_PA_L_MFP_PA2_MFP_UART1_RX (5UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - UART1 TX */
|
||||
#define SYS_PA_L_MFP_PA2_MFP_LCD_S23 (7UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - LCD SEG 23 */
|
||||
|
||||
#define SYS_PA_L_MFP_PA1_MFP_GPA1 (0UL<<SYS_PA_L_MFP_PA1_MFP_Pos) /*!<PA1 Pin Function - GPIOA[1] */
|
||||
#define SYS_PA_L_MFP_PA1_MFP_ADC_CH1 (1UL<<SYS_PA_L_MFP_PA1_MFP_Pos) /*!<PA1 Pin Function - ADC input channel 1 */
|
||||
#define SYS_PA_L_MFP_PA1_MFP_EBI_AD12 (2UL<<SYS_PA_L_MFP_PA1_MFP_Pos) /*!<PA1 Pin Function - EBI AD[12] */
|
||||
|
||||
#define SYS_PA_L_MFP_PA0_MFP_GPA0 (0UL<<SYS_PA_L_MFP_PA0_MFP_Pos) /*!<PA0 Pin Function - GPIOA[0] */
|
||||
#define SYS_PA_L_MFP_PA0_MFP_ADC_CH0 (1UL<<SYS_PA_L_MFP_PA0_MFP_Pos) /*!<PA0 Pin Function - ADC input channel 0 */
|
||||
#define SYS_PA_L_MFP_PA0_MFP_SC2_CD (4UL<<SYS_PA_L_MFP_PA0_MFP_Pos) /*!<PA0 Pin Function - SmartCard 2 card detect */
|
||||
|
||||
/********************* Bit definition of PA_H_MFP register **********************/
|
||||
#define SYS_PA_H_MFP_PA15_MFP_GPA15 (0UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - GPIOA[15] */
|
||||
#define SYS_PA_H_MFP_PA15_MFP_PWM0_CH3 (1UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - PWM0 Channel 3 */
|
||||
#define SYS_PA_H_MFP_PA15_MFP_I2S_MCLK (2UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - I2S MCLK */
|
||||
#define SYS_PA_H_MFP_PA15_MFP_TMR3_CAP (3UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - Timer3 capture event */
|
||||
#define SYS_PA_H_MFP_PA15_MFP_SC0_PWR (4UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - SmartCard 0 power */
|
||||
#define SYS_PA_H_MFP_PA15_MFP_UART0_TX (6UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - UART0 TX */
|
||||
#define SYS_PA_H_MFP_PA15_MFP_LCD_S27 (7UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - LCD SEG 27 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA14_MFP_GPA14 (0UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - GPIOA[14] */
|
||||
#define SYS_PA_H_MFP_PA14_MFP_PWM0_CH2 (1UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - PWM0 Channel 2 */
|
||||
#define SYS_PA_H_MFP_PA14_MFP_EBI_AD15 (2UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - EBI AD[15] */
|
||||
#define SYS_PA_H_MFP_PA14_MFP_TMR2_CAP (3UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - Timer2 capture event */
|
||||
#define SYS_PA_H_MFP_PA14_MFP_UART0_RX (6UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - UART0 RX */
|
||||
#define SYS_PA_H_MFP_PA14_MFP_LCD_S26 (7UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - LCD SEG 26 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA13_MFP_GPA13 (0UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - GPIOA[13] */
|
||||
#define SYS_PA_H_MFP_PA13_MFP_PWM0_CH1 (1UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - PWM0 Channel 1 */
|
||||
#define SYS_PA_H_MFP_PA13_MFP_EBI_AD14 (2UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - EBI AD[14] */
|
||||
#define SYS_PA_H_MFP_PA13_MFP_TMR1_CAP (3UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - Timer1 capture event */
|
||||
#define SYS_PA_H_MFP_PA13_MFP_I2C0_SCL (5UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - I2C0 clock */
|
||||
#define SYS_PA_H_MFP_PA13_MFP_LCD_S25 (7UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - LCD SEG 25 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA12_MFP_GPA12 (0UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - GPIOA[12] */
|
||||
#define SYS_PA_H_MFP_PA12_MFP_PWM0_CH0 (1UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - PWM0 Channel 0 */
|
||||
#define SYS_PA_H_MFP_PA12_MFP_EBI_AD13 (2UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - EBI AD[13] */
|
||||
#define SYS_PA_H_MFP_PA12_MFP_TMR0_CAP (3UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - Timer0 capture event */
|
||||
#define SYS_PA_H_MFP_PA12_MFP_I2C0_SDA (5UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - I2C0 DATA */
|
||||
#define SYS_PA_H_MFP_PA12_MFP_LCD_S24 (7UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - LCD SEG 24 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA11_MFP_GPA11 (0UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - GPIOA[11] */
|
||||
#define SYS_PA_H_MFP_PA11_MFP_I2C1_SCL (1UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - I2C1 clock */
|
||||
#define SYS_PA_H_MFP_PA11_MFP_EBI_NRE (2UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - EBI nRE */
|
||||
#define SYS_PA_H_MFP_PA11_MFP_SC0_RST (3UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - SmartCard0 RST */
|
||||
#define SYS_PA_H_MFP_PA11_MFP_SPI2_MOSI0 (4UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - SPI2 MOSI[0] */
|
||||
#define SYS_PA_H_MFP_PA11_MFP_LCD_S23 (7UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - LCD SEG 23 */
|
||||
#define SYS_PA_H_MFP_PA11_MFP_LCD_S9 (7UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - LCD SEG 9 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA10_MFP_GPA10 (0UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - GPIOA[10] */
|
||||
#define SYS_PA_H_MFP_PA10_MFP_I2C1_SDA (1UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - I2C1 DATA */
|
||||
#define SYS_PA_H_MFP_PA10_MFP_EBI_NWE (2UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - EBI nWE */
|
||||
#define SYS_PA_H_MFP_PA10_MFP_SC0_PWR (3UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - SmartCard0 Power */
|
||||
#define SYS_PA_H_MFP_PA10_MFP_SPI2_MISO0 (4UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - SPI2 MISO[0] */
|
||||
#define SYS_PA_H_MFP_PA10_MFP_LCD_S22 (7UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - LCD SEG 22 */
|
||||
#define SYS_PA_H_MFP_PA10_MFP_LCD_S8 (7UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - LCD SEG 8 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA9_MFP_GPA9 (0UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - GPIOA[9] */
|
||||
#define SYS_PA_H_MFP_PA9_MFP_I2C0_SCL (1UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - I2C0 clock */
|
||||
#define SYS_PA_H_MFP_PA9_MFP_SC0_DAT (3UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - SmartCard0 DATA */
|
||||
#define SYS_PA_H_MFP_PA9_MFP_SPI2_SCLK (4UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - SPI2 SCLK */
|
||||
#define SYS_PA_H_MFP_PA9_MFP_LCD_S21 (7UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - LCD SEG 21 */
|
||||
#define SYS_PA_H_MFP_PA9_MFP_LCD_S7 (7UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - LCD SEG 7 */
|
||||
|
||||
#define SYS_PA_H_MFP_PA8_MFP_GPA8 (0UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - GPIOA[8] */
|
||||
#define SYS_PA_H_MFP_PA8_MFP_I2C0_SDA (1UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - I2C0 DATA */
|
||||
#define SYS_PA_H_MFP_PA8_MFP_SC0_CLK (3UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - SmartCard0 clock */
|
||||
#define SYS_PA_H_MFP_PA8_MFP_SPI2_SS0 (4UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - SPI2 1st chip selection */
|
||||
#define SYS_PA_H_MFP_PA8_MFP_LCD_S20 (7UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - LCD SEG 20 */
|
||||
#define SYS_PA_H_MFP_PA8_MFP_LCD_S6 (7UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - LCD SEG 6 */
|
||||
|
||||
/********************* Bit definition of PB_L_MFP register **********************/
|
||||
#define SYS_PB_L_MFP_PB7_MFP_GPB7 (0UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - GPIOB[7] */
|
||||
#define SYS_PB_L_MFP_PB7_MFP_UART1_CTS (1UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - UART1 CTSn */
|
||||
#define SYS_PB_L_MFP_PB7_MFP_EBI_NCS (2UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - EBI nCS */
|
||||
#define SYS_PB_L_MFP_PB7_MFP_SPI2_MOSI0 (4UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - SPI2 MOSI[0] */
|
||||
#define SYS_PB_L_MFP_PB7_MFP_LCD_S10 (7UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - LCD SEG 10 */
|
||||
#define SYS_PB_L_MFP_PB7_MFP_LCD_S2 (7UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - LCD SEG 2 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB6_MFP_GPB6 (0UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - GPIOB[6] */
|
||||
#define SYS_PB_L_MFP_PB6_MFP_UART1_RTS (1UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - UART1 RTSn */
|
||||
#define SYS_PB_L_MFP_PB6_MFP_EBI_ALE (2UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - EBI ALE */
|
||||
#define SYS_PB_L_MFP_PB6_MFP_SPI2_MISO0 (4UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - SPI2 MISO[0] */
|
||||
#define SYS_PB_L_MFP_PB6_MFP_LCD_S11 (7UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - LCD SEG 11 */
|
||||
#define SYS_PB_L_MFP_PB6_MFP_LCD_S3 (7UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - LCD SEG 3 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB5_MFP_GPB5 (0UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - GPIOB[5] */
|
||||
#define SYS_PB_L_MFP_PB5_MFP_UART1_TX (1UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - UART1 TX */
|
||||
#define SYS_PB_L_MFP_PB5_MFP_SC0_RST (3UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - SmartCard0 RST */
|
||||
#define SYS_PB_L_MFP_PB5_MFP_SPI2_SCLK (4UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - SPI2 SCLK */
|
||||
#define SYS_PB_L_MFP_PB5_MFP_LCD_S12 (7UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - LCD SEG 12 */
|
||||
#define SYS_PB_L_MFP_PB5_MFP_LCD_S4 (7UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - LCD SEG 4 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB4_MFP_GPB4 (0UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - GPIOB[4] */
|
||||
#define SYS_PB_L_MFP_PB4_MFP_UART1_RX (1UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - UART1 RX */
|
||||
#define SYS_PB_L_MFP_PB4_MFP_SC0_CD (3UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - SmartCard0 card detection */
|
||||
#define SYS_PB_L_MFP_PB4_MFP_SPI2_SS0 (4UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - SPI2 chip selection 0 */
|
||||
#define SYS_PB_L_MFP_PB4_MFP_LCD_S13 (7UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - LCD SEG 13 */
|
||||
#define SYS_PB_L_MFP_PB4_MFP_LCD_S5 (7UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - LCD SEG 5 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB3_MFP_GPB3 (0UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - GPIOB[3] */
|
||||
#define SYS_PB_L_MFP_PB3_MFP_UART0_CTS (1UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - UART0 CTSn */
|
||||
#define SYS_PB_L_MFP_PB3_MFP_EBI_NWRH (2UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - EBI nWRH */
|
||||
#define SYS_PB_L_MFP_PB3_MFP_SPI1_SS0 (3UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - SPI1 chip selection 0 */
|
||||
#define SYS_PB_L_MFP_PB3_MFP_LCD_S4 (7UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - LCD SEG 4 */
|
||||
#define SYS_PB_L_MFP_PB3_MFP_LCD_COM2 (7UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - LCD COM 2 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB2_MFP_GPB2 (0UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - GPIOB[2] */
|
||||
#define SYS_PB_L_MFP_PB2_MFP_UART0_RTS (1UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - UART0 RTSn */
|
||||
#define SYS_PB_L_MFP_PB2_MFP_EBI_NWRL (2UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - EBI nWRL */
|
||||
#define SYS_PB_L_MFP_PB2_MFP_SPI1_SCLK (3UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - SPI1 SCLK */
|
||||
#define SYS_PB_L_MFP_PB2_MFP_LCD_S5 (7UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - LCD SEG 5 */
|
||||
#define SYS_PB_L_MFP_PB2_MFP_LCD_COM3 (7UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - LCD COM 3 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB1_MFP_GPB1 (0UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - GPIOB[1] */
|
||||
#define SYS_PB_L_MFP_PB1_MFP_UART0_TX (1UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - UART0 TX */
|
||||
#define SYS_PB_L_MFP_PB1_MFP_SPI1_MISO0 (3UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - SPI1 MISO[0] */
|
||||
#define SYS_PB_L_MFP_PB1_MFP_LCD_S6 (7UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - LCD SEG 6 */
|
||||
#define SYS_PB_L_MFP_PB1_MFP_LCD_S0 (7UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - LCD SEG 0 */
|
||||
|
||||
#define SYS_PB_L_MFP_PB0_MFP_GPB0 (0UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - GPIOB[0] */
|
||||
#define SYS_PB_L_MFP_PB0_MFP_UART0_RX (1UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - UART0 RX */
|
||||
#define SYS_PB_L_MFP_PB0_MFP_SPI1_MOSI0 (3UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - SPI1 MOSI[0] */
|
||||
#define SYS_PB_L_MFP_PB0_MFP_LCD_S7 (7UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - LCD SEG 7 */
|
||||
#define SYS_PB_L_MFP_PB0_MFP_LCD_S1 (7UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - LCD SEG 1 */
|
||||
|
||||
/********************* Bit definition of PB_H_MFP register **********************/
|
||||
#define SYS_PB_H_MFP_PB15_MFP_GPB15 (0UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - GPIOB[15] */
|
||||
#define SYS_PB_H_MFP_PB15_MFP_EXT_INT1 (1UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - External interrupt 1 */
|
||||
#define SYS_PB_H_MFP_PB15_MFP_SNOOPER (3UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - Snooper pin */
|
||||
#define SYS_PB_H_MFP_PB15_MFP_SC1_CD (4UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - SmartCard1 card detect */
|
||||
#define SYS_PB_H_MFP_PB15_MFP_LCD_S31 (7UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - LCD SEG 31 */
|
||||
#define SYS_PB_H_MFP_PB15_MFP_LCD_S14 (7UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - LCD SEG 14 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB14_MFP_GPB14 (0UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - GPIOB[14] */
|
||||
#define SYS_PB_H_MFP_PB14_MFP_EXT_INT0 (1UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - External interrupt 0 */
|
||||
#define SYS_PB_H_MFP_PB14_MFP_SC2_CD (3UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - SmartCard 2 card detect */
|
||||
#define SYS_PB_H_MFP_PB14_MFP_SPI2_SS1 (4UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - SPI2 2nd chip selection */
|
||||
#define SYS_PB_H_MFP_PB14_MFP_LCD_S26 (7UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - LCD SEG 26 */
|
||||
#define SYS_PB_H_MFP_PB14_MFP_LCD_S12 (7UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - LCD SEG 12 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB13_MFP_GPB13 (0UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - GPIOB[13] */
|
||||
#define SYS_PB_H_MFP_PB13_MFP_EBI_AD1 (2UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - EBI AD[1] */
|
||||
#define SYS_PB_H_MFP_PB13_MFP_LCD_S25 (7UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - LCD SEG 25 */
|
||||
#define SYS_PB_H_MFP_PB13_MFP_LCD_S11 (7UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - LCD SEG 11 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB12_MFP_GPB12 (0UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - GPIOB[12] */
|
||||
#define SYS_PB_H_MFP_PB12_MFP_EBI_AD0 (2UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - EBI AD[0] */
|
||||
#define SYS_PB_H_MFP_PB12_MFP_CKO (4UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - CKO */
|
||||
#define SYS_PB_H_MFP_PB12_MFP_LCD_S24 (7UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - LCD SEG 24 */
|
||||
#define SYS_PB_H_MFP_PB12_MFP_LCD_S10 (7UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - LCD SEG 10 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB11_MFP_GPB11 (0UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - GPIOB[11] */
|
||||
#define SYS_PB_H_MFP_PB11_MFP_PWM1_CH0 (1UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - PWM1 Channel 0 */
|
||||
#define SYS_PB_H_MFP_PB11_MFP_TMR3_EXT (2UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - Timer3 external event input */
|
||||
#define SYS_PB_H_MFP_PB11_MFP_TMR3_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - Timer3 toggle output */
|
||||
#define SYS_PB_H_MFP_PB11_MFP_SC2_DAT (4UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - SmartCard2 DATA */
|
||||
#define SYS_PB_H_MFP_PB11_MFP_SPI0_MISO0 (5UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - SPI 0 MISO[0] */
|
||||
#define SYS_PB_H_MFP_PB11_MFP_LCD_V1 (7UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - LCD V1 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB10_MFP_GPB10 (0UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - GPIOB[10] */
|
||||
#define SYS_PB_H_MFP_PB10_MFP_SPI0_SS1 (1UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - SPI0 chip selection 1 */
|
||||
#define SYS_PB_H_MFP_PB10_MFP_TMR2_EXT (2UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - Timer2 external event input */
|
||||
#define SYS_PB_H_MFP_PB10_MFP_TMR2_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - Timer2 toggle output */
|
||||
#define SYS_PB_H_MFP_PB10_MFP_SC2_CLK (4UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - SmartCard2 clock */
|
||||
#define SYS_PB_H_MFP_PB10_MFP_SPI0_MOSI0 (5UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - SPI0 MOSI[0] */
|
||||
#define SYS_PB_H_MFP_PB10_MFP_LCD_V2 (7UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - LCD V2 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB9_MFP_GPB9 (0UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - GPIOB[9] */
|
||||
#define SYS_PB_H_MFP_PB9_MFP_SPI1_SS1 (1UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - SPI1 chip selection 1 */
|
||||
#define SYS_PB_H_MFP_PB9_MFP_TMR1_EXT (2UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - Timer1 external event input */
|
||||
#define SYS_PB_H_MFP_PB9_MFP_TMR1_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - Timer1 toggle output */
|
||||
#define SYS_PB_H_MFP_PB9_MFP_SC2_RST (4UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - SmartCard2 RST */
|
||||
#define SYS_PB_H_MFP_PB9_MFP_EXT_INT0 (5UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - External interrupt 0 */
|
||||
#define SYS_PB_H_MFP_PB9_MFP_LCD_V3 (7UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - LCD V3 */
|
||||
|
||||
#define SYS_PB_H_MFP_PB8_MFP_GPB8 (0UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - GPIOB[8] */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_ADC_EXT (1UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - ADC external trigger */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_TMR0_EXT (2UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - Timer0 external event input */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_TMR0_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - Timer0 toggle output */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_EXT_INT0 (3UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - External interrupt 0 */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_SC2_PWR (4UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - SmartCard 2 power */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_LCD_S30 (7UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - LCD SEG 30 */
|
||||
#define SYS_PB_H_MFP_PB8_MFP_LCD_S13 (7UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - LCD SEG 13 */
|
||||
|
||||
/********************* Bit definition of PC_L_MFP register **********************/
|
||||
#define SYS_PC_L_MFP_PC7_MFP_GPC7 (0UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - GPIOC[7] */
|
||||
#define SYS_PC_L_MFP_PC7_MFP_DA_OUT1 (1UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - DA out1 */
|
||||
#define SYS_PC_L_MFP_PC7_MFP_EBI_AD5 (2UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - EBI AD[5] */
|
||||
#define SYS_PC_L_MFP_PC7_MFP_TMR1_CAP (3UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - Timer1 capture event */
|
||||
#define SYS_PC_L_MFP_PC7_MFP_PWM0_CH1 (5UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - PWM0 Channel 1 */
|
||||
#define SYS_PC_L_MFP_PC7_MFP_LCD_S17 (7UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - LCD SEG 17 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC6_MFP_GPC6 (0UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - GPIOC[6] */
|
||||
#define SYS_PC_L_MFP_PC6_MFP_DA_OUT0 (1UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - DA out0 */
|
||||
#define SYS_PC_L_MFP_PC6_MFP_EBI_AD4 (2UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - EBI AD[4] */
|
||||
#define SYS_PC_L_MFP_PC6_MFP_TMR0_CAP (3UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - Timer0 Capture event */
|
||||
#define SYS_PC_L_MFP_PC6_MFP_SC1_CD (4UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - SmartCard1 card detection */
|
||||
#define SYS_PC_L_MFP_PC6_MFP_PWM0_CH0 (5UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - PWM0 Channel 0 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC5_MFP_GPC5 (0UL<<SYS_PC_L_MFP_PC5_MFP_Pos) /*!<PC5 Pin Function - GPIOC[5] */
|
||||
#define SYS_PC_L_MFP_PC5_MFP_SPI0_MOSI1 (1UL<<SYS_PC_L_MFP_PC5_MFP_Pos) /*!<PC5 Pin Function - SPI0 MOSI[1] */
|
||||
#define SYS_PC_L_MFP_PC5_MFP_LCD_COM3 (7UL<<SYS_PC_L_MFP_PC5_MFP_Pos) /*!<PC5 Pin Function - LCD COM 3 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC4_MFP_GPC4 (0UL<<SYS_PC_L_MFP_PC4_MFP_Pos) /*!<PC4 Pin Function - GPIOC[4] */
|
||||
#define SYS_PC_L_MFP_PC4_MFP_SPI0_MISO1 (1UL<<SYS_PC_L_MFP_PC4_MFP_Pos) /*!<PC4 Pin Function - SPI0 MISO[1] */
|
||||
#define SYS_PC_L_MFP_PC4_MFP_LCD_COM2 (7UL<<SYS_PC_L_MFP_PC4_MFP_Pos) /*!<PC4 Pin Function - LCD COM 2 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC3_MFP_GPC3 (0UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - GPIOC[3] */
|
||||
#define SYS_PC_L_MFP_PC3_MFP_SPI0_MOSI0 (1UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - SPI0 MOSI[0] */
|
||||
#define SYS_PC_L_MFP_PC3_MFP_I2S_DOUT (2UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - I2S Dout */
|
||||
#define SYS_PC_L_MFP_PC3_MFP_SC1_RST (4UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - SmartCard1 RST */
|
||||
#define SYS_PC_L_MFP_PC3_MFP_LCD_COM1 (7UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - LCD COM 1 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC2_MFP_GPC2 (0UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - GPIOC[2] */
|
||||
#define SYS_PC_L_MFP_PC2_MFP_SPI0_MISO0 (1UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - SPI0 MISO[0] */
|
||||
#define SYS_PC_L_MFP_PC2_MFP_I2S_DIN (2UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - I2S Din */
|
||||
#define SYS_PC_L_MFP_PC2_MFP_SC1_PWR (4UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - SmartCard1 Power */
|
||||
#define SYS_PC_L_MFP_PC2_MFP_LCD_COM0 (7UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - LCD COM 0 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC1_MFP_GPC1 (0UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - GPIOC[1] */
|
||||
#define SYS_PC_L_MFP_PC1_MFP_SPI0_SCLK (1UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - SPI0 SCLK */
|
||||
#define SYS_PC_L_MFP_PC1_MFP_I2S_BCLK (2UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - I2S BCLK */
|
||||
#define SYS_PC_L_MFP_PC1_MFP_SC1_DAT (4UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - SmartCard1 DATA */
|
||||
#define SYS_PC_L_MFP_PC1_MFP_LCD_DH2 (7UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - LCD DH2 */
|
||||
|
||||
#define SYS_PC_L_MFP_PC0_MFP_GPC0 (0UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - GPIOC[0] */
|
||||
#define SYS_PC_L_MFP_PC0_MFP_SPI0_SS0 (1UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - SPI0 chip selection 0 */
|
||||
#define SYS_PC_L_MFP_PC0_MFP_I2S_WS (2UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - I2S WS */
|
||||
#define SYS_PC_L_MFP_PC0_MFP_SC1_CLK (4UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - SmartCard1 clock */
|
||||
#define SYS_PC_L_MFP_PC0_MFP_LCD_DH1 (7UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - LCD DH1 */
|
||||
|
||||
/********************* Bit definition of PC_H_MFP register **********************/
|
||||
#define SYS_PC_H_MFP_PC15_MFP_GPC15 (0UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - GPIOC[15] */
|
||||
#define SYS_PC_H_MFP_PC15_MFP_EBI_AD3 (2UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - EBI AD[3] */
|
||||
#define SYS_PC_H_MFP_PC15_MFP_TMR0_CAP (3UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - Timer0 capture event */
|
||||
#define SYS_PC_H_MFP_PC15_MFP_PWM1_CH2 (4UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - PWM1 Channel 2 */
|
||||
#define SYS_PC_H_MFP_PC15_MFP_LCD_S33 (7UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - LCD SEG 33 */
|
||||
#define SYS_PC_H_MFP_PC15_MFP_LCD_S16 (7UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - LCD SEG 16 */
|
||||
|
||||
#define SYS_PC_H_MFP_PC14_MFP_GPC14 (0UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - GPIOC[14] */
|
||||
#define SYS_PC_H_MFP_PC14_MFP_EBI_AD2 (2UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - EBI AD[2] */
|
||||
#define SYS_PC_H_MFP_PC14_MFP_PWM1_CH3 (4UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - PWM1 Channel 3 */
|
||||
#define SYS_PC_H_MFP_PC14_MFP_LCD_S32 (7UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - LCD SEG 32 */
|
||||
#define SYS_PC_H_MFP_PC14_MFP_LCD_S15 (7UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - LCD SEG 15 */
|
||||
|
||||
#define SYS_PC_H_MFP_PC13_MFP_GPC13 (0UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - GPIOC[13] */
|
||||
#define SYS_PC_H_MFP_PC13_MFP_SPI1_MOSI1 (1UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - SPI1 MOSI[1] */
|
||||
#define SYS_PC_H_MFP_PC13_MFP_PWM1_CH1 (2UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - PWM1 Channel 1 */
|
||||
#define SYS_PC_H_MFP_PC13_MFP_SNOOPER (4UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - Snooper pin */
|
||||
#define SYS_PC_H_MFP_PC13_MFP_EXT_INT1 (5UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - External interrupt 1 */
|
||||
#define SYS_PC_H_MFP_PC13_MFP_I2C0_SCL (6UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - I2C0 clock */
|
||||
|
||||
#define SYS_PC_H_MFP_PC12_MFP_GPC12 (0UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - GPIOC[12] */
|
||||
#define SYS_PC_H_MFP_PC12_MFP_SPI1_MISO1 (1UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - SPI1 MISO[1] */
|
||||
#define SYS_PC_H_MFP_PC12_MFP_PWM1_CH0 (2UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - PWM1 Channel 0 */
|
||||
#define SYS_PC_H_MFP_PC12_MFP_EXT_INT0 (5UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - External interrupt 0 */
|
||||
#define SYS_PC_H_MFP_PC12_MFP_I2C0_SDA (6UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - I2C0 DATA */
|
||||
|
||||
#define SYS_PC_H_MFP_PC11_MFP_GPC11 (0UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - GPIOC[11] */
|
||||
#define SYS_PC_H_MFP_PC11_MFP_SPI1_MOSI0 (1UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - SPI1 MOSI[0] */
|
||||
#define SYS_PC_H_MFP_PC11_MFP_UART1_TX (5UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - UART1 TX */
|
||||
#define SYS_PC_H_MFP_PC11_MFP_LCD_S31 (7UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - LCD SEG 31 */
|
||||
|
||||
#define SYS_PC_H_MFP_PC10_MFP_GPC10 (0UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - GPIOC[10] */
|
||||
#define SYS_PC_H_MFP_PC10_MFP_SPI1_MISO0 (1UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - SPI1 MISO[0] */
|
||||
#define SYS_PC_H_MFP_PC10_MFP_UART1_RX (5UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - UART1 RX */
|
||||
#define SYS_PC_H_MFP_PC10_MFP_LCD_S30 (7UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - LCD SEG 30 */
|
||||
|
||||
#define SYS_PC_H_MFP_PC9_MFP_GPC9 (0UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - GPIOC[9] */
|
||||
#define SYS_PC_H_MFP_PC9_MFP_SPI1_SCLK (1UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - SPI1 SCLK */
|
||||
#define SYS_PC_H_MFP_PC9_MFP_I2C1_SCL (5UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - I2C1 clock */
|
||||
#define SYS_PC_H_MFP_PC9_MFP_LCD_S29 (7UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - LCD SEG 29 */
|
||||
|
||||
#define SYS_PC_H_MFP_PC8_MFP_GPC8 (0UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - GPIOC[8] */
|
||||
#define SYS_PC_H_MFP_PC8_MFP_SPI1_SS0 (1UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - SPI1 SS[0] */
|
||||
#define SYS_PC_H_MFP_PC8_MFP_EBI_XCLK (2UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - EBI XCLK */
|
||||
#define SYS_PC_H_MFP_PC8_MFP_I2C1_SDA (5UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - I2C1 DATA */
|
||||
#define SYS_PC_H_MFP_PC8_MFP_LCD_S28 (7UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - LCD SEG 28 */
|
||||
|
||||
/********************* Bit definition of PD_L_MFP register **********************/
|
||||
#define SYS_PD_L_MFP_PD7_MFP_GPD7 (0UL<<SYS_PD_L_MFP_PD7_MFP_Pos) /*!<PD7 Pin Function - GPIOD[7] */
|
||||
#define SYS_PD_L_MFP_PD7_MFP_LCD_S2 (7UL<<SYS_PD_L_MFP_PD7_MFP_Pos) /*!<PD7 Pin Function - LCD SEG 2 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD6_MFP_GPD6 (0UL<<SYS_PD_L_MFP_PD6_MFP_Pos) /*!<PD6 Pin Function - GPIOD[6] */
|
||||
#define SYS_PD_L_MFP_PD6_MFP_LCD_S3 (7UL<<SYS_PD_L_MFP_PD6_MFP_Pos) /*!<PD6 Pin Function - LCD SEG 3 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD5_MFP_GPD5 (0UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - GPIOD[5] */
|
||||
#define SYS_PD_L_MFP_PD5_MFP_I2S_DOUT (2UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - I2S Dout */
|
||||
#define SYS_PD_L_MFP_PD5_MFP_SPI2_MOSI1 (3UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - SPI2 MOSI[1] */
|
||||
#define SYS_PD_L_MFP_PD5_MFP_LCD_S34 (7UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - LCD SEG 34 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD4_MFP_GPD4 (0UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - GPIOD[4] */
|
||||
#define SYS_PD_L_MFP_PD4_MFP_I2S_DIN (2UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - I2S Din */
|
||||
#define SYS_PD_L_MFP_PD4_MFP_SPI2_MISO1 (3UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - SPI2 MISO[1] */
|
||||
#define SYS_PD_L_MFP_PD4_MFP_SC1_CD (4UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - SmartCard1 card detection */
|
||||
#define SYS_PD_L_MFP_PD4_MFP_LCD_S35 (7UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - LCD SEG 35 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD3_MFP_GPD3 (0UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - GPIOD[3] */
|
||||
#define SYS_PD_L_MFP_PD3_MFP_UART1_CTS (1UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - UART1 CTSn */
|
||||
#define SYS_PD_L_MFP_PD3_MFP_I2S_BCLK (2UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - I2S BCLK */
|
||||
#define SYS_PD_L_MFP_PD3_MFP_SPI2_MOSI0 (3UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - SPI2 MOSI[0] */
|
||||
#define SYS_PD_L_MFP_PD3_MFP_SC1_RST (4UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - SmartCard1 reset */
|
||||
#define SYS_PD_L_MFP_PD3_MFP_ADC_CH11 (5UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - ADC input channel 11 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD2_MFP_GPD2 (0UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - GPIOD[2] */
|
||||
#define SYS_PD_L_MFP_PD2_MFP_UART1_RTS (1UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - UART1 RTSn */
|
||||
#define SYS_PD_L_MFP_PD2_MFP_I2S_WS (2UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - I2S WS */
|
||||
#define SYS_PD_L_MFP_PD2_MFP_SPI2_MISO0 (3UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - SPI2 MISO[0] */
|
||||
#define SYS_PD_L_MFP_PD2_MFP_SC1_PWR (4UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - SmartCard1 power */
|
||||
#define SYS_PD_L_MFP_PD2_MFP_ADC_CH10 (5UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - ADC input channel 10 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD1_MFP_GPD1 (0UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - GPIOD[1] */
|
||||
#define SYS_PD_L_MFP_PD1_MFP_UART1_TX (1UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - UART1 TX */
|
||||
#define SYS_PD_L_MFP_PD1_MFP_SPI2_SCLK (3UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - SPI2 SCLK */
|
||||
#define SYS_PD_L_MFP_PD1_MFP_SC1_DAT (4UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - SmartCard1 DATA */
|
||||
#define SYS_PD_L_MFP_PD1_MFP_ADC_CH9 (5UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - ADC input channel 9 */
|
||||
|
||||
#define SYS_PD_L_MFP_PD0_MFP_GPD0 (0UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - GPIOD[0] */
|
||||
#define SYS_PD_L_MFP_PD0_MFP_UART1_RX (1UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - UART1 RX */
|
||||
#define SYS_PD_L_MFP_PD0_MFP_SPI2_SS0 (3UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - SPI2 chip selection 0 */
|
||||
#define SYS_PD_L_MFP_PD0_MFP_SC1_CLK (4UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - SmartCard1 clock */
|
||||
#define SYS_PD_L_MFP_PD0_MFP_ADC_CH8 (5UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - ADC input channel 8 */
|
||||
|
||||
/********************* Bit definition of PD_H_MFP register **********************/
|
||||
#define SYS_PD_H_MFP_PD15_MFP_GPD15 (0UL<<SYS_PD_H_MFP_PD15_MFP_Pos) /*!<PD15 Pin Function - GPIOD[15] */
|
||||
#define SYS_PD_H_MFP_PD15_MFP_LCD_S0 (7UL<<SYS_PD_H_MFP_PD15_MFP_Pos) /*!<PD15 Pin Function - LCD SEG 0 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD14_MFP_GPD14 (0UL<<SYS_PD_H_MFP_PD14_MFP_Pos) /*!<PD14 Pin Function - GPIOD[14] */
|
||||
#define SYS_PD_H_MFP_PD14_MFP_LCD_S1 (7UL<<SYS_PD_H_MFP_PD14_MFP_Pos) /*!<PD14 Pin Function - LCD SEG 1 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD13_MFP_GPD13 (0UL<<SYS_PD_H_MFP_PD13_MFP_Pos) /*!<PD13 Pin Function - GPIOD[13] */
|
||||
#define SYS_PD_H_MFP_PD13_MFP_LCD_S14 (7UL<<SYS_PD_H_MFP_PD13_MFP_Pos) /*!<PD13 Pin Function - LCD SEG 14 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD12_MFP_GPD12 (0UL<<SYS_PD_H_MFP_PD12_MFP_Pos) /*!<PD12 Pin Function - GPIOD[12] */
|
||||
#define SYS_PD_H_MFP_PD12_MFP_LCD_S15 (7UL<<SYS_PD_H_MFP_PD12_MFP_Pos) /*!<PD12 Pin Function - LCD SEG 15 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD11_MFP_GPD11 (0UL<<SYS_PD_H_MFP_PD11_MFP_Pos) /*!<PD11 Pin Function - GPIOD[11] */
|
||||
#define SYS_PD_H_MFP_PD11_MFP_LCD_S16 (7uL<<SYS_PD_H_MFP_PD11_MFP_Pos) /*!<PD11 Pin Function - LCD SEG 16 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD10_MFP_GPD10 (0UL<<SYS_PD_H_MFP_PD10_MFP_Pos) /*!<PD10 Pin Function - GPIOD[10] */
|
||||
#define SYS_PD_H_MFP_PD10_MFP_LCD_S17 (7UL<<SYS_PD_H_MFP_PD10_MFP_Pos) /*!<PD10 Pin Function - LCD SEG 17 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD9_MFP_GPD9 (0UL<<SYS_PD_H_MFP_PD9_MFP_Pos) /*!<PD9 Pin Function - GPIOD[9] */
|
||||
#define SYS_PD_H_MFP_PD9_MFP_LCD_S18 (7UL<<SYS_PD_H_MFP_PD9_MFP_Pos) /*!<PD9 Pin Function - LCD SEG 18 */
|
||||
|
||||
#define SYS_PD_H_MFP_PD8_MFP_GPD8 (0UL<<SYS_PD_H_MFP_PD8_MFP_Pos) /*!<PD8 Pin Function - GPIOD[8] */
|
||||
#define SYS_PD_H_MFP_PD8_MFP_LCD_S19 (7UL<<SYS_PD_H_MFP_PD8_MFP_Pos) /*!<PD8 Pin Function - LCD SEG 19 */
|
||||
|
||||
/********************* Bit definition of PE_L_MFP register **********************/
|
||||
#define SYS_PE_L_MFP_PE7_MFP_GPE7 (0UL<<SYS_PE_L_MFP_PE7_MFP_Pos) /*!<PE7 Pin Function - GPIOE[7] */
|
||||
#define SYS_PE_L_MFP_PE7_MFP_LCD_S8 (7UL<<SYS_PE_L_MFP_PE7_MFP_Pos) /*!<PE7 Pin Function - LCD SEG 8 */
|
||||
|
||||
#define SYS_PE_L_MFP_PE6_MFP_GPE6 (0UL<<SYS_PE_L_MFP_PE6_MFP_Pos) /*!<PE6 Pin Function - GPIOE[6] */
|
||||
|
||||
#define SYS_PE_L_MFP_PE5_MFP_GPE5 (0UL<<SYS_PE_L_MFP_PE5_MFP_Pos) /*!<PE5 Pin Function - GPIOE[5] */
|
||||
#define SYS_PE_L_MFP_PE5_MFP_PWM1_CH1 (1UL<<SYS_PE_L_MFP_PE5_MFP_Pos) /*!<PE5 Pin Function - PWM1 Channel 1 */
|
||||
|
||||
#define SYS_PE_L_MFP_PE4_MFP_GPE4 (0UL<<SYS_PE_L_MFP_PE4_MFP_Pos) /*!<PE4 Pin Function - GPIOE[4] */
|
||||
#define SYS_PE_L_MFP_PE4_MFP_SPI0_MOSI0 (6UL<<SYS_PE_L_MFP_PE4_MFP_Pos) /*!<PE4 Pin Function - SPI0 MOSI[0] */
|
||||
|
||||
#define SYS_PE_L_MFP_PE3_MFP_GPE3 (0UL<<SYS_PE_L_MFP_PE3_MFP_Pos) /*!<PE3 Pin Function - GPIOE[3] */
|
||||
#define SYS_PE_L_MFP_PE3_MFP_SPI0_MISO0 (6UL<<SYS_PE_L_MFP_PE3_MFP_Pos) /*!<PE3 Pin Function - SPI0 MISO[0] */
|
||||
|
||||
#define SYS_PE_L_MFP_PE2_MFP_GPE2 (0UL<<SYS_PE_L_MFP_PE2_MFP_Pos) /*!<PE2 Pin Function - GPIOE[2] */
|
||||
#define SYS_PE_L_MFP_PE2_MFP_SPI0_SCLK (6UL<<SYS_PE_L_MFP_PE2_MFP_Pos) /*!<PE2 Pin Function - SPI0 SCLK */
|
||||
|
||||
#define SYS_PE_L_MFP_PE1_MFP_GPE1 (0UL<<SYS_PE_L_MFP_PE1_MFP_Pos) /*!<PE1 Pin Function - GPIOE[1] */
|
||||
#define SYS_PE_L_MFP_PE1_MFP_PWM1_CH3 (1UL<<SYS_PE_L_MFP_PE1_MFP_Pos) /*!<PE1 Pin Function - PWM1 Channel 3 */
|
||||
#define SYS_PE_L_MFP_PE1_MFP_SPI0_SS0 (6UL<<SYS_PE_L_MFP_PE1_MFP_Pos) /*!<PE1 Pin Function - SPI0 chip selection 0 */
|
||||
|
||||
#define SYS_PE_L_MFP_PE0_MFP_GPE0 (0UL<<SYS_PE_L_MFP_PE0_MFP_Pos) /*!<PE0 Pin Function - GPIOE[0] */
|
||||
#define SYS_PE_L_MFP_PE0_MFP_PWM1_CH2 (1UL<<SYS_PE_L_MFP_PE0_MFP_Pos) /*!<PE0 Pin Function - PWM1 Channel 2 */
|
||||
#define SYS_PE_L_MFP_PE0_MFP_I2S_MCLK (2UL<<SYS_PE_L_MFP_PE0_MFP_Pos) /*!<PE0 Pin Function - I2S MCLK */
|
||||
|
||||
/********************* Bit definition of PE_H_MFP register **********************/
|
||||
#define SYS_PE_H_MFP_PE15_MFP_GPE15 (0UL<<SYS_PE_H_MFP_PE15_MFP_Pos) /*!<PE15 Pin Function - GPIOE[15] */
|
||||
#define SYS_PE_H_MFP_PE15_MFP_LCD_S29 (7UL<<SYS_PE_H_MFP_PE15_MFP_Pos) /*!<PE15 Pin Function - LCD SEG 29 */
|
||||
|
||||
#define SYS_PE_H_MFP_PE14_MFP_GPE14 (0UL<<SYS_PE_H_MFP_PE14_MFP_Pos) /*!<PE14 Pin Function - GPIOE[14] */
|
||||
#define SYS_PE_H_MFP_PE14_MFP_LCD_S28 (7UL<<SYS_PE_H_MFP_PE14_MFP_Pos) /*!<PE14 Pin Function - LCD SEG 28 */
|
||||
|
||||
#define SYS_PE_H_MFP_PE13_MFP_GPE13 (0UL<<SYS_PE_H_MFP_PE13_MFP_Pos) /*!<PE13 Pin Function - GPIOE[13] */
|
||||
#define SYS_PE_H_MFP_PE13_MFP_LCD_S27 (7UL<<SYS_PE_H_MFP_PE13_MFP_Pos) /*!<PE13 Pin Function - LCD SEG 27 */
|
||||
|
||||
#define SYS_PE_H_MFP_PE12_MFP_GPE12 (0UL<<SYS_PE_H_MFP_PE12_MFP_Pos) /*!<PE12 Pin Function - GPIOE[12] */
|
||||
#define SYS_PE_H_MFP_PE12_MFP_UART1_CTS (7UL<<SYS_PE_H_MFP_PE12_MFP_Pos) /*!<PE12 Pin Function - UART1 CTSn */
|
||||
|
||||
#define SYS_PE_H_MFP_PE11_MFP_GPE11 (0UL<<SYS_PE_H_MFP_PE11_MFP_Pos) /*!<PE11 Pin Function - GPIOE[11] */
|
||||
#define SYS_PE_H_MFP_PE11_MFP_UART1_RTS (7UL<<SYS_PE_H_MFP_PE11_MFP_Pos) /*!<PE11 Pin Function - UART1 RTSn */
|
||||
|
||||
#define SYS_PE_H_MFP_PE10_MFP_GPE10 (0UL<<SYS_PE_H_MFP_PE10_MFP_Pos) /*!<PE10 Pin Function - GPIOE[10] */
|
||||
#define SYS_PE_H_MFP_PE10_MFP_UART1_TX (7UL<<SYS_PE_H_MFP_PE10_MFP_Pos) /*!<PE10 Pin Function - UART1 TX */
|
||||
|
||||
#define SYS_PE_H_MFP_PE9_MFP_GPE9 (0UL<<SYS_PE_H_MFP_PE9_MFP_Pos) /*!<PE9 Pin Function - GPIOE[9] */
|
||||
#define SYS_PE_H_MFP_PE9_MFP_UART1_RX (7UL<<SYS_PE_H_MFP_PE9_MFP_Pos) /*!<PE9 Pin Function - UART1 RX */
|
||||
|
||||
#define SYS_PE_H_MFP_PE8_MFP_GPE8 (0UL<<SYS_PE_H_MFP_PE8_MFP_Pos) /*!<PE8 Pin Function - GPIOA[8] */
|
||||
#define SYS_PE_H_MFP_PE8_MFP_LCD_S9 (7UL<<SYS_PE_H_MFP_PE8_MFP_Pos) /*!<PE8 Pin Function - LCD SEG 9 */
|
||||
|
||||
/********************* Bit definition of PF_L_MFP register **********************/
|
||||
#define SYS_PF_L_MFP_PF5_MFP_GPF5 (0UL<<SYS_PF_L_MFP_PF5_MFP_Pos) /*!<PF5 Pin Function - GPIOF[5] */
|
||||
#define SYS_PF_L_MFP_PF5_MFP_I2C0_SCL (1UL<<SYS_PF_L_MFP_PF5_MFP_Pos) /*!<PF5 Pin Function - I2C0 clock */
|
||||
|
||||
#define SYS_PF_L_MFP_PF4_MFP_GPF4 (0UL<<SYS_PF_L_MFP_PF4_MFP_Pos) /*!<PF4 Pin Function - GPIOF[4] */
|
||||
#define SYS_PF_L_MFP_PF4_MFP_I2C0_SDA (1UL<<SYS_PF_L_MFP_PF4_MFP_Pos) /*!<PF4 Pin Function - I2C0 DATA */
|
||||
|
||||
#define SYS_PF_L_MFP_PF3_MFP_GPF3 (0UL<<SYS_PF_L_MFP_PF3_MFP_Pos) /*!<PF3 Pin Function - GPIOF[3] */
|
||||
#define SYS_PF_L_MFP_PF3_MFP_HXT_IN (7UL<<SYS_PF_L_MFP_PF3_MFP_Pos) /*!<PF3 Pin Function - HXT IN */
|
||||
|
||||
#define SYS_PF_L_MFP_PF2_MFP_GPF2 (0UL<<SYS_PF_L_MFP_PF2_MFP_Pos) /*!<PF2 Pin Function - GPIOF[2] */
|
||||
#define SYS_PF_L_MFP_PF2_MFP_HXT_OUT (7UL<<SYS_PF_L_MFP_PF2_MFP_Pos) /*!<PF2 Pin Function - HXT OUT */
|
||||
|
||||
#define SYS_PF_L_MFP_PF1_MFP_GPF1 (0UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - GPIOF[1] */
|
||||
#define SYS_PF_L_MFP_PF1_MFP_CKO (4UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - CKO */
|
||||
#define SYS_PF_L_MFP_PF1_MFP_EXT_INT1 (5UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - External interrupt 1 */
|
||||
#define SYS_PF_L_MFP_PF1_MFP_ICE_CLK (7UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - ICE CLOCK */
|
||||
|
||||
#define SYS_PF_L_MFP_PF0_MFP_GPF0 (0UL<<SYS_PF_L_MFP_PF0_MFP_Pos) /*!<PF0 Pin Function - GPIOF[0] */
|
||||
#define SYS_PF_L_MFP_PF0_MFP_EXT_INT0 (5UL<<SYS_PF_L_MFP_PF0_MFP_Pos) /*!<PF0 Pin Function - External interrupt 0 */
|
||||
#define SYS_PF_L_MFP_PF0_MFP_ICE_DAT (7UL<<SYS_PF_L_MFP_PF0_MFP_Pos) /*!<PF0 Pin Function - ICE DATA */
|
||||
|
||||
/*@}*/ /* end of group NANO100_SYS_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup NANO100_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear Brown-out detector interrupt flag
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro clear Brown-out detector interrupt flag.
|
||||
*/
|
||||
#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODSTS |= SYS_BODSTS_BOD_INT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out 2.5V detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro disable Brown-out 2.5V detector function.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD25() (SYS->BODCTL &= ~SYS_BODCTL_BOD25_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out 2.5V detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out 2.5V detector function.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD25() (SYS->BODCTL |= SYS_BODCTL_BOD25_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out 2.0V detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro disable Brown-out 2.0V detector function.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD20() (SYS->BODCTL &= ~SYS_BODCTL_BOD20_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out 2.0V detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out 2.0V detector function.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD20() (SYS->BODCTL |= SYS_BODCTL_BOD20_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out 1.7V detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro disable Brown-out 1.7V detector function.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD17() (SYS->BODCTL &= ~SYS_BODCTL_BOD17_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out 1.7V detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out 1.7V detector function.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD17() (SYS->BODCTL |= SYS_BODCTL_BOD17_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out detector interrupt flag
|
||||
* @param None
|
||||
* @retval 0 Brown-out detect interrupt flag is not set.
|
||||
* @retval >=1 Brown-out detect interrupt flag is set.
|
||||
* @details This macro get Brown-out detector interrupt flag.
|
||||
*/
|
||||
#define SYS_GET_BOD_INT_FLAG() (SYS->BODSTS & SYS_BODSTS_BOD_INT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out 2.5V detector status
|
||||
* @param None
|
||||
* @retval 0 System voltage is higher than 2.5V setting or BOD_EN is 0.
|
||||
* @retval >=1 System voltage is lower than 2.5V setting.
|
||||
* @details This macro get Brown-out detector output status.
|
||||
* If the BOD_EN is 0, this function always return 0.
|
||||
*/
|
||||
#define SYS_GET_BOD25_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD25_drop_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out 2.0V detector status
|
||||
* @param None
|
||||
* @retval 0 System voltage is higher than 2.0V setting or BOD_EN is 0.
|
||||
* @retval >=1 System voltage is lower than 2.0V setting.
|
||||
* @details This macro get Brown-out detector output status.
|
||||
* If the BOD_EN is 0, this function always return 0.
|
||||
*/
|
||||
#define SYS_GET_BOD20_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD20_drop_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out 1.7V detector status
|
||||
* @param None
|
||||
* @retval 0 System voltage is higher than 1.7V setting or BOD_EN is 0.
|
||||
* @retval >=1 System voltage is lower than 1.7V setting.
|
||||
* @details This macro get Brown-out detector output status.
|
||||
* If the BOD_EN is 0, this function always return 0.
|
||||
*/
|
||||
#define SYS_GET_BOD17_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD17_drop_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out 2.5V detector interrupt function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detector interrupt function.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD25_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD25_RST_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out 2.5V detector reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detect reset function.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD25_RST() (SYS->BODCTL |= SYS_BODCTL_BOD25_RST_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out 2.0V detector interrupt function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detector interrupt function.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD20_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD20_RST_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out 2.0V detector reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detect reset function.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD20_RST() (SYS->BODCTL |= SYS_BODCTL_BOD20_RST_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out 1.7V detector interrupt function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detector interrupt function.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD17_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD17_RST_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out 1.7V detector reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detect reset function.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD17_RST() (SYS->BODCTL |= SYS_BODCTL_BOD17_RST_EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from Brown-out detector reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from Brown-out detector reset
|
||||
* @retval >=1 Previous reset source is from Brown-out detector reset
|
||||
* @details This macro get previous reset source is from Brown-out detect reset or not.
|
||||
*/
|
||||
#define SYS_IS_BOD_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_BOD_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from CPU reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from CPU reset
|
||||
* @retval >=1 Previous reset source is from CPU reset
|
||||
* @details This macro get previous reset source is from CPU reset.
|
||||
*/
|
||||
#define SYS_IS_CPU_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_CPU_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from Power-on Reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from Power-on Reset
|
||||
* @retval >=1 Previous reset source is from Power-on Reset
|
||||
* @details This macro get previous reset source is from Power-on Reset.
|
||||
*/
|
||||
#define SYS_IS_POR_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_POR_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from reset pin reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from reset pin reset
|
||||
* @retval >=1 Previous reset source is from reset pin reset
|
||||
* @details This macro get previous reset source is from reset pin reset.
|
||||
*/
|
||||
#define SYS_IS_RSTPIN_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_PAD_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from system reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from system reset
|
||||
* @retval >=1 Previous reset source is from system reset
|
||||
* @details This macro get previous reset source is from system reset.
|
||||
*/
|
||||
#define SYS_IS_SYSTEM_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_SYS_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from window watch dog reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from window watch dog reset
|
||||
* @retval >=1 Previous reset source is from window watch dog reset
|
||||
* @details This macro get previous reset source is from window watch dog reset.
|
||||
*/
|
||||
#define SYS_IS_WDT_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_WDT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Power-on Reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro disable Power-on Reset function.
|
||||
*/
|
||||
#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
|
||||
|
||||
/**
|
||||
* @brief Enable Power-on Reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Power-on Reset function.
|
||||
*/
|
||||
#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear reset source flag
|
||||
* @param[in] u32RstSrc is reset source. Including:
|
||||
* - \ref SYS_RST_SRC_RSTS_POR_Msk
|
||||
* - \ref SYS_RST_SRC_RSTS_PAD_Msk
|
||||
* - \ref SYS_RST_SRC_RSTS_WDT_Msk
|
||||
* - \ref SYS_RST_SRC_RSTS_BOD_Msk
|
||||
* - \ref SYS_RST_SRC_RSTS_SYS_Msk
|
||||
* - \ref SYS_RST_SRC_RSTS_CPU_Msk
|
||||
* @return None
|
||||
* @details This macro clear reset source flag.
|
||||
*/
|
||||
#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RST_SRC = u32RstSrc )
|
||||
|
||||
/**
|
||||
* @brief Get HIRC trim status
|
||||
* @param None
|
||||
* @retval BIT0 HIRC Frequency Lock
|
||||
* @retval BIT1 Trim Failure Interrupt
|
||||
* @retval BIT2 LXT Clock error
|
||||
* @details This macro get HIRC trim interrupt status register.
|
||||
*/
|
||||
#define SYS_GET_IRCTRIM_INT_FLAG() (SYS->IRCTRIMINT)
|
||||
|
||||
/**
|
||||
* @brief Clear HIRC trim flag
|
||||
* @param[in] u32IRCTrimFlg is HIRC trim flags. Including:
|
||||
* - \ref SYS_IRCTRIMINT_FAIL_INT
|
||||
* - \ref SYS_IRCTRIMINT_32KERR_INT
|
||||
* @return None
|
||||
* @details This macro clear HIRC trim flag.
|
||||
*/
|
||||
#define SYS_CLEAR_IRCTRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRCTRIMINT = u32IRCTrimFlg )
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable register write-protection function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function disable register write-protection function.
|
||||
* To unlock the protected register to allow write access.
|
||||
*/
|
||||
__STATIC_INLINE void SYS_UnlockReg(void)
|
||||
{
|
||||
while(SYS->RegLockAddr != SYS_RegLockAddr_RegUnLock_Msk)
|
||||
{
|
||||
SYS->RegLockAddr = 0x59;
|
||||
SYS->RegLockAddr = 0x16;
|
||||
SYS->RegLockAddr = 0x88;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable register write-protection function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is used to enable register write-protection function.
|
||||
* To lock the protected register to forbid write access.
|
||||
*/
|
||||
__STATIC_INLINE void SYS_LockReg(void)
|
||||
{
|
||||
SYS->RegLockAddr = 0;
|
||||
}
|
||||
|
||||
void SYS_ClearResetSrc(uint32_t u32Src);
|
||||
uint32_t SYS_GetBODStatus(void);
|
||||
uint32_t SYS_GetResetSrc(void);
|
||||
uint32_t SYS_IsRegLocked(void);
|
||||
uint32_t SYS_ReadPDID(void);
|
||||
void SYS_ResetChip(void);
|
||||
void SYS_ResetCPU(void);
|
||||
void SYS_ResetModule(uint32_t u32ModuleIndex);
|
||||
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
|
||||
void SYS_DisableBOD(void);
|
||||
void SYS_EnableIRCTrim(uint32_t u32TrimSel,uint32_t u32TrimEnInt);
|
||||
void SYS_DisableIRCTrim(void);
|
||||
/*@}*/ /* end of group NANO100_SYS_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_SYS_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SYS_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
@@ -0,0 +1,326 @@
|
||||
/**************************************************************************//**
|
||||
* @file timer.h
|
||||
* @version V1.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 14/08/29 7:56p $
|
||||
* @brief Nano100 series TIMER driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __TIMER_H__
|
||||
#define __TIMER_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_TIMER_Driver TIMER Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define TIMER_ONESHOT_MODE (0UL) /*!< Timer working in one shot mode */
|
||||
#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in periodic mode */
|
||||
#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in toggle mode */
|
||||
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in continuous mode */
|
||||
|
||||
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL) /*!< Free counting mode */
|
||||
#define TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_CTL_TCAP_CNT_MODE_Msk) /*!< Trigger counting mode */
|
||||
#define TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_CTL_TCAP_MODE_Msk) /*!< Counter reset mode */
|
||||
|
||||
#define TIMER_CAPTURE_FALLING_EDGE (0UL) /*!< Falling edge trigger timer capture */
|
||||
#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Rising edge trigger timer capture */
|
||||
#define TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Falling edge then rising edge trigger timer capture */
|
||||
#define TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Rising edge then falling edge trigger timer capture */
|
||||
|
||||
#define TIMER_COUNTER_RISING_EDGE (TIMER_CTL_EVENT_EDGE_Msk) /*!< Counter increase on rising edge */
|
||||
#define TIMER_COUNTER_FALLING_EDGE (0UL) /*!< Counter increase on falling edge */
|
||||
|
||||
#define TIMER_TIMEOUT_TRIGGER (0UL) /*!< Timer timeout trigger other modules */
|
||||
#define TIMER_CAPTURE_TRIGGER (TIMER_CTL_CAP_TRG_EN_Msk) /*!< Timer capture trigger other modules */
|
||||
|
||||
/*@}*/ /* end of group NANO100_TIMER_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro is used to set new Timer compared value
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMPR = (u32Value))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to set new Timer prescale value
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF
|
||||
* @return None
|
||||
* @note Clock input is divided by (prescale + 1) before it is fed into timer
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->PRECNT = (u32Value))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to check if specify Timer is inactive or active
|
||||
* @return timer is activate or inactivate
|
||||
* @retval 0 Timer 24-bit up counter is inactive
|
||||
* @retval 1 Timer 24-bit up counter is active
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_TMR_ACT_Msk ? 1 : 0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to start Timer counting
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_TMR_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to stop Timer counting
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_TMR_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer wake-up function
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
* @note To wake the system from power down mode, timer clock source must be ether LXT or LIRC
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_WAKE_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the Timer wake-up function
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_WAKE_EN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the capture pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_TCAP_DEB_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the capture pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_TCAP_DEB_EN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the counter pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_EVNT_DEB_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the counter pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_EVNT_DEB_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer time-out interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
|
||||
{
|
||||
timer->IER |= TIMER_IER_TMR_IE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the Timer time-out interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
|
||||
{
|
||||
timer->IER &= ~TIMER_IER_TMR_IE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer capture trigger interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
|
||||
{
|
||||
timer->IER |= TIMER_IER_TCAP_IE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the Timer capture trigger interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
|
||||
{
|
||||
timer->IER &= ~TIMER_IER_TCAP_IE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function indicates Timer time-out interrupt occurred or not.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer time-out interrupt occurred or not
|
||||
* @retval 0 Timer time-out interrupt did not occur
|
||||
* @retval 1 Timer time-out interrupt occurred
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
|
||||
{
|
||||
return(timer->ISR & TIMER_ISR_TMR_IS_Msk ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the Timer time-out interrupt flag.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->ISR = TIMER_ISR_TMR_IS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function indicates Timer capture interrupt occurred or not.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer capture interrupt occurred or not
|
||||
* @retval 0 Timer capture interrupt did not occur
|
||||
* @retval 1 Timer capture interrupt occurred
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
|
||||
{
|
||||
return(timer->ISR & TIMER_ISR_TCAP_IS_Msk ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the Timer capture interrupt flag.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->ISR = TIMER_ISR_TCAP_IS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function indicates Timer has waked up system or not.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer has waked up system or not
|
||||
* @retval 0 Timer did not wake up system
|
||||
* @retval 1 Timer wake up system
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
|
||||
{
|
||||
return (timer->ISR & TIMER_ISR_TMR_WAKE_STS_Msk ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the Timer wakeup interrupt flag.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->ISR = TIMER_ISR_TMR_WAKE_STS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function gets the Timer capture data.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer capture data value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
|
||||
{
|
||||
return timer->TCAP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function reports the current timer counter value.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
|
||||
{
|
||||
return timer->DR;
|
||||
}
|
||||
|
||||
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
|
||||
void TIMER_Close(TIMER_T *timer);
|
||||
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
|
||||
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
|
||||
void TIMER_DisableCapture(TIMER_T *timer);
|
||||
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
|
||||
void TIMER_DisableEventCounter(TIMER_T *timer);
|
||||
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
|
||||
void TIMER_EnableFreqCounter(TIMER_T *timer,
|
||||
uint32_t u32DropCount,
|
||||
uint32_t u32Timeout,
|
||||
uint32_t u32EnableInt);
|
||||
void TIMER_DisableFreqCounter(TIMER_T *timer);
|
||||
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
|
||||
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
|
||||
|
||||
/*@}*/ /* end of group NANO100_TIMER_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_TIMER_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__TIMER_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,380 @@
|
||||
/**************************************************************************//**
|
||||
* @file uart.h
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 15/06/26 1:36p $
|
||||
* @brief Nano100 Series uart control header file.
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_UART_Driver UART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_UART_EXPORTED_CONSTANTS UART Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UA_LCR constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_WORD_LEN_5 (0) /*!< UART_TLCTL setting to set UART word length to 5 bits */
|
||||
#define UART_WORD_LEN_6 (1) /*!< UART_TLCTL setting to set UART word length to 6 bits */
|
||||
#define UART_WORD_LEN_7 (2) /*!< UART_TLCTL setting to set UART word length to 7 bits */
|
||||
#define UART_WORD_LEN_8 (3) /*!< UART_TLCTL setting to set UART word length to 8 bits */
|
||||
|
||||
#define UART_PARITY_NONE (0x0 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as no parity */
|
||||
#define UART_PARITY_ODD (0x1 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as odd parity */
|
||||
#define UART_PARITY_EVEN (0x3 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as even parity */
|
||||
#define UART_PARITY_MARK (0x5 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to keep parity bit as '1' */
|
||||
#define UART_PARITY_SPACE (0x7 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to keep parity bit as '0' */
|
||||
|
||||
#define UART_STOP_BIT_1 (0x0 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for one stop bit */
|
||||
#define UART_STOP_BIT_1_5 (0x1 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for 1.5 stop bit when 5-bit word length */
|
||||
#define UART_STOP_BIT_2 (0x1 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for two stop bit when 6, 7, 8-bit word length */
|
||||
|
||||
#define UART_TLCTL_RFITL_1BYTE (0x0 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 1 bit */
|
||||
#define UART_TLCTL_RFITL_4BYTES (0x1 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 4 bits */
|
||||
#define UART_TLCTL_RFITL_8BYTES (0x2 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 8 bits */
|
||||
#define UART_TLCTL_RFITL_14BYTES (0x3 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 14 bits */
|
||||
|
||||
#define UART_TLCTL_RTS_TRI_LEV_1BYTE (0x0 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 1 bit */
|
||||
#define UART_TLCTL_RTS_TRI_LEV_4BYTES (0x1 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 4 bits */
|
||||
#define UART_TLCTL_RTS_TRI_LEV_8BYTES (0x2 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 8 bits */
|
||||
#define UART_TLCTL_RTS_TRI_LEV_14BYTES (0x3 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 14 bits */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART RTS LEVEL TRIGGER constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MCSR_LEV_RTS_Pos) /*!< Set RTS is High Level Trigger */
|
||||
#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MCSR_LEV_RTS_Pos) /*!< Set RTS is Low Level Trigger */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UA_FUNC_SEL constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_FUNC_SEL_UART (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set UART Function (Default) */
|
||||
#define UART_FUNC_SEL_LIN (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set LIN Function */
|
||||
#define UART_FUNC_SEL_IrDA (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set IrDA Function */
|
||||
#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set RS485 Function */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_UART_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UART baudrate mode0 register setting value
|
||||
*
|
||||
*/
|
||||
#define UART_BAUD_MODE0 (0)
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UART baudrate mode1 register setting value
|
||||
*
|
||||
*/
|
||||
#define UART_BAUD_MODE1 (UART_BAUD_DIV_16_EN_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param[in] u32SrcFreq UART clock frequency
|
||||
* @param[in] u32BaudRate Baudrate of UART module
|
||||
*
|
||||
* @return UART baudrate mode1 divider
|
||||
*
|
||||
*/
|
||||
#define UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-1)
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode2 divider
|
||||
*
|
||||
* @param[in] u32SrcFreq UART clock frequency
|
||||
* @param[in] u32BaudRate Baudrate of UART module
|
||||
*
|
||||
* @return UART baudrate mode0 divider
|
||||
*/
|
||||
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-1)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write Data to Tx data register
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u8Data Data byte to transmit
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
#define UART_WRITE(uart, u8Data) (uart->THR = (u8Data))
|
||||
|
||||
/**
|
||||
* @brief Read Rx data register
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
*
|
||||
* @return The oldest data byte in RX FIFO
|
||||
*/
|
||||
#define UART_READ(uart) (uart->RBR)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx empty register value.
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Tx empty register value.
|
||||
*/
|
||||
#define UART_GET_TX_EMPTY(uart) (uart->FSR & UART_FSR_TX_EMPTY_F_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx empty register value.
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Rx empty register value.
|
||||
*/
|
||||
#define UART_GET_RX_EMPTY(uart) (uart->FSR & UART_FSR_RX_EMPTY_F_Msk)
|
||||
|
||||
/**
|
||||
* @brief Check specified uart port transmission is over.
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return TE_Flag.
|
||||
*/
|
||||
#define UART_IS_TX_EMPTY(uart) ((uart->FSR & UART_FSR_TE_F_Msk) >> UART_FSR_TE_F_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait specified uart port transmission is over
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FSR) & UART_FSR_TX_EMPTY_F_Msk) >> UART_FSR_TX_EMPTY_F_Pos))
|
||||
|
||||
/**
|
||||
* @brief Check RDA_IF is set or not
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return
|
||||
* 0 : The number of bytes in the RX FIFO is less than the RFITL
|
||||
* 1 : The number of bytes in the RX FIFO equals or larger than RFITL
|
||||
*/
|
||||
#define UART_IS_RX_READY(uart) ((uart->ISR & UART_ISR_RDA_IS_Msk)>>UART_ISR_RDA_IS_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check TX FIFO is full or not
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return
|
||||
* 1 = TX FIFO is full
|
||||
* 0 = TX FIFO is not full
|
||||
*/
|
||||
#define UART_IS_TX_FULL(uart) ((uart->FSR & UART_FSR_TX_FULL_F_Msk)>>UART_FSR_TX_FULL_F_Pos)
|
||||
|
||||
/**
|
||||
* @brief Check RX FIFO is full or not
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return
|
||||
* 1 = RX FIFO is full
|
||||
* 0 = RX FIFO is not full
|
||||
*
|
||||
*/
|
||||
#define UART_IS_RX_FULL(uart) ((uart->FSR & UART_FSR_RX_FULL_F_Msk)>>UART_FSR_RX_FULL_F_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx full register value
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Tx full register value
|
||||
*/
|
||||
#define UART_GET_TX_FULL(uart) (uart->FSR & UART_FSR_TX_FULL_F_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx full register value
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Rx full register value
|
||||
*/
|
||||
#define UART_GET_RX_FULL(uart) (uart->FSR & UART_FSR_RX_FULL_F_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified interrupt
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @param[in] u32eIntSel Interrupt type select
|
||||
* - \ref UART_IER_LIN_IE_Msk : LIN interrupt
|
||||
* - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt
|
||||
* - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt
|
||||
* - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt
|
||||
* - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt
|
||||
* - \ref UART_IER_MODEM_IE_Msk : Modem interrupt
|
||||
* - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt
|
||||
* - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt
|
||||
* - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
#define UART_ENABLE_INT(uart, u32eIntSel) (uart->IER |= (u32eIntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified interrupt
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @param[in] u32eIntSel Interrupt type select
|
||||
* - \ref UART_IER_LIN_IE_Msk : LIN interrupt
|
||||
* - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt
|
||||
* - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt
|
||||
* - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt
|
||||
* - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt
|
||||
* - \ref UART_IER_MODEM_IE_Msk : Modem interrupt
|
||||
* - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt
|
||||
* - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt
|
||||
* - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt
|
||||
* @return None
|
||||
*/
|
||||
#define UART_DISABLE_INT(uart, u32eIntSel) (uart->IER &= ~ (u32eIntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get specified interrupt flag/status
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @param[in] u32eIntTypeFlag Interrupt Type Flag,should be
|
||||
* - \ref UART_ISR_LIN_IS_Msk : LIN interrupt flag
|
||||
* - \ref UART_ISR_ABAUD_IS_Msk : Auto baudrate interrupt flag
|
||||
* - \ref UART_ISR_WAKE_IS_Msk : Wakeup interrupt flag
|
||||
* - \ref UART_ISR_BUF_ERR_IS_Msk : Buffer Error interrupt flag
|
||||
* - \ref UART_ISR_RTO_IS_Msk : Rx time-out interrupt flag
|
||||
* - \ref UART_ISR_MODEM_IS_Msk : Modem interrupt flag
|
||||
* - \ref UART_ISR_RLS_IS_Msk : Rx Line status interrupt flag
|
||||
* - \ref UART_ISR_THRE_IS_Msk : Tx empty interrupt flag
|
||||
* - \ref UART_ISR_RDA_IS_Msk : Rx ready interrupt flag
|
||||
*
|
||||
* @return
|
||||
* 0 = The specified interrupt is not happened.
|
||||
* 1 = The specified interrupt is happened.
|
||||
*/
|
||||
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->ISR & (u32eIntTypeFlag))?1:0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set RTS pin is low
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return None
|
||||
*/
|
||||
static __INLINE void UART_CLEAR_RTS(UART_T* uart)
|
||||
{
|
||||
uart->MCSR |= UART_MCSR_LEV_RTS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RTS pin is high
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return None
|
||||
*/
|
||||
static __INLINE void UART_SET_RTS(UART_T* uart)
|
||||
{
|
||||
uart->MCSR &= ~UART_MCSR_LEV_RTS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear RS-485 Address Byte Detection Flag
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return None
|
||||
*/
|
||||
#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->TRSR |= UART_TRSR_RS485_ADDET_F_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get RS-485 Address Byte Detection Flag
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return RS-485 Address Byte Detection Flag
|
||||
*/
|
||||
#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->TRSR & UART_TRSR_RS485_ADDET_F_Msk) >> UART_TRSR_RS485_ADDET_F_Pos)
|
||||
|
||||
|
||||
void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag);
|
||||
void UART_Close(UART_T* uart );
|
||||
void UART_DisableFlowCtrl(UART_T* uart );
|
||||
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
|
||||
void UART_EnableFlowCtrl(UART_T* uart );
|
||||
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
|
||||
void UART_Open(UART_T* uart, uint32_t u32baudrate);
|
||||
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
|
||||
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
||||
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
|
||||
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
|
||||
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
|
||||
void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
|
||||
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_UART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_UART_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__UART_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,516 @@
|
||||
/**************************************************************************//**
|
||||
* @file usbd.h
|
||||
* @brief NANO100 series USB driver header file
|
||||
* @version 2.0.0
|
||||
* @date 20, September, 2014
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __USBD_H__
|
||||
#define __USBD_H__
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_USBD_Driver USBD Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_USBD_EXPORTED_STRUCTS USBD Exported Structs
|
||||
@{
|
||||
*/
|
||||
typedef struct s_usbd_info
|
||||
{
|
||||
uint8_t *gu8DevDesc; /*!< Device descriptor */
|
||||
uint8_t *gu8ConfigDesc; /*!< Config descriptor */
|
||||
uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
|
||||
uint8_t **gu8HidReportDesc; /*!< Pointer for HID Report descriptor */
|
||||
uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
|
||||
uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
|
||||
} S_USBD_INFO_T;
|
||||
|
||||
/// @cond HIDDEN_SYMBOLS
|
||||
extern S_USBD_INFO_T gsInfo;
|
||||
/// @endcond /* HIDDEN_SYMBOLS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_USBD_EXPORTED_STRUCTS */
|
||||
|
||||
/** @addtogroup NANO100_USBD_EXPORTED_CONSTANTS USBD Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define USBD_BUF_BASE (USBD_BASE+0x100)
|
||||
|
||||
#define USBD_MAX_EP 8
|
||||
|
||||
#define EP0 0 /*!< Endpoint 0 */
|
||||
#define EP1 1 /*!< Endpoint 1 */
|
||||
#define EP2 2 /*!< Endpoint 2 */
|
||||
#define EP3 3 /*!< Endpoint 3 */
|
||||
#define EP4 4 /*!< Endpoint 4 */
|
||||
#define EP5 5 /*!< Endpoint 5 */
|
||||
#define EP6 6 /*!< Endpoint 6 */
|
||||
#define EP7 7 /*!< Endpoint 7 */
|
||||
|
||||
/// @cond HIDDEN_SYMBOLS
|
||||
extern volatile uint32_t g_usbd_UsbConfig;
|
||||
|
||||
/*!<USB Request Type */
|
||||
#define REQ_STANDARD 0x00
|
||||
#define REQ_CLASS 0x20
|
||||
#define REQ_VENDOR 0x40
|
||||
|
||||
/*!<USB Standard Request */
|
||||
#define GET_STATUS 0x00
|
||||
#define CLEAR_FEATURE 0x01
|
||||
#define SET_FEATURE 0x03
|
||||
#define SET_ADDRESS 0x05
|
||||
#define GET_DESCRIPTOR 0x06
|
||||
#define SET_DESCRIPTOR 0x07
|
||||
#define GET_CONFIGURATION 0x08
|
||||
#define SET_CONFIGURATION 0x09
|
||||
#define GET_INTERFACE 0x0A
|
||||
#define SET_INTERFACE 0x0B
|
||||
#define SYNC_FRAME 0x0C
|
||||
|
||||
/*!<USB Descriptor Type */
|
||||
#define DESC_DEVICE 0x01
|
||||
#define DESC_CONFIG 0x02
|
||||
#define DESC_STRING 0x03
|
||||
#define DESC_INTERFACE 0x04
|
||||
#define DESC_ENDPOINT 0x05
|
||||
#define DESC_QUALIFIER 0x06
|
||||
#define DESC_OTHERSPEED 0x07
|
||||
|
||||
/*!<USB HID Descriptor Type */
|
||||
#define DESC_HID 0x21
|
||||
#define DESC_HID_RPT 0x22
|
||||
|
||||
/*!<USB Descriptor Length */
|
||||
#define LEN_DEVICE 18
|
||||
#define LEN_CONFIG 9
|
||||
#define LEN_INTERFACE 9
|
||||
#define LEN_ENDPOINT 7
|
||||
#define LEN_HID 9
|
||||
#define LEN_CCID 0x36
|
||||
|
||||
/*!<USB Endpoint Type */
|
||||
#define EP_ISO 0x01
|
||||
#define EP_BULK 0x02
|
||||
#define EP_INT 0x03
|
||||
|
||||
#define EP_INPUT 0x80
|
||||
#define EP_OUTPUT 0x00
|
||||
|
||||
/*!<USB Feature Selector */
|
||||
#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01
|
||||
#define FEATURE_ENDPOINT_HALT 0x00
|
||||
|
||||
/// @endcond
|
||||
|
||||
#define USBD_WAKEUP_EN USBD_CTL_WAKEUP_EN_Msk /*!< USB Wake-up Enable */
|
||||
#define USBD_DRVSE0 USBD_CTL_DRVSE0_Msk /*!< Drive SE0 */
|
||||
|
||||
#define USBD_DPPU_EN USBD_CTL_DPPU_EN_Msk /*!< USB D+ Pull-up Enable */
|
||||
#define USBD_PWRDN USBD_CTL_PWRDB_Msk /*!< PHY Turn-On */
|
||||
#define USBD_PHY_EN USBD_CTL_PHY_EN_Msk /*!< PHY Enable */
|
||||
#define USBD_USB_EN USBD_CTL_USB_EN_Msk /*!< USB Enable */
|
||||
|
||||
#define USBD_INT_BUS USBD_INTEN_BUSEVT_IE_Msk /*!< USB Bus Event Interrupt */
|
||||
#define USBD_INT_USB USBD_INTEN_USBEVT_IE_Msk /*!< USB usb Event Interrupt */
|
||||
#define USBD_INT_FLDET USBD_INTEN_FLDET_IE_Msk /*!< USB Float Detect Interrupt */
|
||||
#define USBD_INT_WAKEUP USBD_INTEN_WAKEUP_IE_Msk /*!< USB Wake-up Interrupt */
|
||||
|
||||
#define USBD_INTSTS_WAKEUP USBD_INTSTS_WKEUP_STS_Msk /*!< USB Wakeup Interrupt Status */
|
||||
#define USBD_INTSTS_FLDET USBD_INTSTS_FLD_STS_Msk /*!< USB Float Detect Interrupt Status */
|
||||
#define USBD_INTSTS_BUS USBD_INTSTS_BUS_STS_Msk /*!< USB Bus Event Interrupt Status */
|
||||
#define USBD_INTSTS_USB USBD_INTSTS_USB_STS_Msk /*!< USB usb Event Interrupt Status */
|
||||
#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event */
|
||||
#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event */
|
||||
#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event */
|
||||
#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event */
|
||||
#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event */
|
||||
#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event */
|
||||
#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event */
|
||||
#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event */
|
||||
#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event */
|
||||
|
||||
#define USBD_STATE_USBRST USBD_BUSSTS_USBRST_Msk /*!< USB Bus Reset */
|
||||
#define USBD_STATE_SUSPEND USBD_BUSSTS_SUSPEND_Msk /*!< USB Bus Suspend */
|
||||
#define USBD_STATE_RESUME USBD_BUSSTS_RESUME_Msk /*!< USB Bus Resume */
|
||||
#define USBD_STATE_TIMEOUT USBD_BUSSTS_TIMEOUT_Msk /*!< USB Bus Timeout */
|
||||
|
||||
#define USBD_CFG_SSTALL USBD_CFG_SSTALL_Msk /*!< Set Stall */
|
||||
#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */
|
||||
|
||||
#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_EPMODE_Pos)/*!< Endpoint Disable */
|
||||
#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_EPMODE_Pos)/*!< Out Endpoint */
|
||||
#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_EPMODE_Pos)/*!< In Endpoint */
|
||||
#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous */
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_USBD_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compare two input numbers and return maximum one.
|
||||
*
|
||||
* @param[in] a First number to be compared.
|
||||
* @param[in] b Second number to be compared.
|
||||
*
|
||||
* @return Maximum value between a and b.
|
||||
*
|
||||
* @details If a > b, then return a. Otherwise, return b.
|
||||
*/
|
||||
#define Maximum(a,b) ((a)>(b) ? (a) : (b))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compare two input numbers and return minimum one
|
||||
*
|
||||
* @param[in] a First number to be compared
|
||||
* @param[in] b Second number to be compared
|
||||
*
|
||||
* @return Minimum value between a and b
|
||||
*
|
||||
* @details If a < b, then return a. Otherwise, return b.
|
||||
*/
|
||||
#define Minimum(a,b) ((a)<(b) ? (a) : (b))
|
||||
|
||||
/**
|
||||
* @brief Enable USBD engine
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_ENABLE_USB() ((uint32_t)(USBD->CTL |= 0xF))
|
||||
|
||||
/**
|
||||
* @brief Disable USBD engine
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_DISABLE_USB() ((uint32_t)(USBD->CTL &= ~USBD_USB_EN))
|
||||
|
||||
/**
|
||||
* @brief Enable USBD PHY
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_ENABLE_PHY() ((uint32_t)(USBD->CTL |= USBD_PHY_EN))
|
||||
|
||||
/**
|
||||
* @brief Disable USBD PHY
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_DISABLE_PHY() ((uint32_t)(USBD->CTL &= ~USBD_PHY_EN))
|
||||
|
||||
/**
|
||||
* @brief Force USB PHY Transceiver to Drive SE0
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_SET_SE0() ((uint32_t)(USBD->CTL |= USBD_DRVSE0))
|
||||
|
||||
/**
|
||||
* @brief Release SE0
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_CLR_SE0() ((uint32_t)(USBD->CTL &= ~USBD_DRVSE0))
|
||||
|
||||
/**
|
||||
* @brief Set USBD address
|
||||
* @param[in] addr host assign address number
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
|
||||
|
||||
/**
|
||||
* @brief Get USBD address
|
||||
* @param None
|
||||
* @retval USBD address
|
||||
*/
|
||||
#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
|
||||
|
||||
/**
|
||||
* @brief Enable USBD interrupt
|
||||
* @param[in] intr interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
|
||||
|
||||
/**
|
||||
* @brief Get USBD interrupt flag
|
||||
* @param None
|
||||
* @retval interrupt status
|
||||
*/
|
||||
#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
|
||||
|
||||
/**
|
||||
* @brief Clear USBD interrupt
|
||||
* @param[in] flag interrupt flag
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = flag)
|
||||
|
||||
/**
|
||||
* @brief Get USBD Endpoint status
|
||||
* @param None
|
||||
* @retval endpoint status
|
||||
*/
|
||||
#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
|
||||
|
||||
/**
|
||||
* @brief Get USBD bus state
|
||||
* @param None
|
||||
* @retval bus status
|
||||
*/
|
||||
#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->BUSSTS & 0xf))
|
||||
|
||||
/**
|
||||
* @brief check cable connect state
|
||||
* @param None
|
||||
* @retval connect / disconnect
|
||||
*/
|
||||
#define USBD_IS_ATTACHED() ((uint32_t)(USBD->BUSSTS & USBD_BUSSTS_FLDET_Msk))
|
||||
|
||||
/**
|
||||
* @brief Stop USB endpoint transaction
|
||||
* @param[in] ep endpoint
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_CLRRDY_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set USB data1 token
|
||||
* @param[in] ep endpoint
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQ_SYNC_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set USB data0 token
|
||||
* @param[in] ep endpoint
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQ_SYNC_Msk))
|
||||
|
||||
/**
|
||||
* @brief Set USB payload size (IN data)
|
||||
* @param[in] ep endpoint
|
||||
* @param[in] size IN transfer length
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
|
||||
|
||||
/**
|
||||
* @brief Get USB payload size (OUT data)
|
||||
* @param[in] ep endpoint
|
||||
* @retval received data length
|
||||
*/
|
||||
#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
|
||||
|
||||
/**
|
||||
* @brief config endpoint
|
||||
* @param[in] ep endpoint
|
||||
* @param[in] config config value
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
|
||||
|
||||
/**
|
||||
* @brief Set buffer for USB endpoint
|
||||
* @param[in] ep endpoint
|
||||
* @param[in] offset buffer offset
|
||||
* @retval None
|
||||
*/
|
||||
#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
|
||||
|
||||
/**
|
||||
* @brief Get buffer for USB endpoint
|
||||
* @param[in] ep endpoint
|
||||
* @retval buffer offset
|
||||
*/
|
||||
#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
|
||||
|
||||
/**
|
||||
* @brief Set USB endpoint stall state
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
|
||||
*
|
||||
*/
|
||||
#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_SSTALL_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear USB endpoint stall state
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
|
||||
*/
|
||||
#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= ~USBD_CFG_SSTALL_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get USB endpoint stall state
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID.
|
||||
*
|
||||
* @retval 0 USB endpoint is not stalled.
|
||||
* @retval Others USB endpoint is stalled.
|
||||
*
|
||||
* @details Get USB endpoint stall state of the specified endpoint ID.
|
||||
*
|
||||
*/
|
||||
#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_SSTALL_Msk)
|
||||
|
||||
/**
|
||||
* @brief To support byte access between USB SRAM and system SRAM
|
||||
*
|
||||
* @param[in] dest Destination pointer.
|
||||
*
|
||||
* @param[in] src Source pointer.
|
||||
*
|
||||
* @param[in] size Byte count.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
|
||||
*
|
||||
*/
|
||||
static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size)
|
||||
{
|
||||
while (size--) *dest++ = *src++;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set USB endpoint stall state
|
||||
*
|
||||
* @param[in] epnum USB endpoint number
|
||||
* @return None
|
||||
*
|
||||
* @details Set USB endpoint stall state, endpoint will return STALL token.
|
||||
*/
|
||||
static __INLINE void USBD_SetStall(uint8_t epnum)
|
||||
{
|
||||
uint32_t u32CfgAddr;
|
||||
uint32_t u32Cfg;
|
||||
int i;
|
||||
|
||||
for (i=0; i<USBD_MAX_EP; i++)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||
u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
|
||||
|
||||
if((u32Cfg & 0xf) == epnum)
|
||||
{
|
||||
*((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg | USBD_CFG_SSTALL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear USB endpoint stall state
|
||||
*
|
||||
* @param[in] epnum USB endpoint number
|
||||
* @return None
|
||||
*
|
||||
* @details Clear USB endpoint stall state, endpoint will return ACK/NAK token.
|
||||
*/
|
||||
static __INLINE void USBD_ClearStall(uint8_t epnum)
|
||||
{
|
||||
uint32_t u32CfgAddr;
|
||||
uint32_t u32Cfg;
|
||||
int i;
|
||||
|
||||
for (i=0; i<USBD_MAX_EP; i++)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||
u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
|
||||
|
||||
if((u32Cfg & 0xf) == epnum)
|
||||
{
|
||||
*((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg & ~USBD_CFG_SSTALL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get USB endpoint stall state
|
||||
*
|
||||
* @param[in] epnum USB endpoint number
|
||||
* @retval 0 USB endpoint is not stalled.
|
||||
* @retval non-0 USB endpoint is stalled.
|
||||
*
|
||||
* @details Get USB endpoint stall state.
|
||||
*/
|
||||
static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
|
||||
{
|
||||
uint32_t u32CfgAddr;
|
||||
uint32_t u32Cfg;
|
||||
int i;
|
||||
|
||||
for (i=0; i<USBD_MAX_EP; i++)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||
u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
|
||||
|
||||
if((u32Cfg & 0xf) == epnum)
|
||||
break;
|
||||
}
|
||||
return (u32Cfg & USBD_CFG_SSTALL);
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
extern volatile uint8_t g_usbd_RemoteWakeupEn;
|
||||
|
||||
typedef void (*VENDOR_REQ)(void); /*!<USB Vendor request callback function */
|
||||
|
||||
typedef void (*CLASS_REQ)(void); /*!<USB Class request callback function */
|
||||
|
||||
typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!<USB Standard request "Set Interface" callback function */
|
||||
typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
|
||||
void USBD_Start(void);
|
||||
void USBD_GetSetupPacket(uint8_t *buf);
|
||||
void USBD_ProcessSetupPacket(void);
|
||||
void USBD_StandardRequest(void);
|
||||
void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
|
||||
void USBD_CtrlIn(void);
|
||||
void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
|
||||
void USBD_CtrlOut(void);
|
||||
void USBD_SwReset(void);
|
||||
void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
|
||||
void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
|
||||
void USBD_LockEpStall(uint32_t u32EpBitmap);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_USBD_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_USBD_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
|
||||
#endif //__USBD_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,162 @@
|
||||
/**************************************************************************//**
|
||||
* @file wdt.h
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 14/08/29 7:56p $
|
||||
* @brief Nano100 series WDT driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WDT_H__
|
||||
#define __WDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_WDT_Driver WDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_WDT_EXPORTED_CONSTANTS WDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^4 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^6 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^8 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^10 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^12 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^14 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^16 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^18 * WDT clocks */
|
||||
|
||||
#define WDT_RESET_DELAY_3CLK (3UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 3 WDT clocks */
|
||||
#define WDT_RESET_DELAY_18CLK (2UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 18 WDT clocks */
|
||||
#define WDT_RESET_DELAY_130CLK (1UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 130 WDT clocks */
|
||||
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 1026 WDT clocks */
|
||||
|
||||
/*@}*/ /* end of group NANO100_WDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro clear WDT time-out reset system flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_RESET_FLAG() (WDT->ISR = WDT_ISR_RST_IS_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro clear WDT time-out interrupt flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->ISR = WDT_ISR_IS_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro clear WDT time-out wake-up system flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->ISR = WDT_ISR_WAKE_IS_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro indicate WDT time-out to reset system or not.
|
||||
* @return WDT reset system or not
|
||||
* @retval 0 WDT did not cause system reset
|
||||
* @retval 1 WDT caused system reset
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_RESET_FLAG() (WDT->ISR & WDT_ISR_RST_IS_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro indicate WDT time-out interrupt occurred or not.
|
||||
* @return WDT time-out interrupt occurred or not
|
||||
* @retval 0 WDT time-out interrupt did not occur
|
||||
* @retval 1 WDT time-out interrupt occurred
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->ISR & WDT_ISR_IS_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro indicate WDT time-out waked system up or not
|
||||
* @return WDT time-out waked system up or not
|
||||
* @retval 0 WDT did not wake up system
|
||||
* @retval 1 WDT waked up system
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->ISR & WDT_ISR_WAKE_IS_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to reset 18-bit WDT counter.
|
||||
* @details If WDT is activated and enabled to reset system, software must reset WDT counter
|
||||
* before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_RESET_COUNTER() (WDT->CTL |= WDT_CTL_WTR_Msk)
|
||||
|
||||
/**
|
||||
* @brief This function stops WDT counting and disable WDT module
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void WDT_Close(void)
|
||||
{
|
||||
WDT->CTL = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables the WDT time-out interrupt
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void WDT_EnableInt(void)
|
||||
{
|
||||
WDT->IER = WDT_IER_IE_Msk;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disables the WDT time-out interrupt
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void WDT_DisableInt(void)
|
||||
{
|
||||
WDT->IER = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
void WDT_Open(uint32_t u32TimeoutInterval,
|
||||
uint32_t u32ResetDelay,
|
||||
uint32_t u32EnableReset,
|
||||
uint32_t u32EnableWakeup);
|
||||
|
||||
/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_WDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__WDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,126 @@
|
||||
/**************************************************************************//**
|
||||
* @file wwdt.h
|
||||
* @version V1.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 14/01/14 5:38p $
|
||||
* @brief Nano100 series WWDT driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WWDT_H__
|
||||
#define __WWDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_WWDT_Driver WWDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup NANO100_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define WWDT_PRESCALER_1 (0UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1 */
|
||||
#define WWDT_PRESCALER_2 (1UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 2 */
|
||||
#define WWDT_PRESCALER_4 (2UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 4 */
|
||||
#define WWDT_PRESCALER_8 (3UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 8 */
|
||||
#define WWDT_PRESCALER_16 (4UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 16 */
|
||||
#define WWDT_PRESCALER_32 (5UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 32 */
|
||||
#define WWDT_PRESCALER_64 (6UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 64 */
|
||||
#define WWDT_PRESCALER_128 (7UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 128 */
|
||||
#define WWDT_PRESCALER_192 (8UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 192 */
|
||||
#define WWDT_PRESCALER_256 (9UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 256 */
|
||||
#define WWDT_PRESCALER_384 (0xAUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 384 */
|
||||
#define WWDT_PRESCALER_512 (0xBUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 512 */
|
||||
#define WWDT_PRESCALER_768 (0xCUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 768 */
|
||||
#define WWDT_PRESCALER_1024 (0xDUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1024 */
|
||||
#define WWDT_PRESCALER_1536 (0xEUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1536 */
|
||||
#define WWDT_PRESCALER_2048 (0xFUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 2048 */
|
||||
|
||||
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to RLD register to reload WWDT counter */
|
||||
/*@}*/ /* end of group NANO100_WWDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup NANO100_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro clear WWDT time-out reset system flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STS = WWDT_STS_RF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro clears WWDT compare match interrupt flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_INT_FLAG() (WWDT->STS = WWDT_STS_IF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is use to get WWDT time-out reset system flag.
|
||||
* @return WWDT reset system or not
|
||||
* @retval 0 WWDT did not cause system reset
|
||||
* @retval 1 WWDT caused system reset
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_RESET_FLAG() (WWDT->STS & WWDT_STS_RF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to indicate WWDT compare match interrupt flag.
|
||||
* @return WWDT compare match interrupt occurred or not
|
||||
* @retval 0 WWDT compare match interrupt did not occur
|
||||
* @retval 1 WWDT compare match interrupt occurred
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_INT_FLAG() (WWDT->STS & WWDT_STS_IF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro to reflects current WWDT counter value
|
||||
* @param None
|
||||
* @return Return current WWDT counter value
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_COUNTER() (WWDT->VAL)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to reload the WWDT counter value to 0x3F.
|
||||
* @param None
|
||||
* @return None
|
||||
* @details After WWDT enabled, application must reload WWDT counter while
|
||||
* current counter is less than compare value and larger than 0,
|
||||
* otherwise WWDT will cause system reset.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_RELOAD_COUNTER() (WWDT->RLD = WWDT_RELOAD_WORD)
|
||||
|
||||
|
||||
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
|
||||
|
||||
|
||||
/*@}*/ /* end of group NANO100_WWDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group NANO100_WWDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group NANO100_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__WWDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
|
||||
Reference in New Issue
Block a user